RU1795520C - Semiconductor on-line storage with correction of information - Google Patents

Abstract

The invention relates to computing. The aim of the invention is to expand the scope of the device. The introduction into the adder device modulo two and the element DISEQUALITY with appropriate connections allows one to detect two-bit and other multiple errors that cannot be corrected by the information correction device, to generate and output a signal for detecting two-bit and other multiple errors for use in the computing device. Such hardware diagnostics of the corrected error makes it possible to apply several levels of fault tolerance in the construction of mass storage devices. 1 ill.

Description

The invention relates to the field of computer engineering, in particular to integrated semiconductor random access memory (RAM) devices.

A semiconductor RAM is known that uses an additive code for correcting single errors, consisting of a storage device (matrix of memory cells for information and control bits), a decoder and an error correction unit that can correct one defect in each word of the storage device.

However, a defect that causes the line bus to short to another substrate bus, for example, a breakdown of a gate insulator, leads to the appearance of errors in many bits of one word and cannot be corrected by the error correction unit.

Known semiconductor random access memory (RAM) with information correction, containing memory cells of information bits of a drive, memory cells of control bits of a drive, address decoder, address amplifiers, drive, information inputs and outputs, write and read enable inputs, correction blocks , OR element, first and second delay elements. In such RAM, a breakdown of the gate gate dielectric of the address transistor leads to the appearance of a two-bit error in the drive word, because the inputs of memory cells of two bits are connected to the output of each address amplifier. However, the selected cells belong to different groups of storage bits and errors in them are corrected by blocks 10 independently of one another, as single-bit ones. When porting a high-capacity memory device, including memory systems on an entire plate, several levels of fault tolerance must be applied. For example, combine from VI

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fault tolerance within individual blocks by using additive code with the replacement of failed blocks. In this case, a failure that appears in a separate unit during operation and is not corrected by the error correction unit should be detected, and information about its presence is necessary for the operation of the unit replacement procedure.

The disadvantage of the described RAM is the lack of a signal indicating the appearance of multi-bit errors during operation, which cannot be corrected by the correction device available inside the block.

An object of the present invention is to expand the scope of a multi-bit error detection device.

This goal is achieved by the fact that adders modulo two and elements of DISABILITY are entered into the semiconductor random access memory with information correction, and the control outputs of the group of each correction block are connected to the inputs of the group of the corresponding adder modulo two, the output of which is connected to the first input of the corresponding element , the second input of which is connected to the control input of the corresponding correction unit, the outputs of the elements DISEQUALITY are outputs Igna multiple device error.

The drawing shows a structural diagram of a semiconductor random access memory with information correction, where 1 is a memory cell of information bits, 2 is a memory cell of control bits, 3 is a decoder, 4 is address amplifiers, 5 is a drive, 6 is information inputs of the device , 7 - information outputs of the device, 8 - input Write permission, 9 - input Read permission, 10-error correction blocks, 11 - OR element, 12 - first delay element, 13 - second delay element, 14 - outputs Multiple error signal. Ki, 15 - adder by module two, 16 - disambiguation elements, 17 - address inputs of the device, each of the correction blocks 10 contains 18 - disambiguation elements of the second type, 19 - information bits recording blocks, 20 - control bits recording block, 21 - information bits registers, 22 - the register of the check bit, 23 - the first type of Disambiguity element, 24 - blocks of reading information bits,

25 is a block reading control bit,

26 is an AND element; 27 is an OR element. Comparison block 30 contains: 28 - elements of DISPARABILITY, 29 - element I. Block

error correction is similar to the prototype correction block. The address inputs of the device 17 are connected to the address inputs of the decoder 3, the outputs of which are connected to the address inputs of the storage cells

1 and 2 drives through addressable amplifiers 4.

The information inputs and outputs of the memory cells are connected to the inputs of the information registers 21 and control 22 times5 rows, as well as to the outputs of the recording blocks 19 and 20. The outputs of the information registers 21 are connected to the inputs of the elements DISEQUALITY of the first kind 23 and to the inputs of the elements DISEQUALITY

0 28 comparison blocks. 30. The output of the register of the check bit 22 is connected to the input of the reading unit of the control bit 25, the output of which is connected to the second inputs of the elements Discontinuity of the first type 23. The outputs of the elements of the Discontinuity 23 are connected to the inputs of the read blocks of 24 information bits, the outputs of which are information device outputs 7.

0 Information inputs 6 of the device are connected to the inputs of the elements DISPARABILITY of the second type 18 and to the second inputs of the elements DISPERSIBILITY - 28 of the comparison unit 30. Output5 The elements of the DISPARABILITY of the second type 18 are connected to the inputs of the recording blocks 19. Second inputs of the blocks 19 information bits and recording blocks 20 control bit connected to the output

0 of the OR element 27. In the block of comparison 30, the outputs of the elements DISEQUALITY 28 inside the comparison block are connected to the inputs of the And 28 element, and outside it form a group of control outputs of the correction block 10, and the control outputs of the group of each correction block are connected to the group inputs of the corresponding adder modulo two 15. The output of the adder 15 is connected to the first input of the element NERVO ASSIGNMENT 16, the second input of which is supplied with the error control signal of the corresponding correction unit from the output of the element And 29 of the comparison unit 30. The output is ementa unequal 16

5 is the output of the −14 multiple error signal of the device. Input 8 The recording permission of the device is connected to the input of the OR element 27 of the correction unit 10 and to the input of the first delay element 12, the output of which is connected to the input of the second element

delay 13 and the input of the element OR 11 of the device. The other input of the OR element 11 is connected to the Read permission input 9 and the input element 11 is connected to the read enable inputs of the information registers 21 and the control bits registers 22. The output of the second delay element 13 is connected to the input of the element And 26 of the correction blocks 10. The other input of the element And 26 is connected to the output of the element And 29 of the comparison unit, The output of the element And 26 is connected to the second input of the element OR 27, with the second inputs of the elements IMPORTANCE 18 and the input of the block check bit records 20.

The device operates as follows.

The signals from the address inputs 17 of the device go to the input of the decoder 3, and from the outputs through the address amplifiers 4 to the address transistors selected by the decoder of memory cells 1 and 2 of the information and control bits. Information signals from the inputs of the device 6 through the elements of the second disambiguity 18 are supplied to the recording units 19 and the signal Recording permission from the input 8 of the device to the recording units through the element OR 27, information is recorded in the selected memory cells. The information is recorded in direct code, because LOGO 0 signal from the output of the AND element 26 is received at the second inputs of the elements. Inequality of the second kind 18 (the signal has not arrived at its input. Recording permission from the output of the delay element). At the same time, the same LOGO signal from the output of the And element 26 through the recording block of the control bit 20 is recorded in the cells 2 of the control bits and indicates that the information is recorded in the direct code. Then, the Recording Resolution signal delayed by the first delay element 12, through the OR element 11 is fed to the read enable inputs of the information and control bit registers, there is a control read of the recorded information and a bitwise comparison of the information recorded and read during the control read in the elements 28 30. If it matches, then at the outputs of all elements 28 LOG 1 signals will be generated, and at the output of element And 29 a LOGO signal indicating the absence of an error ki in written on the address information, and recording the process terminates. Indeed, at the input of the And 26 element, a signal Log 0 and a signal Resolution

recording from the second delay element 13 will not pass to the recording blocks of information and control bits. At the same time, the signals from the outputs of the elements VARIABILITY 28 of the comparison block are fed to the input of the adder modulo two to 15. Modern memory devices most often have byte memory organization, i.e. the information word contains 8 or a multiple of 8 (26, 32, etc.)

0 number of bits. Therefore, when the information recorded and read during the control readout coincides, the adder 15 receives a multiple of 2 number of Log 1 signals from the outputs of the elements 28 and

5, at the output of the adder, a signal Log 0 is generated. The same signal is fed to the second input of the element DISABILITY 16c of the output of element And 29 and at the output 14 of the device a signal Log 0 appears, indicating the absence of a multiple error in this word. If the information recorded and read in the process of check reading at least in one bit does not match, then the output of the block

5 of the comparison, an Error Signal - Log 1 is generated. The Recording Resolution signal from the output of the second delay element 13 through the And 26 element is supplied to the second inputs. disambiguation elements 18 and on

0 inputs Recording permission of recording blocks 19 and 20, causing re-recording of information in cells 1 in the inverse code. In case of a spacious recording in cells 2, a signal Log 1 is recorded at this address, indicating that information in this word is stored in an inverse code. During the control reading, an odd number of Log 1 signals from the outputs of elements 28 are received at the input of adder 15, because

0, the mismatch between the recorded and read information occurred only in one bit of the word, and the signal Log 1 is generated at the output of the adder 15, i.e. both outputs of element 16 receive the same signals

5 Log 1 and at the output 14 of the device, the signal Log 0 is generated again, the error is corrected by the correction unit. If a multiple of 2 errors were detected in the written word during the control reading, then Log 0 will appear at the output of adder 15, and Log 1 will be output at the output of the comparison unit. If the logic signals do not match, the inputs of element 16 generate an output

5 signal Log 1, indicating the detection of multiple errors in this word.

In the read mode, the decoder 3 unlocks the address transistors in the selected memory cells of the information and control bits and, by the read permission signal (input 9) coming through the OR element 11 to the corresponding inputs of the registers 21 and 22, information is read at this address. The information from the register 22 is fed to the input of the reading unit of the control bit 25, and from its output to the inputs of the elements, the first-order Inequality is 23, the first inputs of which are fed from the registers

21.

If the LOG 0 signal is stored in cells 2 at this address, then information from the registers 21 goes to the reader 24 and to the output of the device without inversion. Otherwise, information is inverted stored in cells 1 at this address.

The probability of occurrence of three or more errors in one word of information in general

the case is determined by the technical features of the manufacturing of the memory device, its design and error correction methods. At the current level of technology and rational

microcircuit design, the probability of occurrence of three or more errors in one word is negligible.

A two-bit error is detected in the proposed device, and a signal from the output of the multiple device error 14 can be used to replace the failed address or block in the memory system. In all cases, hardware diagnostics of uncorrectable errors increases the reliability of computer systems.

It should be noted that the proposed multiple error detection device does not require temporary redundancy, and its hardware redundancy is negligible.

Claims (1)

The claims A semiconductor random access memory with information correction, comprising an address decoder, an OR element, first and second delay elements, groups of addressable amplifiers, a drive and correction blocks, the control inputs and outputs of each correction block connected to the Information outputs - the inputs of the bits of the drive group, information the inputs and outputs of the correction blocks are information inputs and outputs of the device, the first recording enable inputs of the correction blocks and the input of the first element, delay ki are combined and are the input of the write enable of the device, the output of the first delay element is connected to the input of the second delay element and the first input of the OR element, the second input of which is the read enable input of the device, the outputs of the OR element are connected to the read enable inputs of the correction blocks, the second, the inputs write permissions which are connected to the output of the second delay element, the inputs of the address decoder are the address inputs of the device, each output of the address decoder is connected to the inputs of the address amplifiers with of the corresponding troupe, the output of which is connected to the address inputs of the same bits of the drive groups, characterized in that, in order to expand the device's field of application by detecting multi-bit errors, modulo two adders and UNEQUALITY elements are introduced into it, and the control outputs of the group of each correction block are connected with the inputs of the group of the corresponding adder modulo two, the output of which is connected to the first input of the corresponding element DISABILITY, the second input of which is connected to the control nym output of the respective correction block elements unequal outputs are the outputs of multiple devices error signal.