RU1780090C - Multiplying pulse-width modulator - Google Patents

Abstract

The invention relates to analog computing and can be used as a multiplication unit, for example, in analog and hybrid computers. The purpose of the invention-17ni - improving accuracy. The device circuit contains sources 1 and 2 of the input signals Ux and Uy connected respectively to the first and second information inputs of the device, the integrator 3 on the operational amplifier, three comparators -1, 5, 6, two logical elements EXCLUSIVE OR 7 and 8, two logical inverters (elements NOT) 9 and 10 and two logical elements And 11 and 12. During operation of the device, output informative intervals are formed in the middle sections of the sawtooth voltage and do not capture the areas of changing the direction of integration, wherever. '^ its expression Nonlinearity is observed and the influence of the fronts of the comparator 4 is observed, thereby achieving an increase in the accuracy of the device. 3 ill.

Description

VI 00 O

Ltd

/ i3o6peiei; s / ie refers to analog computing technology and can be used with BOPO and qualities; -} multiplication unit, Nagfimar, aHajiOroBbix and flexible 8 numeric digits.

Lime -; mind is about; and О1Цм latitudinal-IMPULSE REDDULATOR (УШ1ЛГ Л) CONDITION; 1 II: / i3

psl: lrdog: atg; l -: o soedutnanychkh sum ciru K; W ierpsToos chain and the nij.io cable that is covered by the first one are connected to the percope; icoToporo is connected to the perk;: - to the input cvMN-iMoyiouiero integratosis, the second; a, | to the first input of which the summarizing ego is connected, and the second input is the first input of the input. The second informational .1th input is connected to the second input of the sum MwpyiOLU .arD and the pa pa Da via the block of the 1st processor, controlled by the input (P signals of the second comparator, output and; 1-module 1-stage signal / i produced; CHi . From the start of the PeraO Comparison, the disadvantage is that it has a low level of pressure and is made up for: the presence of the TupyHJiU-ix unit and the input signal signal NZ1 / 1L8 are close to the default value; x: -: 0-4 peiiieHhjj: /; I.C.: /; |: |; 0 .i; O CONDING 6

ss emulating and covered by; 10 b veni; , -iow of pSTrHji- connects the first comparator, yyhol; oTOpi; f for the first input sum -1; /: ru О; this integrator ЕОой Бход KCTOpoiD is the first INLIRATION-NUM input of the CORNER, and the output is, csu. : - I’m talking about the sound through the guy. The resistor is connected to the rsepBOwy input of the second KOMfiapoTops, second m,; oh, 4; g: tf: horn -: srz; the second large-scale re; n1C-op is connected to the second informational unit 8 8 REVIEWS

 while running

the third vi fourth scaling resistors guide | (.lyu7 coo7B8TCHieh: MO to the output cyMiviV: pyOL u, eio injectors to the second information input ViiJi / lM, and the second to the second input are combined and connected to the first input of the third comparator with the second potentials to the outputs of the second and third compartments, connecting to the output, reactive front, R- and S-outlets Tpi- an irregular device, the output of which serves as the output of the CRIMP,

The known modulator is more accurate than the technical solution described above, however, its accuracy remains low, since the duration of each of the two Informative output intervals of CS / lM depends on the moments of the change in the direction of integration, where the non-linearity of the sawtooth voltage at the output of the integrator, which leads leads to additional errors. In addition, the accuracy of the multiplication is significantly affected by the delays and edges of all 1p8x circuit comparators, which lead to the appearance in the output signal leaving, defining additional errors.

The aim of the invention in / 1 is to increase accuracy,

the goal is achieved by the fact that in the angle grinder containing series-connected

a summing integrator and a positive feedback loop, the first com., a parator whose output is connected to the first input of the summing integrator, the second input of which is the first VIHformation input of the CRIM, the output of the summing integrator through the first scale resistor connected to the first input of the second comparator, the second input of the second through the second scale: the first resistor is connected to the second information input of the VLSI, the first outputs of the third and fourth large-scale resistors are connected respectively to the output of the iHTarpaTops and the second information input of the ACHIM, and the second output is combined and connected to the first input of the third comparator, the second input of which is connected to the zero potential bus; , the first and second elements are introduced

EXCLUDING AND L AND, the first and second elements are NOT and the first and second elements AND, with the first comparator connected to the first inputs of the first and second elements EXCLUSIVE HER OR, the second inputs of which are connected to the outputs of the third and second comparators, the outputs of the first and second EXCLUSIVE OR elements, respectively, through the first f, the second elements are NOT connected to the first inputs of the first / 1 of the second AND element, the outputs of which are respectively the first and second outputs of the EAR and the second inputs of the first and W of the elements and the subpar

to the inputs of the second and first elements of i-IE, respectively

In FIG. 1 shows a schematic of the angle-correction circuit: in FIG. 2 shows a fragment of the logical part of the angle-correction circuit when transforming a work

input signals into a digital code; on f1 / (G, 3 shows the timing diagrams of the operation of the CRIS for positive input signals.

The LLL circuit contains sources 1 and 2 of the input signals Ux Uy connected

respectively, to the first and second information inputs of the CRIS, summing the integrator 3 on the operational amplifier, three comparators 4, 5 and 6, two logical elements EXCLUSIVE OR 7 and 8, two logical inverters (elements NOT) 9 and 10 and two logical elements And 11 and 12. The output of the comparator 3 is connected through scale resistors 13, 14 and 15 to the non-inverting inputs of the three comparators 4, 5 and 6. To the inverting input of the integrator 3 are connected through the resistors 16 and 17 the source 1 of the first input signal Ux and the output of the first comparator 4, which is connected also to lane th inputs of the exclusive OR gates 7 and 8 and masschtabny through resistor 18 to its noninverting input. The second inputs of the elements EXCLUSIVE OR 7 and B are connected to the outputs of the comparators 5 and 6, and the outputs of these elements are connected via logic inverters 9 and 10, respectively, to the first inputs of the logical elements And 11 and 12. The second inputs of the elements And 11 and 12 are connected directly to the outputs of the elements INCLUDING OR 8 and 7, respectively. The source 2 of the second input signal Uy through scale resistors 19 and 20 is connected respectively to the non-inverting input of the comparator 5 and to the inverting input of the comparator 6.

At the output of the elements And 11 and 12, positive output pulses of the CRR are formed. With positive input signals Ux and Uy, the pulse duration at the output of the And 12 element is longer than the pulse duration at the output of the And 11 element, therefore the output of the And 12 element can be considered CONDITIONALLY positive, and the output of the And 11 element is negative. When the polarity of one of the input signals changes, the pulse duration at the output of the And 11 element becomes larger than the pulse width at the output of the And 11 element.

The scheme works as follows.

The integrator 3 and comparator 4 form a self-oscillating pulse-width modulator. At the output of the integrator 3, a sawtooth voltage is generated, modulated in speed by the signal Ux. The rate of change of voltage at the output of the integrator 3 with a negative voltage at the output of the comparator 4 and a positive input signal Ux is equal to -Uo + Ux

a at a positive voltage at the output of the comparator

-Uo + UN

where ± Uo is the voltage at the output of comparator 4; TO is the integrator 3. time constant equal to CR17 (assuming that R16 is R17). The comparator 4 switches from one saturation state to another when the voltage at its non-inverting input changes sign, for example, from -I- to -. The potential of a non-inverting input is

Uc

Uv

Ri3 + R18,

p ± Ri3 + R18Ri3 + Ri8

where UM is the voltage at the output of the integrator. Equating to zero, we determine the voltage value at the output of the integrator, corresponding to the switching threshold of the computer Rn

stator 4 (see Fig. 3 a, b) UK ± Us -5-

The comparators 5 and 6 are switched at the moments when the voltage at the output of the integrator 3 is compared with the levels ± Uy, as shown in FIG. 3 c.

The change in the output signal of the comparators 5 and 6 is described by the expressions (with equal resistance Rig) Z5 sign (u + Uy); Z6 sign (UH - Uy),

which is equivalent to comparing the sawtooth voltage Un on comparator 5 with level -Uy, and on comparator Uy. Pulses are generated on the EXCLUSIVE OR logic elements when the voltages on the comparator 4 and on the comparators 5 and 6 do not coincide in sign (Fig. 3 f. E).

At the outputs of the elements And 11 and 12, the output pulses of the CRIM G1IG2 are formed (see Fig. 3 g. H), which define informative intervals. The duration of these intervals can be determined from the following considerations (see Fig. 3 a, g, h). When the voltage at the output of comparator 4 is negative, the integrator integrates the difference -Uo + Ux in a positive direction from the UK level to the + UK level.

Interval r i corresponds to a change in the integrator voltage from -Uy to + Uy, i.e. on 2Uy with a speed of Vi. From where the time interval ri can be defined as the ratio of the voltage change (path) to speed:

2Uy 2Uy

   vi-iJo-u; ° It is similarly determined 12. which corresponds to a change in the integrator voltage from to -Uy with a positive voltage at the output of the comparator 4,

2 V2 Uo + Ux The difference in the durations of these intervals is

Uxuv

ri G2 4ToyG

and

The duration of the conversion cycle is determined by changing the integrator voltage by 2UK (from -UK to + UK with CTbioVi soon and from + UK to -UK with speed V2). It can be determined by replacing in the expressions n and T2 Uy by UK and summing the obtained intervals

2U, 2U.

+ That

Uo-b Ux

Uo-ux

UK Up

The relative difference in the durations of the output mm pulses is

 G1-g y.

TC Uo UK

As follows from the description of the operation of the CSLM and timing diagrams, output informative intervals are formed in the middle sections of the sawtooth voltage and do not capture the areas of the change in the direction of the mn-airgrower, where the non-linearity is most pronounced and the greatest influence of the comparator 4 edges is observed, which increases the accuracy of the work of the CSLM. The presence of two, not four, as in analog devices, informative intervals also helps to increase the accuracy of its operation.

It can be shown that the accuracy of the proposed angle grinder is significantly less influenced by the delay of the comparators than in the prototype device. So, if we assume that the delays of all comparators when switching in the positive and negative directions are equal, then the delays of the comparators 5 and 6 do not affect the conversion accuracy at all, and the switching delays of the comparator 4 do not introduce non-linearity errors, but introduce only a small multiplicative error.

In many applications of VLSI, its output signal is converted to a digital code by filling informative time intervals with pulses from a reference frequency generator (RFC). This can also be done in the circuit of FIG. 1 by applying to the third inputs of the elements And pulses GOCH. However, such direct conversion often leads to significant errors due to cutting of the counted pulses by the pulse fronts. defining informative intervals. In order to eliminate this error, informative time intervals are linked to the pulses of the reference frequency. In FIG. Figure 2 shows a fragment of a circuit for this binding. In this circuit, the outputs of logic gates EXCLUSIVE OR 7 and 8 are connected to the D-inputs of two D-flip-flops 21 and 22, the C-inputs of these triggers are connected to the direct output of GFC 23. The direct outputs of the triggers 21 and 22 are connected to the first inputs of AND 11 and 12, and inverse with the second inputs of AND elements, but in the reverse order. The third inputs of the elements And 11 and 12 are connected and connected 5. are with the inverse output of the GOCH.

In this scheme, output informative intervals are formed not at the moment of changing the logic level at the output of the elements EXCLUSIVE OR 7 and 8, but in

0 the moment of arrival of the front of the first pulse of the frequency band after switching these elements. At the same time, the informative time interval is always equal to an integer number of impulse impulses. The filling of these intervals occurs with GOCH pulses shifted by 1/2 of their period. In this case, the circuit never cuts the impulse of an RFP by the fronts of informative intervals, which increases the accuracy of

0 of the circuit, as well as the stability of the pulse counters, which count the number of filling pulses.

Claims (1)

SUMMARY OF THE INVENTION A pulse-width multiplier modulator comprising a summing integrator in series and positively coupled to a first comparator, the output of which is connected to the first input of the summing 0 integrator, the second input of which is the first information input of the device, the output of the summing integrator through the first scale resistor is connected to the first input of the second comparator, the second 5, the input of which through the second scale resistor is connected to the second information input of the device, the first conclusions of the third and fourth scale resistors are connected respectively to the output 0 summing integrator and the second information input of the device, and the second conclusions are connected and connected to the first input of the third comparator, the second input of which is connected to the bus of zero potential. characterized in that. in order to improve accuracy, the first and second elements are EXCLUSIVE OR, the first and second elements are NOT, and the first and second elements are I. The output of the first comparator is connected to the first inputs the first and second EXCLUSIVE OR elements, the second inputs of which are connected to the outputs of the third and second comparators, the outputs of the first and second EXCLUSIVE OR elements, respectively, through the first and second elements are NOT connected to the first inputs of the first and second AND elements, the outputs of which are respectively the first and the second outputs of the device, and the second inputs of the first and second elements AND are connected to the inputs of the second and first elements, respectively. -L. FIG. g