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KR970029748A - Reference voltage generation circuit of semiconductor device - Google Patents

Reference voltage generation circuit of semiconductor device Download PDF

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Publication number
KR970029748A
KR970029748A KR1019950040655A KR19950040655A KR970029748A KR 970029748 A KR970029748 A KR 970029748A KR 1019950040655 A KR1019950040655 A KR 1019950040655A KR 19950040655 A KR19950040655 A KR 19950040655A KR 970029748 A KR970029748 A KR 970029748A
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South Korea
Prior art keywords
reference voltage
gate
terminal
drain
mos transistor
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KR1019950040655A
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Korean (ko)
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KR0172436B1 (en
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원종학
경계현
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김광호
삼성전자 주식회사
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Priority to KR1019950040655A priority Critical patent/KR0172436B1/en
Publication of KR970029748A publication Critical patent/KR970029748A/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

본 발명은 반도체 장치등을 위한 기준전압 발생회로에 관한 것으로, 특히 엔엔모오스 트랜지스터와 양의 온도계수를 가지는 온도보상회로를 가지고 온도, 공정 및 외부의 공급전압의 레벨이 변화더라도 변화의 값을 자동적으로 보상하여 일정한 레벨의 기준전압을 발생하는 기준전압 발생회로에 관한 것이다. 상기의 기준전압 발생회로는 상기 전원전압이 입력되는 단자로부터 상기 기준전압이 출력되는 기준전압단자의 사이에 직렬 접속되어 전류를 공급하는 제1, 제2저항과, 상기 기준전압단자와 접지단자의 사이에 드레인-소오스 채널이 접속되어 게이트로 입력되는 제어전압에 따라 상기 기준전압단자의 레벨을 제어하는 제1엔모오스 트랜지스터와, 상기 제2저항과 상기 제1엔모오스 트랜지스터의 게이트 사이에 드레인-소오스 채널이 접속되며 상기 제1 및 제2저항의 접속노드에 게이트가 접속된 제2엔모오스 트랜지스터와, 상기 기준전압단자로부터 출력되는 기준전압을 온도변화에 적응적으로 분압하여 온도보상제어전압을 출력하는 온도보상수단과, 상기 제1엔모오스 트랜지스터의 게이트와 상기 접지단자의 사이에 드레인-소오스 채널이 접속되며 게이트가 상기 온도보상수단의 출력노드에 접속되어 상기 제1엔모오스 트랜지스터의 게이트로 입력되는 제어전압을 제어하는 제3엔모오스 트랜지스터로 구성된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generating circuit for a semiconductor device and the like. In particular, the present invention has a temperature compensation circuit having an NMOS transistor and a positive temperature coefficient, so that a change in temperature, process, and external supply voltage can be obtained. The present invention relates to a reference voltage generating circuit that automatically compensates and generates a reference voltage at a constant level. The reference voltage generating circuit includes first and second resistors connected in series between a terminal from which the power supply voltage is input and a reference voltage terminal to which the reference voltage is output, and a current of the reference voltage terminal and the ground terminal. A drain-source channel is connected between the first NMOS transistor for controlling the level of the reference voltage terminal according to a control voltage input to the gate, and a drain- between the second resistor and the gate of the first NMOS transistor. The second compensation transistor is connected to a source channel connected to a gate of the first and second resistors, and the reference voltage output from the reference voltage terminal is adaptively divided to change the temperature compensation control voltage. A drain-source channel is connected between the output temperature compensation means and a gate of the first NMOS transistor and the ground terminal. It is composed of a third NMOS transistor connected to an output node of the temperature compensation means to control a control voltage input to the gate of the first NMOS transistor.

Description

반도체 장치의 기준전압 발생회로Reference voltage generation circuit of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 기준전압 발생회로의 실시예의 상세 구성도.3 is a detailed configuration diagram of an embodiment of a reference voltage generating circuit according to the present invention.

Claims (6)

외부로부터 공급되는 전원전압을 입력하여 그 보다 더 낮은 기준전압을 발생하는 반도체 장치의 기준전압발생회로에 있어서, 상기 전원전압이 입력되는 단자로부터 상기 기준전압이 출력되는 기준전압단자의 사이에 직렬 접속되어 전류를 공급하는 제1, 제2저항과, 상기 기준전압단자와 접지단자의 사이에 드레인-소오스 채널이 접속되어 게이트로 입력되는 제어전압에 따라 상기 기준전압단자의 레벨을 제어하는 제1모오스 트랜지스터와, 상기 제2저항과 상기 제1모오스 트랜지스터의 게이트 사이에 드레인-소오스 채널이 접속되며 상기 제1 및 제2저항의 접속노드에 게이트가 접속된 제2모오스 트랜지스터와, 상기 기준전압단자로부터 출력되는 기준전압을 온도변화에 적응적으로 분압하여 온도보상제어전압을 출력하는 온도보상수단과, 상기 제1모오스 트랜지스터의 게이트와 상기 접지단자의 사이에 드레인-소오스 채널이 접속되며 게이트가 상기 온도보상수단의 출력노드에 접속되어 상기 제1모오스 트랜지스터의 게이트로 입력되는 제어전압을 제어하는 제3모오스 트랜지스터로 구성함을 특징으로 하는 반도체 장치의 기준전압 발생회로.In a reference voltage generation circuit of a semiconductor device which inputs a power supply voltage supplied from an external source and generates a lower reference voltage, a series connection is performed between a terminal from which the power supply voltage is input and a reference voltage terminal from which the reference voltage is output. First and second resistors for supplying current and a drain-source channel connected between the reference voltage terminal and the ground terminal to control the level of the reference voltage terminal according to a control voltage input to the gate A second MOS transistor having a drain-source channel connected between a transistor, the second resistor and a gate of the first MOS transistor, and having a gate connected to a connection node of the first and second resistors, and from the reference voltage terminal. Temperature compensation means for adaptively dividing the output reference voltage according to temperature change and outputting a temperature compensation control voltage; A third MOS transistor is connected between a gate of the switch transistor and the ground terminal, and a drain-source channel is connected to an output node of the temperature compensation means to control a control voltage input to the gate of the first MOS transistor. A reference voltage generation circuit of a semiconductor device, characterized in that the configuration. 제1항에 있어서, 상기 온도보상수단은, 상기 기준전압 출력단자에 일측이 접속된 제3저항과, 상기 제3저항의 타측과 접지단자의 사이에 드레인-소오스 채널이 접속되며 게이트가 상기 기준전압 출력단자에 접속된 제4모오스 트랜지스터로 구성되어 상기 제3저항과 제4모오스 트랜지스터의 채널저항에 의해 상기 기준전압을 분압하여 상기 제3모오스 트랜지스터의 게이트에 온도보상 제어전압을 공급함을 특징으로 하는 반도체 장치의 기준전압 발생회로.2. The temperature compensation means of claim 1, wherein the temperature compensating means comprises: a third resistor having one end connected to the reference voltage output terminal, and a drain-source channel connected between the other side of the third resistor and the ground terminal; And a fourth MOS transistor connected to a voltage output terminal to divide the reference voltage by the third resistance and the channel resistance of the fourth MOS transistor to supply a temperature compensation control voltage to the gate of the third MOS transistor. A reference voltage generating circuit of a semiconductor device. 제1항 또는 제2항에 있어서, 상기 기준전압 발생회로내의 모든 모오스 트랜지스터들은 양의 온도계수를 가짐을 특징으로 하는 반도체 장치의 기준전압 발생회로.The reference voltage generator circuit of claim 1, wherein all the MOS transistors in the reference voltage generator circuit have a positive temperature coefficient. 제1항 또는 제2항에 있어서, 게이트가 상기 전원전압에 접속되어 있으며 드레인-소오스의 채널이 상기 제3모오스 트랜지스터의 소오스와 상기 접지단자의 사이에 직렬 접속된 제5 및 제6모오스 트랜지스터를 더포함함을 특징으로 하는 반도체 장치의 기준전압 발생회로.The fifth and sixth transistors of claim 1 or 2, wherein a gate is connected to the power supply voltage, and a drain-source channel is connected in series between the source of the third transistor and the ground terminal. And a reference voltage generating circuit of the semiconductor device. 제5항에 있어서, 상기 제5 및 제6모오스 트랜지스터를 각각은 양의 온도계수를 가지는 N채널형 모오스 트랜지스터임을 특징으로 하는 반도체 장치의 기준전압 발생회로.6. The reference voltage generator of claim 5, wherein each of the fifth and sixth MOS transistors is an N-channel MOS transistor having a positive temperature coefficient. 제6항에 있어서, 상기 제5모오스 트랜지스터의 드레인-소오스 채널의 사이에는 융단가능한 퓨즈가 더 접속됨을 특징으로 하는 반도체 장치의 기준전압 발생회로.7. The reference voltage generator circuit of claim 6, wherein a fused fuse is further connected between the drain and source channels of the fifth MOS transistor. ※ 참고사항:최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950040655A 1995-11-10 1995-11-10 Reference voltage generation circuit of semiconductor device KR0172436B1 (en)

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KR0172436B1 KR0172436B1 (en) 1999-03-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990065308A (en) * 1998-01-12 1999-08-05 윤종용 Reference voltage generator

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000002771A (en) * 1998-06-23 2000-01-15 윤종용 Reference voltage generating circuit of a semiconductor device
KR20020091958A (en) * 2001-06-01 2002-12-11 삼성전자 주식회사 Circuit for generating internal voltage of semiconductor memory device
KR20190077161A (en) 2017-12-23 2019-07-03 모젼스랩(주) Creation and providing system of realistic mixed reality

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990065308A (en) * 1998-01-12 1999-08-05 윤종용 Reference voltage generator

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