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KR970013073A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR970013073A
KR970013073A KR1019950024983A KR19950024983A KR970013073A KR 970013073 A KR970013073 A KR 970013073A KR 1019950024983 A KR1019950024983 A KR 1019950024983A KR 19950024983 A KR19950024983 A KR 19950024983A KR 970013073 A KR970013073 A KR 970013073A
Authority
KR
South Korea
Prior art keywords
insulating film
conductive layer
sog
forming
contact hole
Prior art date
Application number
KR1019950024983A
Other languages
Korean (ko)
Other versions
KR0157893B1 (en
Inventor
박래학
Original Assignee
문정환
엘지반도체 주식회사
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Publication date
Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR1019950024983A priority Critical patent/KR0157893B1/en
Publication of KR970013073A publication Critical patent/KR970013073A/en
Application granted granted Critical
Publication of KR0157893B1 publication Critical patent/KR0157893B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자 제조방법에 관한 것으로 제1 전도층이 형성되어 있는 절연막 상에 제1 절연막 상기 제1절연막 위에 SOG 및, 상기 SOG 위에 제 2 절연막을 형성하는 공정과; 주변회로부 상의 제1 전도층에 대응되는 영역의 제1 절연막, SOG 및, 제2 절연막을 시작하여 접촉 홀을 형성하는 공정과; 상기 접촉 홀 측면에 절연막 측벽을 형성하는 공정과; 상기 접촉 홀에 제2 전도층을 형성하는 공정 및; 상기 제2 전도층과 제2 절연막 상에 제3 전도층을 형성하는 공정을 구비하며 소자 제조를 완료하므로써, 1) SOG를 이용한 평탄화 공정시 필수적으로 요구되는 에치백 공정을 스킵(skip)할 수 있어, 에치백시 야기되던 평탄도 저하 문제나 식각 선택성을 이용한 식각 공정의 어려움 및 좁은 전도층패턴 스페이서에 증착된 얇은 CVD 산화막 위에서의 SOG 에치백에 따른 공정 마진 감소 등과 같은 제반 문제점들을 해제거할 수 있게 될 뿐 아니라, 2) SOG를 이용한 평탄화 공정시 넌-에치백 공정으로 인하여 야기되는 접촉 홀의 포이저니 현상 및 콘택 저항 증가현상을 제거할 수 있게 되어 SOG와 제2 전도층 사이에서 문제시되던 소자의 특성 저하문제를 개선할 수 있게 된다.The present invention relates to a method for fabricating a semiconductor device, comprising: forming a first insulating film (SOG) on the first insulating film and a second insulating film on the SOG on the insulating film on which the first conductive layer is formed; Forming a contact hole starting with the first insulating film, the SOG, and the second insulating film in a region corresponding to the first conductive layer on the peripheral circuit portion; Forming an insulating film sidewall on the contact hole side; Forming a second conductive layer in the contact hole; Comprising the step of forming a third conductive layer on the second conductive layer and the second insulating layer and by completing the device manufacturing, 1) it is possible to skip the etchback process is required in the planarization process using SOG This eliminates problems such as flatness degradation caused by etch back, difficulty in etching using etch selectivity, and process margin reduction due to SOG etch back on thin CVD oxide deposited on narrow conductive layer pattern spacers. In addition, 2) it was possible to eliminate the poisony of the contact hole and the increase in contact resistance caused by the non-etch back process in the planarization process using the SOG, thereby causing a problem between the SOG and the second conductive layer. The problem of deterioration of the properties can be improved.

Description

반도체 소자 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2(가)도는 내지 제2(바)도는 본 발명에 따른 반도체 소자 제조공정을 도시한 공정수순도.2 (a) to 2 (bar) is a process flowchart showing a semiconductor device manufacturing process according to the present invention.

Claims (4)

제1 전도층이 형성되어 있는 절연막 상에 제1 절연막, 상기 제1절연막 위에 SOG 및, 상기 SOG위에 제2 절연막을 형성하는 공정과; 주변회로부 상의 제1 전도층에 대응되는 영역의 제1 절연막, SOG 및, 제2 절연막을 식각하여 접촉 홀을 형성하는 공정과; 상기 접촉 홀 측면에 절연막 측벽을 형성하는 공정과; 상기 접촉 홀에 제2 전도층을 형성하는 공정 및; 상기 제2 전도층과 제2 절연막 상에 제3 전도층을 형성하는 공정을 구비하여 형성되는 것을 특징으로 하는 반도체 소자 제조방법.Forming a first insulating film on the insulating film on which the first conductive layer is formed, SOG on the first insulating film, and a second insulating film on the SOG; Etching the first insulating film, the SOG, and the second insulating film in a region corresponding to the first conductive layer on the peripheral circuit portion to form contact holes; Forming an insulating film sidewall on the contact hole side; Forming a second conductive layer in the contact hole; And forming a third conductive layer on the second conductive layer and the second insulating layer. 제1항에 있어서, 상기 절연막 측벽은 상기 접촉 홀을 포함한 제2 절연막 상에 절연막을 형성하는 공정 및; 상기 절연막을 이방성 식각이니 스터터링 식각 방법으로 식각하는 공정을 더 포함하여 형성되는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the insulating film sidewall comprises: forming an insulating film on the second insulating film including the contact hole; The method of manufacturing a semiconductor device, characterized in that it further comprises the step of etching the insulating film by an anisotropic etching by the stuttering etching method. 제1항 또는 제2항에 있어서, 측벽 형성을 위한 상기 절연막은 100-500Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the insulating film for forming sidewalls is formed to a thickness of 100-500 Å. 제1항에 있어서, 상기 반도체 소자 제조방법은 접촉 홀에 제2 전도층을 형성하는 공정을 실시하기 전, 접촉 홀 하부의 자연산화막을 제거하기 위한 스퍼티링 식각 공정을 더 포함하여 형성되는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the semiconductor device manufacturing method further includes a sputtering etching process for removing a native oxide layer under the contact hole before performing the process of forming the second conductive layer in the contact hole. A semiconductor device manufacturing method characterized in that.
KR1019950024983A 1995-08-14 1995-08-14 Fabricating method of semiconductor device KR0157893B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950024983A KR0157893B1 (en) 1995-08-14 1995-08-14 Fabricating method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950024983A KR0157893B1 (en) 1995-08-14 1995-08-14 Fabricating method of semiconductor device

Publications (2)

Publication Number Publication Date
KR970013073A true KR970013073A (en) 1997-03-29
KR0157893B1 KR0157893B1 (en) 1999-02-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7728923B2 (en) 2005-09-09 2010-06-01 Samsung Electronics Co., Ltd. Backlight unit and display device having the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100457407B1 (en) * 1997-12-30 2005-02-23 주식회사 하이닉스반도체 Method for forming metal interconnection of semiconductor device to improve electrical characteristic of metal interconnection

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7728923B2 (en) 2005-09-09 2010-06-01 Samsung Electronics Co., Ltd. Backlight unit and display device having the same

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KR0157893B1 (en) 1999-02-01

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