KR970009468B1 - Jitter compensation circuit for processing jitter components of reproduced video signal - Google Patents

Abstract

No content.

Description

Jitter Correction Circuit for Processing Jitter Components in Playback Video Signals

1 is a schematic block diagram showing an example of a conventional jitter correction circuit.

FIG. 2 is a timing chart for explaining the operation of the correction circuit shown in FIG.

3 is a block diagram showing the configuration of a timing circuit included in the correction circuit shown in FIG.

4A and 4B are timing charts for explaining the operation of the timing circuit shown in FIG.

5 is a schematic block diagram showing another example of a conventional jitter correction circuit.

6 is a schematic block diagram showing a jitter correction circuit as a first embodiment of the present invention.

7 is a schematic block diagram showing a jitter correction circuit as a second embodiment of the present invention.

8 is a schematic block diagram showing a jitter correction circuit as a third embodiment of the present invention.

9 is a block diagram of a horizontal period detection circuit included in the embodiment of FIG.

FIG. 10 is a block diagram showing a correction signal generation circuit included in the embodiment of FIG.

11 is a typing chart for explaining the operation of the embodiment shown in FIG.

* Explanation of symbols for main parts of the drawings

1: A / D converter 2: timing circuit

3: video delay circuit 4: memory

8 synchronous disconnect circuit 9 jitter detection circuit

10: burst flag generating circuit 11: fixed delay circuit

12 clock phase modulation circuit 13 write start control circuit

14 write control circuit 15 read H generation circuit

16 read control circuit 17 reference clock generation circuit

20: 1H delay circuit 21: subtraction circuit

22: limiter 23: delay circuit

24: horizontal period detection circuit 25: speed error prediction circuit

26: correction signal generation circuit 27: addition circuit

100: jitter correction circuit 200: VTR video signal reproduction circuit

300,400: Terminal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a jitter correction circuit, and in particular, a video signal such as a high-definition television (HDTV) signal reproduced by a video signal reproducing apparatus such as a video tape recorder (hereinafter referred to as a VTR) or a video disk player. The correction circuit which processes the jitter component contained in it.

In general, a reproduced video signal output from a video signal reproducing apparatus such as a VTR or a video disc player is subjected to temporal fluctuation due to various causes. In general, this temporal variation is called jitter. For example, taking the VTR as an example, images reproduced according to various causes such as fluctuations in the tape traveling speed when the video signal is recorded on the tape and / or during playback from the tape, mismatched rotation of the cylinder, shaking during the tape run, etc. The signal contains jitter components. Leaving these jitter components causes screen shake and color mismatch, resulting in deterioration of image quality. Thus, the conventional video signal reproducing apparatus is usually provided with a jitter component correction circuit. As an example of such a jitter correction circuit, a circuit employed in VTR is disclosed in Japanese Patent Laid-Open No. 58-124385.

1 is a schematic block diagram of a conventional jitter correction circuit for such a VTR. In FIG. 1, the jitter correction circuit 100 is built in the VTR itself, receives a reproduced video signal from the video signal reproducing circuit 200 of the VTR, performs jitter correction described later, and reproduces the corrected video signal of the VTR. The video signal is output to the outside via the external output terminal 300 of the VTR, and supplied to a display device (not shown) such as a monitor TV.

The jitter correction circuit 100 shown in FIG. 1 summarizes the jitter component in the reproduced video signal by controlling the start timing of writing the A / D-converted reproduced video information for each horizontal line into the memory. The jitter component is corrected in detail by controlling the timing of A / D conversion of the reproduced video signal. To correct this jitter component, first, the amount of jitter in the reproduced video signal must be detected. The detection of such jitter amount is made by detecting the shift in the phase of the burst signal in consideration of the level of the burst signal in the A / D-converted reproduced video signal described later corresponding to the shift in the phase of the video signal itself.

2 is a timing chart for explaining the operation of the jitter correction circuit 100 shown in FIG. Next, the configuration and operation of a conventional jitter correction circuit will be described with reference to FIGS. 1 and 2. FIG.

First, the reproduced video signal provided to the jitter correction circuit 100 in the video signal reproducing circuit 200 of FIG. 1 is, as shown in FIG. H _sync ), a burst signal, and an image signal (including time-base compressed color signal C and luminance signal Y), in particular, the horizontal synchronization signal and the burst signals are included in the horizontal blanking period. do.

This reproduced video signal is first provided to the A / D converter 7 and A / D converted in synchronization with the reference clock supplied from the reference clock generation circuit 17. The output of the A / D converter 7 is then provided to the synchronous separation circuit 8 and the jitter detection circuit 9. The synchronizing separation circuit 8 detects the timing of the horizontal synchronizing signal in the provided video signal, and generates a negative synchronizing separation pulse at this timing (Fig. 2 (b)). This timing detection usually involves a constant delay from the time of pulse generation. This pulse is provided to the burst flag generator circuit 10 and the fixed delay circuit 11.

The burst flag generation circuit 10 starts to count the reference clock pulses provided by the reference clock generation circuit 17 in correspondence with the provided pulses (FIG. 2B). When the count value reaches a predetermined value, a burst flag pulse as shown in FIG. 2C is generated and provided to the jitter detection circuit 9. The rising timing of the burst flag pulse and its duration are determined in advance so as to correspond to the generation periods of the four burst waves in the center excluding the pulses on both sides of the burst wave for six synchronizations, for example.

On the other hand, the fixed delay circuit 11 also starts counting the reference clock pulses provided by the reference clock generating circuit in correspondence with the provided pulses (FIG. 2B). Then, when the count value reaches a predetermined value, that is, after the end of the burst period, the pulse shown in FIG. 2 (d) is generated at a timing immediately before the video signal period begins, a write start control circuit (described later) 13) to provide.

The jitter detection circuit 9 detects the sampling phase of the burst signal at the level of the A / D converter 7 output (that is, the burst wave) during the burst flag pulse generation period. When temporal fluctuations, i.e., phase shifts, occur in the reproduced video signal, the sampling point of the burst wave fluctuates during A / D conversion, and the level of each sampling point fluctuates. Therefore, the jitter detection circuit 9 calculates a sampling phase at such a sampling level, and outputs an average value of four waves as a signal corresponding to the phase shift amount of the video signal, that is, the jitter amount.

Jitter is assumed to occur within the range of ± n clocks when the reference clock frequency is 2n (n is a positive integer) times the burst frequency. Therefore, the jitter amount detected by the jitter detection circuit 9 also falls within this range.

The detection data output from the jitter detection circuit 9 is, for example, 8 bits of data, the upper 3 bits of which are provided to the write start control circuit 13, and as described later, a large jitter component (an integer number of reference clocks). The lower five bits are provided to the clock phase modulation circuit 12 and the timing circuit 2 to correspond to a period of less than one period of the reference clock (less than one cycle of the reference clock) as described below. Is used for calibration.

The clock phase modulation circuit 12 is a circuit for modulating the phase of the reference clock supplied from the reference clock generation circuit 17. The reproduced video signal supplied from the video signal reproducing circuit 200 is also provided to the A / D converter 1 and A / D converted in synchronization with the phase-modulated clock output to the clock phase modulating circuit 12. Here, the phase modulation circuit 12 immediately controls the abnormal amount of the reference clock to correct the phase shift of one clock cycle or less based on the lower data of the detection data in the jitter detection circuit 9 described above. do.

The output of the A / D converter 1 is then provided to the timing circuit 2. This timing circuit is summarized from the jitter detection circuit 9 in view of the fact that it is difficult to reliably transfer A / D converted data when the phase relationship between the above-described reference clock and the phase modulated clock becomes a specific phase relationship. Such specific phase relationship is detected based on the detection data, thereby controlling the transmission timing of the A / D conversion data. 3 is a block diagram of the configuration of the timing circuit 2, and FIGS. 4A and 4B are timing charts for explaining the principle of operation thereof.

That is, the latch circuit 2a latching the output of the timing circuit 2 A / D converter 1 and the clock phase modulation circuit 12 in FIG. A timing switching circuit 2b for processing sign reversal or the like on the phase modulation clock based on the jitter detection data, and D-flip flops 2c that operate by receiving a reference clock. In the circuit of FIG. 3, the timing switching circuit 2b normally provides the phase modulation clock to the latch circuit 2a as it is, and the latch circuit 2a latches the A / D conversion data at that timing. Here, for example, as shown in FIG. 4A, at the rising timing of the phase modulation clock, the A / D conversion data [FIG. 4A (b)] is latched in the latch circuit 2a, and the data is stored. As shown in Fig. 4A (c), it is assumed that the reference clock is written to the D-flip flop 2c with the rising of the reference clock. By the way, in the phase relationship as shown in Fig. 4A, the transfer operation to the D-flip flop 2c is performed during the writing of the video data, so that accurate data transfer can be realized. Therefore, in the case where the phase relationship as shown in FIG. 4A occurs, as shown in FIG. 4B, if the timing of writing to the latch circuit 2a is shifted by 1/2 cycle without changing the A / D conversion timing, D -Data transfer to the flip flop 2c can be reliably performed.

Therefore, in the timing circuit 2 of FIG. 3, when the jitter detection data shows a specific abnormality relationship as shown in FIG. 4A, the latch circuit 2a is shifted by shifting the phase modulation clock by 1/2 cycle in accordance with the sign inversion. ) To provide.

The output of the timing circuit 2 is delayed to compensate for the time delay accompanying the horizontal synchronization detection described above via the image delay circuit 3 and then written to the memory 4. The write operation and the read operation of the memory 4 are controlled by the write control circuit 14 and the read control circuit 16, respectively. The write start timing of the memory 4 is defined by the write start pulses provided from the write control start circuit 13 to the write control circuit 14.

In more detail, the write start control circuit 13 receives the pulse (FIG. 2D) in the fixed delay circuit 11 to start the counting of the reference clock pulses, and from the jitter detection circuit 9 When the count value determined according to the contents of the upper level data in the detection data is reached, a write start pulse (variable delay pulse) as shown in Fig. 2E is generated and provided to the write control circuit 14. That is, the write start control circuit 13 variably delays the fixed delay output (FIG. 2D) by a time corresponding to the amount of jitter at that time. As a result, the write start pulse (FIG. 2E) is synchronized with the start point in the video signal period without regard to the degree of jitter in each 1H period, so that only the video information of each horizontal line is written in the write control circuit 14 Will be written to the memory 4 under the control of?).

Then, the read start timing of the video information for each horizontal line written in the memory 4 is defined by the read start pulse provided from the read H generation circuit 15 to the read control circuit 16, and the read control is performed. Under the control of the circuit 16, the contents of the memory 4 are read out in synchronization with the reference clock.

The video information read out from the memory 4 is D / A-converted in synchronism with the reference clock by the D / A converter 5 and is output to the outside via the terminal 300 as a reproduced video signal.

By the way, the conventional example of FIG. 1 is equipped with two A / D converters 1 and 7, These A / D converters are not necessary for the operation | movement simultaneously. Therefore, even if only one A / D converter is provided and the clock inputted in the horizontal blanking period and the video signal period is switched, the same operation as in the conventional example of FIG. 1 can be realized.

5 is a schematic block diagram showing an example of a conventional jitter correction circuit including only one A / D converter as described above.

The conventional example shown in FIG. 5 is the same as the conventional example shown in FIG. 1 except for the following. That is, the A / D converter 7 of FIG. 1 is not provided, and the reproduced video signal converted by the A / D converter 1 and passed through the timing circuit 2 again is the synchronous separation circuit 8 and the jitter detection circuit. Is provided in (9). The synchronizing separation circuit 8 detects the horizontal synchronizing timing in the reproduced video signal as in the conventional example of FIG. 1, and provides a pulse synchronized with the burst flag generating circuit 10 and the fixed delay circuit 11 at the same time. The clock switching circuit 18 is also provided. The operation of the burst flag generation circuit 10 and the fixed delay 11 is the same as in the case of FIG.

In addition, the clock which is commonly supplied to the A / D converter 1 and the timing circuit 2 is selected by the first switch S ₁ . The switching of this switch S ₁ is controlled by the clock switching circuit 18. In other words, the clock switching circuit 18 switches the switch S ₁ to the terminal b side during the horizontal blanking period in accordance with the output of the synchronous separation circuit 8, whereby the A / D conversion circuit 1 and the timing circuit are switched. Reference clock from the reference clock generation circuit 17 is supplied to (2). Further, a switch S ₂ which is switched in conjunction with the switch S ₁ is further provided, the switch S ₂ is also switched to the terminal b side during the horizontal blanking period, and the jitter correction data of the timing circuit 2 is changed. Supply is stopped.

In this manner, during the horizontal blanking period, the reproduced video signal A / D converted by the reference clock is provided to the jitter detection circuit 9 through the timing circuit 2, and the jitter detection circuit 9 is as shown in FIG. The jitter detection data is generated based on the average value of the burst sample phases during the burst flag pulse generation period. Then, based on the upper data of the jitter detection data, the write start control circuit 13 defines the start timing of writing the video information into the memory 4, and the phase clock modulation circuit 12 phases the phase based on the lower data. Determine the abnormality of the modulation clock.

When the horizontal blanking period ends and enters the video signals C and Y period, the switches S ₁ and S ₂ are switched to the terminal a side, respectively, in accordance with the signal from the clock switching circuit 18. As a result, the phase modulation clock is supplied to the A / D converter 1 and the timing circuit 2 from the clock phase modulation circuit 12 through the switch S ₁ in common, and the jitter detection is supplied to the timing circuit 2. In the circuit 9, the lower data of the jitter detection data is supplied through the switch S ₂ .

That is, the jitter amount is detected based on the reference clock during the horizontal blanking period in the conventional example of FIG. 5, and during the video signal period, A / D conversion of the reproduced video signal is performed in synchronization with the clock corrected based on this jitter amount. At the same time, the A / D conversion data is written into the memory 4 at a prescribed timing based on the jitter amount.

However, in the conventional example of FIG. 5, it is conceivable that the switching of the switches S _{1 and} S ₂ is necessary before and after the horizontal blanking period, and this hinders accurate jitter correction. For example, due to the switching from the phase modulation clock to the reference clock by the switch S ₁ immediately before the horizontal blanking period, the timing of sampling of the A / D converter 1 changes, resulting in a synchronous separation circuit. In some cases, the horizontal synchronization timing in (8) may not be detected accurately. As described above, when the detection of the horizontal synchronization timing fails, the determination of the burst period and the detection of the jitter amount cannot be performed, and as a result, accurate jitter correction cannot be performed. In addition, for switching from the reference clock to the phase modulation clock by the switch S ₁ at the timing of switching from the horizontal blanking period to the video signal period, the possibility that the image information to be written into the memory 4 will be affected. There is also.

It is therefore an object of the present invention to provide a jitter correction circuit that can accurately and stably correct jitter components included in a reproduced video signal.

Another object of the present invention is to provide a jitter correction circuit capable of simultaneously detecting jitter amount with one A / D converter without establishing a switch means.

In summary, the jitter correction circuit according to the present invention performs A / D conversion of a reproduced video signal in synchronization with a phase modulation clock, detects a burst sampling phase from an A / D converted value of a burst signal in the reproduced video signal, Jitter amount in the reproduced video signal is detected, and jitter correction data is obtained. The latest jitter correction data is calculated based on the latest detected jitter amount and jitter correction data one horizontal period ago. Based on the obtained jitter correction data, the timing of the start of writing of the A / D conversion value of the video signal into the memory is specified so as to eliminate the jitter component, and the phase of the phase modulation clock for A / D conversion is controlled.

Therefore, the main advantage of the present invention is that the A / D conversion of the reproduced video signal is performed only by the phase-modulated clock only without providing switch means, so that one A / D converter provides stable and reliable jitter correction of the reproduced video signal. It can be realized.

6 is a schematic block diagram showing a shutter correction circuit for a VTR according to the first embodiment of the present invention. In FIG. 6, the jitter correction circuit 100 reproduces the reproduced video signal through the terminal 400 in the video signal reproducing circuit 200 (not shown in FIG. 6) of the VTR, as in the conventional example of FIG. For example, the jitter is corrected by receiving the reproduced video signal and output to the outside as the reproduced video signal of the VTR through the output terminal 300. In the following embodiment, the frequency of the burst signal included in the reproduced video signal is assumed to be 1/6 multiplied by the reference clock.

The embodiment shown in FIG. 6 is the same as the conventional example shown in FIG. 5 except for the following. That is, in the embodiment of FIG. 6, the clock switching circuit 18, the switch S ₁ , and the switch S _{2 of} FIG. 5 are not provided, and the A / D converter 1 is separated from the clock phase modulation circuit 12. The A / D conversion is always performed in synchronization with the phase modulation clock of the A, so that the A / D conversion output is provided to the timing circuit 2 in the always operating state. The A / D conversion data output in synchronization with the reference clock from the timing circuit 2 is provided to the video delay circuit 3 and provided to the synchronization separation circuit 8, and the horizontal synchronization timing is detected. The output of the timing circuit 2 is not provided to the jitter detection circuit as shown in FIG. The output of this synchronous separation circuit 8 is provided to the burst flag generator circuit 10 and the fixed delay circuit 11, and the burst flag generator circuit 10 and the fixed delay circuit 11 are respectively a burst flag pulse and a fixed delay. Generate a pulse.

The A / D converted video data delayed by the video delay circuit 3 is written to the memory 4 and input to the jitter detection circuit 9. The jitter detection circuit 9 detects the phase of the A / D conversion data, i.e., the burst sampling signal, during the burst flag pulse generation period, and outputs it as the amount of jitter for the phase modulated clock at that time.

The data thus detected is provided to the negative input of the subtraction circuit 21 in order to detect jitter correction data. The jitter correction data of 1H before held by the 1H delay circuit 20 is input to the positive input of the subtraction circuit 21. The subtraction circuit 21 subtracts jitter detection data from jitter correction data before 1H, and calculates the jitter correction amount. In other words, according to this embodiment, the latest jitter amount detected on the basis of the phase modulated clock corrected before the one horizontal period corresponds to the jitter variation, and therefore, if the jitter amount is subtracted from the jitter correction data before one horizontal period, The amount of jitter to be corrected is calculated. This jitter correction amount, through the limiter 22, the value stays within the range of the predetermined value. Although this predetermined range is set narrower than the response range of the write start control circuit 13, when this response range is wide enough, the limiter 22 may be abbreviate | omitted. The data output from the meter 22 is provided to the write start control circuit 13, the clock phase modulation circuit 12, and the timing circuit 2 as jitter correction data, and as described above, the 1H delay circuit. 20 is stored.

The clock phase modulation circuit 12 detects the lower data for correcting jitter of one clock cycle or less from the provided jitter correction data, thereby appropriately converting an ideal amount of the reference clock to correct such small jitter components. The timing circuit 2 also determines the phase relationship between the phase modulation clock and the reference clock based on the jitter correction lower data, and adjusts the timing as necessary.

In addition, the write start control circuit 13 determines the number of counts of the reference clock based on the higher-order data among the provided jitter correction data, and when the count value of the reference clock pulse reaches this value, the variable delay pulse, that is, write A start pulse is generated and provided to the write control circuit 14. The write control circuit 14 receives this write start pulse and writes the A / D conversion data into the memory 4 line by line. In this way, the write start pulse is not limited to the degree of jitter and coincides with the start point of the video signal period, so that only the video information of each horizontal line is written into the memory 4.

In this way, the image data is written to the memory 4 in synchronization with the horizontal synchronizing signal in the reproduced video signal. The read H generation circuit 15 generates a read start pulse at one horizontal sync and provides the read control circuit 16 to the read control circuit 16, whereby the read control circuit 16 converts the A / D in the memory 4 every one horizontal line. Read the data. The video data read in this way no longer contains the jitter component, and is A / D converted by the A / D converter 5 and output to the outside through the terminal 300.

Although not shown in FIG. 6, in the case of digitally performing various processes after synchronizing the time-sequential color signal C or luminance signal Y in the A / D conversion data by intrinsically extending the time axis, It is necessary to establish such a processing circuit at the front end of the A / D converter 5.

In addition, as described above, the synchronous extraction of the horizontal synchronizing timing by the synchronous separation circuit 8 generally involves a delay, and therefore, the amount of jitter accurate unless the burst signal input to the jitter detection circuit 9 is also delayed a considerable amount. Cannot be detected. In the first embodiment shown in FIG. 6, in order to compensate for this delay by the synchronous separation circuit 8, that is, the occurrence delay of the synchronous separation pulse, the image delay circuit 3 is provided for the purpose of time axis correction or the like. The delay of the video data is used. However, when the delay time of the video delay circuit 3 is not long enough, the generation of the burst flag pulse by the burst flag generation circuit 10 is delayed, and thus, the jitter amount cannot be accurately detected.

7 is a schematic block diagram of the jitter correction circuit according to the second embodiment of the present invention which solves this problem. According to the embodiment of FIG. 7, the output of the timing circuit 2 is delayed by the dedicated delay circuit 23, which is opened independently, so that the image data is output in correspondence with the actual delay time of the synchronous separation circuit 8. As shown in FIG. It can delay and accurately detect jitter. Since this seventh embodiment is the same as the embodiment of FIG. 6 in other respects, the description thereof will not be repeated.

On the other hand, in the above-described first and second embodiments, the phase shift at the start of each horizontal line is adjusted, that is, the phase shift is detected during the horizontal blanking period to detect the shift at the start of the video signal period. It cannot compensate for jitter caused by temporal fluctuations during the video signal period.

8 is a schematic block diagram of a jitter correction circuit according to a third embodiment of the present invention which solves this problem. This embodiment of FIG. 8 is the same as the embodiment of FIG. 7 except for the following. That is, the embodiment of FIG. 8 anticipates the variation of the jitter during the video signal period, and correspondingly changes the phase of the clock continuously during the video signal period.

More specifically, in the embodiment of FIG. 8, the jitter detection circuit 90 includes the 1H delay circuit 20, the subtraction circuit 21, and the limiter circuit 22 of FIG. 7, and the horizontal period detection. The circuit 24, the speed error prediction circuit 25, the correction signal generation circuit 26, and the addition circuit 27 are provided. The horizontal period detecting circuit 24 is a circuit for accurately detecting the horizontal period and outputting the horizontal period data, the means for calculating the horizontal period roughly, the means for calculating the variation in the horizontal period in detail, and the arithmetic processing of both. Means are provided.

9 is a detailed block diagram of such a horizontal period detection circuit 24. As shown in FIG. First, the approximate calculation of the horizontal period will be described. The fixed delay circuit 11 generates a fixed delay pulse at a time delayed by an integral number of the reference clock from the sync separation pulse generated in the sync separation circuit 8, that is, near the end of the horizontal blanking period, and detects the horizontal period. The reset input of the counter 24a in the circuit 24 and the latch input of the latch circuit 24b are provided. The counter 24a counts the reference clock and is reset for each line by a fixed delay pulse, and the count value is latched in the latch circuit 24b at the timing of reset. In other words, the data latched in the latch circuit 24b corresponds almost to the horizontal period, but is still data that still includes temporal shift. In the embodiment of FIG. 8, the clock modulation state of the clock phase modulation circuit 12 is fixed to a specific modulation state during the horizontal synchronizing period of the reproduced video signal. The A / D conversion is performed at a timing of a fixed phase with respect to the reference clock phase.

Next, detailed calculation of the horizontal period will be described. The jitter detection circuit 90 of FIG. 8 detects jitter correction data on the basis of the burst signal level corresponding to the amount of phase displacement during the burst flag pulse generation period, similarly to the embodiment of FIG. 7, and delays 1H in the horizontal period detection circuit. To the circuit 24c and the subtraction circuit 24d. As described above, the range of the phase shift amount detected by the jitter detection circuit 90 is in the range of ± 3 clocks because the burst signal period is set to 6 times the reference clock period, and the detection accuracy is 1/1 of one clock. 32. Therefore, the jitter detection output is detected with 5 bits of precision for a decimal point of 1 clock or less in the range of ± 3 clocks.

The subtraction circuit 24d subtracts the jitter correction data of 1H before held by the 1H delay circuit 24c from the provided jitter correction data, and calculates a detailed variation of horizontal synchronization. The addition circuit 24e adds the approximate horizontal period data in the latch circuit 24b and the detailed fluctuation amounts in the subtraction circuit 24d, thereby calculating a high precision horizontal period, so that the speed error prediction circuit 25 To provide.

The speed error prediction circuit 25 is well known based on the horizontal periods T _nl , T _n-2 , and T _n-3 before 1H, before 2H, and before 3H.

T _n = 3T _nl , -3T _n-2 + T _n-3

Is calculated, and the horizontal period T _n in the line is predicted. Then, in the horizontal period T _n thus predicted, the speed error prediction data DELTA T _n is calculated by subtracting the reference horizontal period T _{0 and} provided to the correction signal generation circuit 26.

10 is a block diagram showing the correction signal generation circuit 26 in detail. This correction signal generation circuit 26 includes a counter 26a that counts the reference clock and is reset by the write start pulse.

The value of this counter 26a is provided to one input of the multiplication circuit 26b. At the other input of the multiplication circuit 26b, the speed error prediction data DELTA T _{n is} provided from the speed error prediction circuit 25, and the multiplication circuit 26b outputs the data DELTA T _n and the counter 26a. And multiplying predetermined coefficients, and supplying a multiplication output that continuously increases or decreases from 0 to? T _n during each video signal period as a correction signal. 11 is a timing chart showing the relationship between the provided reproduced video signal a and this correction signal b.

Next, the addition circuit 27 adds subordinate data relating to jitter correction of one clock or less among the jitter correction data from the jitter detection circuit 90 and correction signals from the correction signal generation circuit 26 and then clocks the clock. Supply to the phase modulation circuit 12 and the timing circuit (2). The clock phase modulation circuit 12 is in a fixed modulation state until jitter correction data is generated, and after generation of jitter correction data, the modulation clock phase at the start of the video signal period is defined, and the phase is again changed during the video signal period. The change is proportional to the speed error prediction data DELTA T _n . In this embodiment, the phase modulation step of the clock phase modulation circuit 12 is composed of, for example, 16 steps.

As described above, according to the third embodiment of the present invention, the phase of the phase modulation clock is continuously changed during the video signal period of each horizontal line, thereby coping with jitter generated during the video signal period.

Claims (13)

A jitter correction circuit for processing jitter components of a reproduced video signal, comprising: means (400) for supplying the reproduced video signal comprising at least a horizontal sync signal component, a burst signal component, and a video signal component during one horizontal period, phase modulation Clock phase modulating means (12) for supplying a clock, A / D converting means (1) for A / D converting the reproduced video signal in synchronization with the phase modulated clock, and the burst signal component by the A / D converting means Jitter detecting means (10,9) for generating jitter detection data for each horizontal period based on the A / D conversion value of the correction data, and correction data for generating jitter correction data for each horizontal period based on the jitter detection data. Generating means (20, 21), a memory (4) for temporarily storing the A / D converted value of the video signal component by the A / D converting means, and the A / D converted value of the video signal component Means (14, 15, 16) for writing to and reading from the memory, and to the memory of the A / D conversion values of the video signal components to cancel the jitter components based on the jitter correction data. Means (11, 13) for defining the timing of writing start of the data; and the correction data generating means generates the latest jitter correction data based on the jitter detection data and the jitter correction data before one horizontal period; And the clock phase modulating means controls the phase of the phase modulated clock to cancel the jitter component based on the jitter correction data. The jitter correction circuit according to claim 1, further comprising means (17) for generating a reference clock, wherein said clock phase modulation means modulates and supplies a phase of said reference clock. 3. The means (2) according to claim 2, characterized by detecting a specific phase relationship between the reference clock and the phase modulated clock based on the jitter correction data and adjusting the transmission timing of the A / D conversion means output. The jitter correction circuit further comprises. 2. The apparatus according to claim 1, further comprising: synchronous separation means (8) for detecting timing of said horizontal synchronization signal component in said A / D conversion means, wherein said jitter detecting means is adapted to the timing of said detected horizontal synchronization signal component. Means (10) for specifying a generation period of said burst signal component on the basis of; and means (9) for obtaining an average level of A / D conversion values of said burst wave during the generation period of said burst signal. Jitter Compensation Circuit. 5. The apparatus according to claim 4, wherein said write start timing defining means generates means (11) for generating a signal delayed by a fixed time at the timing of said detected horizontal synchronizing signal, and said fixed time delayed signal in response to said jitter correction data. And means (13) for generating a write start pulse at a variable time delay and providing the write start pulse to said memory writing means. The jitter according to claim 1, wherein said correction data generating means includes means (20) for holding said jitter correction data before one horizontal period, and means (21) for subtracting the latest jitter detection data. Correction circuit. The jitter correction circuit according to claim 6, wherein the correction data generating means includes a limiter (22) for receiving the subtraction means output. 5. The delay as set forth in claim 4, wherein the delay is provided at the front end of the jitter detecting means and delays the A / D conversion means output by a time equivalent to a delay time involved in timing detection of the horizontal synchronizing signal component by the synchronizing separation means. And a means (3,23). 2. The apparatus according to claim 1, further comprising: means (23, 25, and 26) for predicting the jitter component during the video signal component period and generating a correction signal and adding the jitter correction data and the correction signal to the clock phase modulation means. And a means (27). 10. The horizontal period detecting means (24) according to claim 9, wherein the correction signal generating means detects a horizontal period of the reproduced video signal based on the jitter correction data, and a plurality of horizontal detected by the horizontal period detecting means. Means 25 for predicting an error of the latest horizontal period based on the period, and means 26 for generating the correction signal continuously changing during an image signal period based on the predicted horizontal period error. Jitter correction circuit. 2. The jitter correction circuit according to claim 1, further comprising A / D conversion means (5) for A / D converting a signal A / D conversion value of the video read out from the memory. The jitter correction circuit according to claim 1, wherein the reproduced video signal is an output of a reproduced video signal of a video tape recorder. The jitter correction circuit according to claim 1, wherein the reproduced video signal is an output of a reproduced video signal of a video disc player.

Images