KR970004907Y1 - Digital convergence adjustment device - Google Patents

Abstract

None.

Description

Digital Convergence Control

1 is a conceptual block diagram of a general digital convergence adjustment device

2 is a convergence adjustment screen according to FIG.

3 is a block diagram of a conventional digital convergence adjustment device.

4 is a conventional digital convergence adjustment flow chart

5 is an embodiment of a digital convergence adjustment device according to the present invention

6 is another embodiment of a digital convergence adjustment device according to the present invention

* Explanation of symbols for main parts of the drawings

1: PLL unit 2: Adjustment pattern and adjustment point display generating unit

3: address generator 4: memory

5: CPU 6: interpolator

7: Serial and Parallel Converter 8: Digital Analog Converter

9: amplifier 10: keyboard

11 control unit 100 convergence control unit

110: register 120: switching unit

The present invention relates to a digital convergence adjusting device, and more particularly, to a digital convergence adjusting device capable of shortening the convergence adjusting time and improving the system efficiency.

In general, in a color TV receiver, the electron beam is more concentrated from the center of the cathode ray tube (hereinafter, referred to as a CRT) to the periphery, whereby a phenomenon of deterioration in image quality occurs.

In particular, in a projection type TV using three mono CRTs, a device for concentrating the light in one place is required because the angles of incidence of the light on the screen are different from each other. Conventionally, an analog convergence method using a general passive element is applied. However, in order to solve this problem, the digital convergence method has been proposed, which is shown in FIG.

According to this, first, by using the horizontal and vertical blank signals (VBLK) and (HBLK), the phase lookup loop (hereinafter referred to as PLL) section 1 creates a system clock synchronized with the synchronization signal, and then clocks the clock. The adjustment pattern and adjustment point display as shown in FIG.

Then, an address applied to the memory unit 4 by the address generator 3 is generated using the system clock generated by the PLL unit 1.

The convergence correction data value of the adjustment point is stored in the memory unit 4, and the interpolation unit 6 calculates the convergence correction data value between the adjustment point using the data.

If the CPU 5 obtains this value in software, the interpolation section 6 is not necessary.

The output of the interpolator 6 is converted into parallel data by the serial-to-parallel converter 7, and then converted into an analog signal via the digital analog converter 8.

The output of the digital analog converter 8 is input to the amplifier 9 through a low pass filter LPF, amplified and applied to the convergence yoke CY.

Since the change of current means the change of the magnetic field, the change of the magnetic field is used to adjust the convergence by adjusting the direction of the electron beam.

At the time of convergence correction, the CPU 5 receives the input of the keyboard 10 and manipulates the contents of the memory unit 4 to perform the partial adjustment of the convergence. It becomes possible.

And during the adjustment, the operator adjusts while watching the screen as shown in FIG. 2. FIG. 2 shows the corrected state. In the actual adjustment, it is necessary to check the initial state that is not adjusted at all. Can be implemented.

The conventional technique shown in FIG. 3 is Japanese Patent Laid-Open No. 62-59488.

In FIG. 3, the control unit 11 may be regarded as the combination of the PLL unit 1 and the address generator 3 of FIG. 1, and a clear (hereinafter referred to as CLR) key is added to the keyboard 10. The operation thereof will be described together with the flowchart of FIG.

First, during adjustment, the operator inputs the CRT key of the keyboard 10 to check the convergence free state (convergence correction off state).

The CPU 5 then receives this and clears all correction data in the memory section 4.

This means that the CPU 5 writes the data contents of the memory section 4 to 00H for all addresses.

In this state, since all the correction data of the memory unit 4 is 00, the convergence correction is turned off, and when an arbitrary key is input again, the CPU 5 again transmits the convergence correction data to the memory unit 4. Should be written.

When the CLR key is not input, the CPU 5 can perform adjustment by manipulating the adjustment point correction data of the memory unit 4.

In order to check the convergence free state, the conventional technology described above requires the CPU to move the data from the memory to another place and then write 00 back to the memory when the CLR key is pressed. Since the data must be read and written to memory again, the operator has to wait for this operation time, which is a disadvantage in terms of system efficiency.

And if you have a system with software interpolation, there is a lot of data to write from the CPU to memory, so depending on the CPU speed, you have to wait a long time to return to the original state from the convergence off state. There was a disadvantage of requiring another separate memory to store the correction data.

The present invention has been made to solve this problem, and an object of the present invention is to provide a digital convergence control device which can shorten the return time to the non-convergence state and the correction state, thereby improving the efficiency of the system. In providing.

A feature of the present invention for achieving the above object is a PLL unit for generating a system clock using the horizontal and vertical black signals inputted, and a screen adjustment pattern and an adjustment point using the system clock generated by the PLL unit. An adjustment pattern and an adjustment point display generation unit to display, an address generation unit for generating an address, a memory unit for storing convergence correction data, a CPU controlling the memory unit, and a control signal of the CPU A convergence control unit for outputting correction data of the memory unit or an initial value, a serial-to-parallel converter for converting the output of the convergence control unit into parallel data, and converting the output of the serial-to-parallel converter to an analog signal. A digital analog converter and an amplifier for amplifying the output of the digital analog converter through a low pass filter In the jital con version's adjustment device.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

5 and 6 are circuit diagrams showing one embodiment and another embodiment of the digital convergence adjusting device according to the present invention, and are in parallel with the memory unit 4 of the general digital convergence adjusting device as shown in FIG. The convergence control unit 100 is provided between the converters 7, and some of the blocks shown in FIG. 1 are not shown in the drawing.

In the case of FIG. 5, the convergence control unit 100 includes a plurality of AND gates AND1 -ANDn having one input connected to the memory unit 4 and the CPU 5 in parallel, respectively. a register 110 for storing n bits, one input is connected in parallel to the output terminal of the register 110, a type force is connected in parallel to the memory unit 4, and one input is connected to the memory unit 4; The switching unit 120 includes a plurality of AND gates AND1 -ANDn.

According to the present invention configured as described above, first, when the CLR key is input from the keyboard 10 in the case of FIG. 5, the CPU 5 determines the input key and makes the output terminal OUT low.

Therefore, the outputs of the AND gates AND1-ANDn of the convergence control unit 100 are all low, so in this case, the data value input to the serial-parallel conversion unit 7 is 00 regardless of what data is output from the memory unit 4. Will be

That is, this is the same as clearing all the correction data of the memory section 4 in the prior art.

If an arbitrary key is input, the CPU 5 sets the output terminal OUT to high, and the correction data of the memory unit 4 is transferred to the serial-parallel conversion unit 7 in a normal state to correct the convergence corrected screen. Allow the operator to check.

In addition, in the embodiment according to FIG. 6, when the CLR key of the keyboard 10 is input, the CPU 5 inputs a 00 value to the register 110.

Then, since the outputs Q1-Qn of the register 110 are all zero, the outputs of the AND gates AND1-ANDn of the switching unit 110 go low.

Therefore, even in this case, even if any data is output from the memory unit 4, the data value input to the serial-parallel conversion unit 7 becomes 00, so that the convergence correction off state can be confirmed.

If any key is input, the CPU 5 sets the outputs Q1-Qn of the register 120 high and the outputs of the AND gates AND1-ANDn become high, thereby correcting the data of the memory unit 4. Is transmitted to the serial-to-parallel converter 7 in a normal state.

In addition, when the CPU 5 sets only a specific bit other than 00 to 1, the output of the register 110 corresponding to the bit becomes high, and the output of the AND gate connected thereto becomes high. Is delivered to (7).

This may be used to turn off a specific high or specific low bit.

As described above, the present invention can reduce the adjustment time and improve the efficiency of the digital convergence adjustment, and can clear only any desired bits.

In addition, as in the conventional case, a separate memory for storing correction data in the convergence correction off state is not required.

Claims (4)

A PLL unit for generating a system clock by using input horizontal and vertical blank signals, an adjustment pattern and an adjustment point display generator for displaying a screen adjustment pattern and an adjustment point using the system clock generated by the PLL unit, An address generator for generating an address, a memory unit for storing convergence correction data, a CPU controlling the memory unit, and selectively outputting correction data or initial values of the memory unit according to a control signal of the CPU A converging control unit to convert the output of the converging control unit into parallel data, a digital analog converting unit converting the output of the serial and parallel converting unit into an analog signal, and an output of the digital analog converting unit. Digital convergence adjusting device, characterized in that consisting of an amplifier for amplifying the low pass filter. The digital display device as claimed in claim 1, wherein the convergence control unit comprises a plurality of AND gates each having one input connected in parallel to the memory unit and the CPU, and having an output low when a clear key of the keyboard is input. Convergence adjuster. The register of claim 1, wherein the convergence control unit is configured to control an output under control of the CPU. And a switching unit which is switched in accordance with the output of the register. The digital convergence adjustment device of claim 3, wherein the switching unit comprises a plurality of end gates each having one input connected in parallel to an output of the register and a memory unit.