KR960011857B1 - Semiconductor device and the manufacturing method - Google Patents

Abstract

a first insulating film(31) formed on the surface of a semiconductor device(30) to expose some of the device(30); a first metal layer(32) formed on the surface of the semiconductor device(30) and on a part of the first insulating film(31); a second insulating film(33) formed on the first metal layer(32) and on the first insulating layer(31) to expose a part of the first metal layer(32); a second metal layer(34) formed to cover the exposed first metal layer(32); a first and a second barrier metal layer(35,36) formed on the second metal layer(34); and a first, a second and a third solder bumper(40,41,42) formed on the second barrier metal layer(36).

Description

Semiconductor device and manufacturing method thereof

1 is a cross-sectional view showing a structure in which the solder is electroplated during electroplating.

2 is a cross-sectional view showing bumps formed on a chip as a semiconductor element.

3 is a cross-sectional view showing a state in which a chip is mounted on a substrate.

4 is a cross-sectional view of a solder bump structure formed by the prior art.

5 is a cross-sectional view showing the structure of a solder bump according to the present invention.

6A to 6H are process flowcharts showing a method of forming solder bumps according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a structure of a solder bump used as a terminal electrode of a semiconductor device and a method for manufacturing the same.

In order to meet the rapid growth and high density of hybrid ICs in recent years, a flip chip method using metal projections called bumps instead of wires is used for pads of semiconductor devices. Many wireless bonding methods, such as, have been developed, and many studies on solder bumps having a low melting point temperature have been made. In other words, in order to improve the height of the solder bumps, to narrow the distance between the solder bumps in order to minimize the high-density mounting and chip size, and to maintain a certain distance between the surface of the chip and the surface of the chip when mounting the chip on the substrate Many technologies have been developed to minimize stress of the chip.

Looking at these technologies, US Patent No. 3,625,837 first deposits chromium (Cr), a diffusion barrier metal, and copper (Cu), a wettable metal, to form solder bumps on pads of semiconductor devices. After forming a photoresist pattern for selective electroplating on the metals, the solder bumps by electroplating and reflowing lead (95% -100%), tin (0% -5%) solder It discloses a technique for forming a.

In the technique disclosed in US Pat. No. 3,625,837, the distance between solder bumps is because the solder is electroplated sideways by subtracting the thickness of the photoresist pattern used for the selective electroplating from the height of the electroplating solder during electroplating. It is limited by the height of the solder to be electroplated.

That is, as shown in FIG. 1, since the solder is electroplated sideways by a length S similar to the level of the solder height T which is electroplated during selective electroplating, in order to obtain a predetermined bump height, As shown in FIG. 2, the distance L between bumps should be designed such that at least two times the bump height H is maintained.

Therefore, the electroplating of solder with this technique limits the high density mounting and chip size minimization. In addition, when the chip having the bumps as described above is mounted on the substrate, as shown in FIG. 3, since the gap W between the substrate and the surface of the chip cannot be maintained at an appropriate level, solder from the chip due to thermal stress The bumps may fall off and be damaged.

Next, the solder bump forming technique disclosed in US Pat. No. 4,661,375 is a technique related to the deposition method among the solder bump forming methods such as electroplating method, deposition method, and deposition method. After evaporation and selective etching, it is first deposited by soldering at 100% lead at 327 ℃ and then secondly deposited by solder (95%) and tin (5%) at 312 ℃. . Then, after depositing a third deposit of lead (90%) and tin (10%) at a temperature of 307 ° C, these deposited solders were reflowed at a temperature of 327 ° C to lead (95%) and tin (5%). It is possible to improve the solder bump height by 27% to 76% by using a technique of forming a solder bump of the conventional deposition technique.

However, the technique disclosed in US Pat. No. 4,661,375 has a difficulty in increasing the height of solder bumps compared to the electroplating method, and when a chip using bumps according to this technique is mounted on a substrate, the substrate and the chip as in the previous technique. It is difficult to keep the gap between them.

Another conventional technique is a mushroom-shaped solder bump forming technique that uses a copper bump 16 of about 30 μm to 40 μm as shown in FIG. Except for the copper bumps 16, it is similar to the technique of US Pat. No. 3,625,837.

Referring to FIG. 4, an oxide film 11 formed on the surface of the semiconductor device 10 is selectively etched to provide an aluminum electrode 12, and an insulating film formed by a chemical vapor deposition (CVD) method. 13), and openings are selectively formed by conventional photolithography techniques to form pads.

Next, a thin film of chromium 14, which is a diffusion barrier metal, and copper 15, which is a hygroscopic metal, is deposited on the entire surface of the opening and the insulating layer 13, and then an insulating film for selectively electroplating the copper bumps 16 and the solder bumps is formed. A resist (not shown) is used to apply a thickness of about 5 μm and then an opening is formed in the portion to be electroplated using conventional photolithography techniques.

Next, the copper bumps 16 are electroplated at a height of about 30 µm to 40 µm using the barrier metals 14 and 15 as electrodes. At this time, the copper of about 25 micrometers-about 35 micrometers which removed the thickness of the photoresist is also electroplated sideways.

Next, after electroplating solder having a predetermined mixing ratio using the barrier metals 14 and 15 as electrodes, the photoresist is removed and the barrier metal is etched using the formed bumps as a mask pattern, and then soldered by surface tension. And the non-hygroscopic property of the insulating film formed by the CVD method and the hygroscopic property of the solder and copper, reflowing to the melting point temperature of the solder to form solder bumps of about 140 μm and mushroom bumps as shown in FIG. Is formed. At this time, the height of the solder is determined by the amount of solder to be electroplated.

In the technique shown in FIG. 4, the copper electroplating is also electroplated laterally by subtracting the thickness of the photoresist used for the selective electroplating from the height of the selectively electroplated copper. Since the solder is electroplated, the solder is electroplated sideways by a length S similar to the height T of the electroplated solder as shown in FIG. As such, the distance between bumps (L) is to be designed so that the total bump height (H) is more than twice. In addition, this technique requires a photoresist layer having a thickness of about 5 μm and needs to be coated with a high viscosity photoresist, so that a separate facility is required because existing production equipment cannot be used, and bumps are formed using such a technique. In order to narrow the distance between the bumps, the thickness of the photoresist used for the selective electroplating should be very high. As such, there is a practical difficulty due to the problem of the photoresist capable of increasing the thickness and the equipment that can be applied thereto.

To solve this problem, IBM's C-4 technology uses a metal mask to selectively deposit solder by a deposition method, and then reflows the solder to form bumps. In this technology, however, it takes a lot of time to increase the height of the bumps, and there are a number of problems such as low productivity, so electroplating is the preferred technology.

Accordingly, an object of the present invention is to provide a semiconductor device capable of high-density mounting by improving the structure of solder bumps in order to solve the problems of the prior art as described above.

Another object of the present invention is to provide a semiconductor device capable of minimizing the stress of the chip due to heat by maintaining a constant gap between the substrate and the surface of the chip when mounting the chip on the substrate.

Another object of the present invention is to provide a method for manufacturing a semiconductor device which can efficiently manufacture the solder bumps of the above-described structure.

In order to achieve the above objects and other objects, the present invention is characterized in that the solder bumps have a hemispherical structure in which layers having different solder ratios are stacked.

In order to achieve the above another object, the method of the present invention is a method of manufacturing a semiconductor device having a solder bump forming step, the solder bump forming step, the first step of forming a solder and the melting point temperature of the solder In the second step of reflowing the solder is made repeatedly, the solder has a different composition ratio.

EMBODIMENT OF THE INVENTION Hereinafter, the preferred embodiment of the semiconductor device and its manufacturing method which concern on this invention is demonstrated with reference to attached drawing.

5 is a cross-sectional view illustrating a structure of a solder bump according to the present invention, in which a first insulating layer 31 is formed on a surface of the semiconductor device 30 to expose a portion of the semiconductor device 30. The first metal layer 32 is formed on the surface of the semiconductor device 30 and a portion of the first insulating layer 31, and the first metal layer 32 and the first metal layer 32 are exposed. A second insulating layer 33 is formed on the first insulating layer 31, and a second metal layer 34 is formed to cover the exposed first metal layer 32. The first and second metal layers 34 are formed on the second metal layer 34. Second barrier metal layers 35 and 36 are sequentially formed, and first, second and third solder bumps 40, 41 and 43 are sequentially formed on the second barrier metal layer 36.

6A to 6H are process flowcharts showing a method of forming solder bumps according to the present invention.

FIG. 6A illustrates a process of forming a general pad formed on a semiconductor device. First, a first insulating layer 31, for example, an oxide film is formed on a surface of a semiconductor device 30, and then the first opening is formed through a conventional etching process. Next, a second insulating layer 33 used as a protective film of the first metal layer 32, for example, a PSG (Phospho-Silicate Glass) film or a nitride film is deposited, and then the first etching process is performed through a conventional etching process. The second insulating layer 33 is selectively etched to expose a portion of the metal layer 32 to form a second opening. Until this process, a pad is generally formed in a semiconductor device.

6B illustrates a process of forming the second metal layer 34, the first barrier metal layer 35, and the second barrier metal layer 36. First, aluminum oxide is naturally oxidized to the aluminum film, which is the first metal layer 32. After the film is removed by RF treatment, a second metal layer 34, for example, an aluminum film, for use as an electrode during electroplating is deposited on the entire surface to a predetermined thickness, for example, a thickness of about 1 m to 2 m. Subsequently, a barrier metal layer is formed on the second metal layer 34 for excellent adhesion between the aluminum film used as the second metal layer and the solder bumps to be formed in a subsequent process. First, the diffusion barrier is formed as the first barrier metal layer 35. A metal such as chromium, tungsten titanium (TiW), or nickel (Ni), which is a metal, is deposited to a predetermined thickness, for example, about 1000 to 2000 microns, and then the second barrier metal layer 36 is a metal such as copper, which is a hygroscopic metal. Is deposited to a predetermined thickness, for example, a thickness of about 1 μm. In this case, the barrier metal layers are deposited using a sputter or evaporation evaporation equipment, and the same barrier metal layer is not exposed to the atmosphere after the deposition of the first barrier metal layer 35. Successively, the second barrier metal layer 36 is deposited. By performing an etching process by applying a predetermined mask pattern on the second barrier metal layer 36, the patterned first and second barrier metal layers 35 and 36 may be obtained. Here, the diameters of the first and second barrier metal layers 35 and 36 determine the diameter of the solder.

FIG. 6C shows a process of forming the third insulating film 37 and the first photoresist layer 38. The third insulating film 37, for example, the PSG film by the CVD method, on the entire surface after the process of FIG. Or a nitride film is deposited to a predetermined thickness, for example, about 3 μm to 4 μm, and then, on the third insulating film 37, a low-viscosity photoresist for semiconductor manufacturing is formed to a predetermined thickness, eg, about 1.5 μm to 2.5 μm. The first photoresist layer 38 is formed by applying. In this case, since an insulating film having a predetermined thickness using a CVD method and a photoresist layer are used together as an insulating film for selective electroplating, the photoresist layer can be used as a low-viscosity photoresist so that existing production equipment can be used as it is. have.

FIG. 6D illustrates a process of forming the electroplated first solder 39. First, the third insulating layer 37 is etched through a conventional etching process to form the first and second barrier metal layers 35 and 36. This complete exposure exposes an opening for selective electroplating. In this case, the distance between the insulating films used for selective electroplating (the patterned third insulating layer and the first photoresist layer 37 and 38 and the barrier metal layers 35 and 36 is equal to the insulating layers 37 and 38). It does not matter even if it covers a part of the barrier metal layers 35 and 36, but it is good to maintain at an appropriate interval as shown. Subsequently, the oxide film naturally oxidized to the second barrier metal layer 36 is removed, and selectively electroplating a solder having 95% lead and 5% tin using the second metal layer 34 as an electrode is shown. As described above, an electroplated first solder 39 can be obtained.

FIG. 6E illustrates a process of forming the first solder bump 40. First, after removing the first photoresist layer after the process of FIG. 6D, the electroplated first solder and the third insulating layer are subjected to surface tension. The electroplated at a temperature of about 320 ° C., the melting point temperature of the electroplated first solder, using the non-hygroscopic properties of the (37) layer and the hygroscopic properties of the electroplated first solder and second barrier metal layers. By reflowing the first solder, a hemispherical first solder bump 40 having a height of about 30 μm is formed. Here, the first solder may be made of lead, tin, and silver having a predetermined mixing ratio in addition to the lead (95%) and tin (5%), and the solder having a melting point temperature of about 320 ° C.

FIG. 6F illustrates a process for forming the second solder bump 41 and the electroplating third solder 42. First, 90% lead and 10% tin are formed using the second metal layer 34 as an electrode. After the electroplating of the solder, the second solder bump 41 having a height of about 40 μm is reflowed by reflowing the electroplated second solder at a temperature of about 310 ° C., which is the melting point temperature of the electroplated second solder. When the second metal layer 34 is formed as an electrode and then electroplated with 60% lead and 40% tin, an electroplated third solder 42 can be obtained as shown. Here, in the configuration of the second solder and the third solder, in addition to the above-described lead and tin, a solder composed of lead, tin, and silver in a predetermined mixing ratio may be used.

FIG. 6g first removes the third insulating film after the process of FIG. 6f and exposes the second metal layer 34 used as an electrode during electroplating using the electroplated third solder 42 as a mask pattern. It shows the process of etching the part. In the etching process of the second metal layer, the amount of the third solder to be electroplated during the electroplating should be taken into consideration since the electroplated third solder is etched to about 3 μm to 6 μm, which is three times the thickness of the second metal layer.

FIG. 6h illustrates a process of forming the third solder bumps 43. By reflowing the electroplated third solder at a temperature of about 240 ° C. which is the melting point temperature of the electroplated third solder, By forming a third solder bump 43 having a height, it is possible to manufacture a hemispherical bump (composed of the first, second and third solder bumps) of which the total height of the solder bumps is about 140 μm. Here, the solder bumps may be formed by depositing step by step without electroplating the solder. In this case, a metal layer, for example, an aluminum film, which is used as an electrode during electroplating is not necessary. Since the height of the solder bumps for each step is determined by the amount of solder to be electroplated, an appropriate amount of solder should be electroplated. Then, 50% to 60% of the total solder bump height is formed in the last step, and the solder bumps formed in this last step are solder bumps having a melting point temperature of 150 ° C to 250 ° C regardless of the mixing ratio. shall.

As described above, according to the solder bump forming technique of the present invention, the distance between the solder bumps can be narrowed by about 50% compared to the conventional one, so that the high density mounting and the chip size can be made smaller than the conventional one, When the used chip is mounted, the reflow temperature is used at about 240 ° C, the melting point temperature of the final solder, so that the solder formed in the first and second stages does not melt, so that the gap between the substrate and the chip surface is always maintained at about 70 μm to 80 μm. Therefore, the stress of the chip due to heat can be minimized.

In addition, by using an insulating film such as a PSG film by a CVD method and a low-viscosity photoresist layer for selective electroplating, the existing equipment for coating can be used as it is.

Claims (19)

A first insulating film formed on the surface of the semiconductor device so that a part surface of the semiconductor device is exposed, a first metal layer formed on the surface of the exposed semiconductor device and a part of the first insulating film, and a part surface of the first metal layer is exposed A second insulating layer formed on the first metal layer and the first insulating layer, a second metal layer formed to cover the exposed first metal layer, first and second barrier metal layers sequentially formed on the second metal layer, and the second barrier metal layer. And first, second, and third solder bumps formed on top of each other. The semiconductor device of claim 1, wherein the second metal layer is used as an electrode during electroplating. The semiconductor device according to claim 1 or 2, wherein the first and second metal layers are aluminum films. The semiconductor device according to claim 3, wherein the second insulating film is a PSG film or a nitride film. The semiconductor device according to claim 4, wherein the first barrier metal layer is chromium, tungsten titanium, or nickel as a diffusion barrier metal. 6. The semiconductor device according to claim 5, wherein said second barrier metal layer is a hygroscopic metal and is copper. The method of claim 6, wherein the first solder bump of the first, second and third solder bump has a melting point temperature of 320 ℃, the second solder bump has a melting point temperature of 310 ℃, the third solder bump has a melting point temperature It is 240 degreeC. The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 7, wherein the height of the first solder bump is 30 m, the height of the second solder bump is 40 m, and the height of the third solder bump is 70 m. Forming a general pad in the semiconductor device; Forming a metal layer used as an electrode during electroplating on a pad of a semiconductor device; Forming and patterning first and second barrier metal layers sequentially on the metal layer; Sequentially forming an insulating film and a photoresist layer on the entire surface of the resultant product; Etching the insulating film and the photoresist layer to expose the first and second barrier metal layers; Removing the photoresist layer to form an electroplated first solder on the entire surface of the resultant using the metal layer as an electrode; Forming a first solder bump by reflowing at the melting point temperature of the electroplated first solder; Forming a second solder electroplated on the entire surface of the resultant using the metal layer as an electrode; Forming a second solder bump by reflowing at the melting point temperature of the electroplated second solder; Forming an electroplated third solder on the entire surface of the resultant using the metal layer as an electrode; After removing the insulating layer, etching the exposed portion of the metal layer used as an electrode during electroplating by using the electroplated third solder as a mask pattern; And forming a third solder bump by reflowing at the melting point temperature of the electroplated third solder. The method of manufacturing a semiconductor device according to claim 9, wherein the metal layer forms an aluminum film with a thickness of about 1 μm to 2 μm. The method of claim 10, wherein the first barrier metal layer is a diffusion barrier metal, and the metal is formed in a thickness of about 1000 to 2000 microns, such as chromium, tungsten titanium, or nickel. 12. The method of claim 11, wherein the second barrier metal layer is a hygroscopic metal, wherein a metal such as copper is formed to a thickness of about 1 µm. The method of claim 9, wherein the first and second barrier metal layers are continuously formed in the same equipment so as not to be exposed to the atmosphere by using a sputtering or evaporation equipment. The method of manufacturing a semiconductor device according to claim 12, wherein the insulating film forms a PSG film or a nitride film by a CVD method to a thickness of about 3 µm to 4 µm. 15. The method of manufacturing a semiconductor device according to claim 14, wherein the photoresist layer forms a low viscosity photoresist for semiconductor manufacturing to a thickness of about 1.5 탆 to 2.5 탆. 16. The method of claim 15, wherein the first electroplated solder is a mixture having a predetermined composition ratio having a melting point temperature of about 320 DEG C, and the second electroplated solder is a mixture having a predetermined composition ratio having a melting point temperature of about 310 DEG C. And the electroplated third solder is a mixture having a predetermined composition ratio with a melting point temperature of about 240 ° C. The method of claim 16, wherein the height of the first solder bump is 30 μm and the height of the second solder bump is 40 μm, and the height of the third solder bump is 70 μm. The semiconductor device according to claim 1, wherein the solder composition ratios of the first, second and third solder bumps are different from each other. The method of claim 1, wherein the first solder bumps of the first, second and third solder bumps are a mixture of 95% lead and 5% tin, and the second solder bumps are 90% lead and tin. And the third solder bump is a mixture of 60% lead and 40% tin in the semiconductor device.