Nothing Special   »   [go: up one dir, main page]

KR960018958A - Main Memory Access Device Using Data Buffer When Performing Atomic Instruction in Multiprocessor System - Google Patents

Main Memory Access Device Using Data Buffer When Performing Atomic Instruction in Multiprocessor System Download PDF

Info

Publication number
KR960018958A
KR960018958A KR1019940030614A KR19940030614A KR960018958A KR 960018958 A KR960018958 A KR 960018958A KR 1019940030614 A KR1019940030614 A KR 1019940030614A KR 19940030614 A KR19940030614 A KR 19940030614A KR 960018958 A KR960018958 A KR 960018958A
Authority
KR
South Korea
Prior art keywords
data
bus
main memory
register
control
Prior art date
Application number
KR1019940030614A
Other languages
Korean (ko)
Other versions
KR0135927B1 (en
Inventor
원철호
김성운
윤석한
Original Assignee
양승택
재단법인 한국전자통신연구소
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 양승택, 재단법인 한국전자통신연구소 filed Critical 양승택
Priority to KR1019940030614A priority Critical patent/KR0135927B1/en
Publication of KR960018958A publication Critical patent/KR960018958A/en
Application granted granted Critical
Publication of KR0135927B1 publication Critical patent/KR0135927B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)

Abstract

본 발명은 다수개의 프로세서(CPU)가 버스를 통하여 메인 메모리에 연결된 다중 프로세서 시스템에 관한 것으로 특히, 각각의 프로세서 보드마다 독특한 기능을 수행하기 위한 중앙처리장치와, 어드레스 버스와 데이타 버스 및 제어 버스로 상기 중앙처리장치와 연결되어 상기 시스템 버스를 통하여 메인메모리 액세스동작을 수행하는 버스정합부와, 상기 제어버스와 어드레스 버스에 연결되고 입력되는 어드레스와 제어 정보를 해독하여 메모리 액세스 사이클을 제어하는 소정갯수의 제어신호를 발생시키는 메모리 제어부와, 상기 데이타 버스를 통하여 상기 중앙처리장치와 연결되어 상기 메모리 제어부의 제어신호에 따라 데이타를 저장 또는 출력하는 레지스터 및 상기 레지스터에 저장되어 있는 데이타와 상기 데이타 버스를 통하여 입력되는 데이타를 비교하여 상기 메모리 제어부에 입력하는 비교기를 포함하는 것을 특징으로 하는 다중프로세서 시스템에서 아토믹 명령어 수행시 데이타 버퍼를 사용한 메인 메모리 액세스 장치를 제공하여 불필요한 동작의 수행을 방지할 수 있는 효과가 있다.The present invention relates to a multiprocessor system in which a plurality of processors (CPUs) are connected to main memory through a bus. In particular, the present invention relates to a central processing unit, an address bus, a data bus, and a control bus for performing unique functions for each processor board. A bus matching unit connected to the central processing unit to perform a main memory access operation through the system bus, and a predetermined number of memory access cycles connected to the control bus and the address bus to read and input address and control information. A memory controller for generating a control signal of the memory; and a register connected to the central processing unit through the data bus to store or output data according to a control signal of the memory controller; and a data stored in the register and the data bus. Day entered through In the multiprocessor system, a main memory access device using a data buffer is used to execute an atomic instruction in a multiprocessor system.

Description

다중 프로세서 시스템에서 아토믹 명령어 수행시 데이타 버퍼를 사용한 메인 메모리 액세스 장치Main Memory Access Device Using Data Buffer When Performing Atomic Instruction in Multiprocessor System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따라 아토믹 명령어 수행시 데이타 버퍼를 사용하여 메인 메모리를 액세스할 수 있도록 구성되어 있는 다중 프로세서 시스템의 구성 예시도,1 is an exemplary configuration diagram of a multiprocessor system configured to access a main memory using a data buffer when performing an atomic instruction according to the present invention.

제2도는 제1도에서 도시되어 있는 다중 프로세서 시스템에서의 아토믹 명령어 수행 과정 순서도.2 is a flow chart of the atomic instruction execution process in the multiprocessor system shown in FIG.

Claims (3)

시스템 버스에 연결되어 있는 메인메모리와의 데이타 통신을 위하여 다수개의 프로세서 보드가 상기 시스템 버스에 연결되어 상기 메인 메모리를 액세스할 수 있도록 구성되어 있는 다중 프로세서 시스템에 있어서, 각각의 프로세서 보드마다 독특한 기능을 수행하기 위한 중앙처리장치와; 어드레스 버스와 데이타 버스 및 제어 버스로 상기 중앙처리장치와 연결되어 상기 시스템 버스를 통하여 메인메모리 액세스동작을 수행하는 버스 정합부와; 상기 제어버스와 어드레스 버스에 연결되고 입력되는 어드레스와 제어 정보를 해독하여 메모리 액세스 사이클을 제어하는 소정갯수의 제어신호를 발생시키는 메모리 제어부와; 상기 데이타 버스를 통하여 상기 중앙처리장치와 연결되어 상기 메모리 제어부의 제어신호에 따라 데이타를 저장 또는 출력하는 레지스터; 및 상기 레지스터에 저장되어 있는 데이타와 상기 데이타 버스를 통하여 입력되는 데이타를 비교하여 상기 메모리 제어부에 입력하는 비교기를 포함하는 것을 특징으로 하는 다중프로세서 시스템에서 아로믹 명령어 수행시 데이타 버퍼를 사용한 메인 메모리 액세스 장치.In a multiprocessor system in which a plurality of processor boards are connected to the system bus to access the main memory for data communication with main memory connected to a system bus, each processor board has a unique function. A central processing unit for performing; A bus matching unit connected to the central processing unit through an address bus, a data bus, and a control bus to perform a main memory access operation through the system bus; A memory control unit connected to the control bus and the address bus and generating a predetermined number of control signals for decrypting an input address and control information to control a memory access cycle; A register connected to the central processing unit through the data bus to store or output data according to a control signal of the memory controller; And a comparator for comparing the data stored in the register with the data input through the data bus and inputting the data to the memory controller. Device. 제1항에 있어서, 상기 메모리 제어부는 아토믹 데이타의 읽기 사이클에서 상기 레지스터에 입력제어신호를 전달하여 상기 데이타 버스의 값이 상기 레지스터에 입력 저장되도록 하고, 아토믹 데이타의 쓰기 사이클에서 출력제어신호를 전달하여 상기 레지스터(41)에 저장되어 있는 내용이 출력되도록 하는 것을 특징으로 하는 다중프로세서 시스템에서 아토믹 명령어 수행시 데이타 버퍼를 사용한 메인 메모리 액세스 장치.The method of claim 1, wherein the memory controller transfers an input control signal to the register in a read cycle of atomic data so that a value of the data bus is input to and stored in the register, and transmits an output control signal in a write cycle of atomic data. Main memory access device using a data buffer when performing an atomic instruction in a multiprocessor system, characterized in that to output the contents stored in the register (41). 제1항 또는 제2항에 있어서, 상기 메모리 제어부는 상기 비교기의 출력신호를 검사하여 아토믹 데이타의 쓰기 사이클에 상기 중앙처리장치로부터 출력되는 데이타와 아토믹 데이타의 읽기 사이클에 상기 레지스터에 저장되었던 데이타가 동일한 경우 상기 중앙처리장치로부터 요구되어진 쓰기 동작을 중단하도록 하는 것을 특징으로 하는 다중프로세서 시스템에서 아토믹 명령어 수행시 데이타 버퍼를 사용한 메인 메모리 액세스 장치.The memory controller of claim 1, wherein the memory controller examines an output signal of the comparator and stores data output from the CPU in a write cycle of atomic data and data stored in the register in a read cycle of atomic data. In the same case, the main memory access device using a data buffer when performing an atomic instruction in a multiprocessor system, characterized in that for stopping the write operation requested from the central processing unit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940030614A 1994-11-21 1994-11-21 Main Memory Access Device Using Data Buffer When Performing Atomic Instruction in Multiprocessor System KR0135927B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940030614A KR0135927B1 (en) 1994-11-21 1994-11-21 Main Memory Access Device Using Data Buffer When Performing Atomic Instruction in Multiprocessor System

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940030614A KR0135927B1 (en) 1994-11-21 1994-11-21 Main Memory Access Device Using Data Buffer When Performing Atomic Instruction in Multiprocessor System

Publications (2)

Publication Number Publication Date
KR960018958A true KR960018958A (en) 1996-06-17
KR0135927B1 KR0135927B1 (en) 1998-06-15

Family

ID=19398499

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940030614A KR0135927B1 (en) 1994-11-21 1994-11-21 Main Memory Access Device Using Data Buffer When Performing Atomic Instruction in Multiprocessor System

Country Status (1)

Country Link
KR (1) KR0135927B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100312337B1 (en) * 1997-10-04 2001-12-28 구자홍 Address control method and apparatus of multiprocessor system

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7114042B2 (en) 2003-05-22 2006-09-26 International Business Machines Corporation Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment
KR100934227B1 (en) 2007-09-21 2009-12-29 한국전자통신연구원 Memory switching control device using open serial matching, its operation method and data storage device applied thereto

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100312337B1 (en) * 1997-10-04 2001-12-28 구자홍 Address control method and apparatus of multiprocessor system

Also Published As

Publication number Publication date
KR0135927B1 (en) 1998-06-15

Similar Documents

Publication Publication Date Title
US4325116A (en) Parallel storage access by multiprocessors
KR930018378A (en) Method and device for performance optimization of cache memory system
KR970012203A (en) Data processing system for executing trace functions and their methods
KR940012147A (en) Microcomputer system
KR830009518A (en) Data Processing System for Parallel Processing
KR960011613A (en) Data processing device
KR940012146A (en) Semiconductor integrated circuit with CPU and multiplier
KR910012962A (en) DMA controller
KR930022198A (en) Data processing unit
KR920001323A (en) How processors work to improve computer performance by removing branches
KR860003552A (en) Micro programmable system
KR930008604A (en) Microprocessors and Control Methods
KR930002935A (en) Information processing device
KR930700907A (en) Apparatus and method for providing a stall cache
KR970012153A (en) How to run data processor and breakpoint operations
KR910001565A (en) Multiprocessor system
KR880011676A (en) Block access method using cache memory
KR830010423A (en) Data exchange method of data processing system
KR960018958A (en) Main Memory Access Device Using Data Buffer When Performing Atomic Instruction in Multiprocessor System
KR950015104A (en) How to support indivisible cycle using bus monitor
JP2619425B2 (en) Sequence controller
KR970076252A (en) Microcomputer
KR930010775A (en) Image processing device
KR950020134A (en) Cache Memory Control in Multiprocessor Systems
KR880004383A (en) Microprocessor system

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19941121

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19941121

Comment text: Request for Examination of Application

PG1501 Laying open of application
E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19971231

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19980119

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19980119

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20001212

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20011228

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20021227

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20031231

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20041231

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20051216

Start annual number: 9

End annual number: 9

PR1001 Payment of annual fee

Payment date: 20070103

Start annual number: 10

End annual number: 10

FPAY Annual fee payment

Payment date: 20080103

Year of fee payment: 11

PR1001 Payment of annual fee

Payment date: 20080103

Start annual number: 11

End annual number: 11

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

Termination category: Default of registration fee

Termination date: 20091210