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KR960015914A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR960015914A
KR960015914A KR1019940025539A KR19940025539A KR960015914A KR 960015914 A KR960015914 A KR 960015914A KR 1019940025539 A KR1019940025539 A KR 1019940025539A KR 19940025539 A KR19940025539 A KR 19940025539A KR 960015914 A KR960015914 A KR 960015914A
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KR
South Korea
Prior art keywords
signal
self
refresh
output signal
oscillator
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Application number
KR1019940025539A
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Korean (ko)
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KR0140641B1 (en
Inventor
심재광
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019940025539A priority Critical patent/KR0140641B1/en
Publication of KR960015914A publication Critical patent/KR960015914A/en
Application granted granted Critical
Publication of KR0140641B1 publication Critical patent/KR0140641B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

본 발명은 반도체 기억소자에 관한 것으로, 특히 DRAM(Dynalnic Randoln Access Memory)의 리프레쉬에 관한 논리를 포함하는 셀프 리플레쉬 제어부를 칩 내부에 설계하여 셀프 리프레쉬(Self Refersh)가 부가장치없이 되도록, 한 반도체 기억소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. In particular, a self-refresh control unit including logic for refreshing a DRAM (Dynalnic Randoln Access Memory) is designed inside a chip so that a self-refresh (Self Refersh) is possible without an additional device. It relates to a memory device.

이와 같은 본 발명은 셀프 리플레쉬 모드를 사용하고자 하는 시스템에서 셀프 리프레쉬 전입전후에 필요한 전셀에 대한 리프레쉬와 셀프 리프레쉬에 대한 제어를 칩내부에 설계된 셀프 리프레쉬 제어부에 의해 이루어지게 하여 DRAM을 이용하여 구현하는 시스템의 구성을 효율적으로 할 수 있게 하는 효과가 있다.As described above, the present invention implements control using the self-refresh control unit designed inside the chip to control the refresh and self-refresh of all cells required before and after the self-refreshing in the system to use the self-refresh mode. There is an effect that can make the configuration of the system efficiently.

Description

반도체 기억소자Semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 (a)는 본 발명의 반도체 기억소자의 셀프 리플레쉬 제어부의 구성블럭도,3A is a block diagram of a self refresh control unit of the semiconductor memory device of the present invention;

(b)는 제3도(a)의 셀프 리러프레쉬 제어부의 각 구성블럭의 신호파형도,(b) is a signal waveform diagram of each component block of the self-refresh refresh controller of FIG.

(c)는 제3도(a)의 셀프 리프레쉬 제어부의 각 구성블럭의 신호파형도.(c) is a signal waveform diagram of each component block of the self-refresh control unit of FIG.

Claims (1)

외부의 행 어드레스 스토로브(RAS*)신호와, 열 어드레스 스트로브(CAS*)신호를 받아들여 CAS*가 RAS*보다 먼저 인에이블 되었음을 검출하는 CBR검출기와, 상기 CBR 검출기의 출력신호에 의해 시스템의 동작타이밍을 동기화하기 위한 클럭을 발생하는 클럭발생기와, 상기 클럭발생기의 출력신호를 받아 셀프 리플레쉬 진입시간을 계산출력하는 타이머와, 상기 타이머의 출력신호에 의해 셀프 리플레쉬진입전에 전셀 리플레쉬를 행하기 위한 클럭을 발생하는 재1오실레이터와, 상기 제1오실레이터의 출력신호를 카운트하여 행 어드레스 필드의 시간이 지난 후에 제1오실레이터의 동작을 정지시키는 제1카운터와, 상기 제1카운더의 출력신호에 의해 인에이블 되어 클럭발생기의 출력신호에 동기화된 내부 RAS신호를 출력하는 내부 RAS신호발생기와, 외부 RAS*신호와 타이머의 출력신호를 입력으로 하여 셀프 리프레쉬의 종료시점을 검출하는 셀프 리플레쉬종료검출기와, 상기 셀프 리플레쉬 종료검출기의 셀프 리프레쉬 종료신호가 입력되면 셀프 리플레쉬 종료후의 전셀 리플레쉬를 위한 클럭을 발생하는 제2오실레이터와, 상기 제2오실레이터의 출력신호를 카운트하여 행 어드레스 필드의 시간이 지난 후에 제2오실레이터의 동작을 정지시키는 제2카운터와, 제1오실레이터의 출력신호와 내부 RAS 신호발생기의 출력신호와, 제2오실레이터의 출력신호를 논리연산하여 출력하는 제2OR 게이트와, 상기 셀프 리플레쉬 종료검출기의 출력신호와 타이머의 출력신호를 논리연산하여 출력하는 제1OR 게이트와, 상기 재1OR 게이트와 제2OR 게이트의 출력신호와 외부의 RAS*신호간 멀티문렉싱하여 출력하는 멀티플렉시와, 상기 CBR 검출기와 제2OR 게이트의 출력신호를 논리연산하여 내부 어드레스 카운터 제어신호간 출력하는 제3OR 게이트로 이루어진 셀프 리프레쉬 제어부를 포함하여 구성되는 반도체 기억소자.A CBR detector which receives an external row address stove (RAS *) signal and a column address strobe (CAS *) signal and detects that CAS * is enabled before RAS *, and an output signal of the CBR detector A clock generator for generating a clock for synchronizing operation timing, a timer for outputting the self-refresh entry time based on the output signal of the clock generator, and an output signal of the timer to perform all-cell refresh before self-refresh entry. A first oscillator for generating a clock for performing the operation, a first counter for counting an output signal of the first oscillator to stop the operation of the first oscillator after a time of the row address field passes, and an output of the first counter Internal RAS signal generator which is enabled by signal and outputs internal RAS signal synchronized with output signal of clock generator, and external RAS * signal A self refresh end detector for detecting the end of self refresh by inputting the output signal of the timer, and a clock for all cell refresh after the self refresh ends when the self refresh end signal of the self refresh end detector is input. A second oscillator, a second counter for counting the output signal of the second oscillator to stop the operation of the second oscillator after a time of the row address field passes, an output signal of the first oscillator, and an output of the internal RAS signal generator. A second OR gate for performing a logic operation on the signal, an output signal of the second oscillator, a first OR gate for performing a logic operation on the output signal of the self-refresh end detector, and an output signal of the timer, and the re-OR gate; A multiplex for outputting a multi-multiplexed output signal between a second OR gate and an external RAS * signal, and the CBR And a self-refresh control unit comprising a third OR gate for logically operating the detector and the output signal of the second OR gate to output the internal address counter control signal. ※ 참고사항 : 최초출된 내용에 의하여 공개하는 것임.※ Note: It is to be disclosed based on the original contents.
KR1019940025539A 1994-10-06 1994-10-06 Semiconductor memory device KR0140641B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940025539A KR0140641B1 (en) 1994-10-06 1994-10-06 Semiconductor memory device

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Application Number Priority Date Filing Date Title
KR1019940025539A KR0140641B1 (en) 1994-10-06 1994-10-06 Semiconductor memory device

Publications (2)

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KR960015914A true KR960015914A (en) 1996-05-22
KR0140641B1 KR0140641B1 (en) 1998-06-01

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474549B1 (en) * 1997-06-30 2005-06-27 주식회사 하이닉스반도체 Casby Force Refresh Device for Semiconductor Memory Devices
US8488404B2 (en) 2009-06-26 2013-07-16 Hynix Semiconductor Inc. Counter control signal generator and refresh circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474549B1 (en) * 1997-06-30 2005-06-27 주식회사 하이닉스반도체 Casby Force Refresh Device for Semiconductor Memory Devices
US8488404B2 (en) 2009-06-26 2013-07-16 Hynix Semiconductor Inc. Counter control signal generator and refresh circuit

Also Published As

Publication number Publication date
KR0140641B1 (en) 1998-06-01

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