KR960000899B1 - High voltage selection circuit and the data output buffer with it - Google Patents

Abstract

The device comprises a PMOS transistor MP2 which has a drain and bulk connected with on output node, a gate connected with the second voltage, and a source connected with the first voltage and a PMOS transistor MP3 which has a drain connected with the second voltage, a source and bulk connected with an output node, and a gate connected with the first voltage.

Description

High voltage selection circuit and data output buffer including the same

1 is a circuit diagram showing a conventional data output buffer.

2 is a high voltage selection circuit diagram of the present invention.

3 is a circuit diagram showing a first embodiment of a data output buffer according to the present invention.

4 is a first simulation diagram of the data output buffer shown in FIG.

FIG. 5 is a second simulation diagram comparing and analyzing leakage currents generated when the data output buffers shown in FIG. 2 and FIG. 2 operate.

6 is a circuit diagram showing a second embodiment of a data output buffer according to the present invention.

* Explanation of symbols for main parts of the drawings

11,21: high voltage selection circuit section 22: high voltage transmission circuit section

23: bootstrap element

The present invention relates to a high voltage selection circuit of a semiconductor memory device and a data output buffer including the same. In particular, a high voltage selection circuit for comparing a voltage level of two nodes with each other and delivering a higher voltage level to an output terminal, In combination, the present invention relates to a data output buffer which reduces the leakage current flowing from the output stage to the power potential when the potential level of the data output stage is higher than the power potential.

In general, as the manufacturing technology of semiconductor devices improves, as the degree of integration of semiconductor devices increases and the size of devices decreases, attempts to lower power supply voltages in order to improve device reliability and reduce power consumption have been made. In this case, the data output buffer having the NMOS type driver stage in the conventional CMOS circuit has a problem that the pull-up characteristic is weak in reliability at high voltage. Attention is again paid to CMOS data output buffers using transistors. However, in the case of configuring the data output buffer using the CMOS output driver stage, the problem of leakage current occurs when latch-up occurs or when the voltage level of the data output stage Dout is higher than the power supply voltage. Will be generated.

In the present invention, rather than the problem of latch-up, the data output buffer for blocking the leakage current generated when the voltage level of the data output terminal Dout is higher than the power supply voltage.

FIG. 1 is a circuit diagram illustrating a conventional data output buffer, and illustrates a case in which a power supply voltage is applied with a bias of an N-well. The data output buffer is connected between a power supply voltage and an output node Dout, and a PMOS transistor MP1 having a gate connected to the node N1, an NMOS transistor MN1 connected between the output node Dout and a ground voltage and whose gate is connected to the node N2; It consists of a junction diode D2 connected between the node N3 to which the power supply voltage and the N-well of the PMOS transistor MP1 are connected, and a resistor R1 connected between the power supply voltage and the node N3.

In operation, data output to the data output terminal Dout is determined according to the voltage levels of the nodes N1 and N2. When both nodes N1 and N2 are logic high, the pull-down transistor MN1 is turned on to output low data. When both nodes N1 and N2 are logic logic low, the pull-up transistor MP1 is turned on to output high data.

If a voltage higher than the power supply voltage is applied to the data output terminal Dout, a current leakage path to the power supply voltage is formed, one of which is a leakage current falling into the power supply voltage through a well bias, and one of the pull-up transistors As it is turned on, it is a leakage current flowing through the pull-up transistor.

First, the leakage current flowing through the N- well is a pull-up transistor MP1 the PN junction between the data output terminal Dout and the associated P ⁺ region and the N- wells are turned in the forward direction - is turned on the output terminal Dout → the diode D2 → resistor R1 → Selected Since a current flows to the power supply voltage Vcc, a leakage current is generated from the data output terminal Dout to the power supply voltage. When the leakage current flows through the pull-up transistor MP1, the voltage level of the data output terminal Dout is higher than the power supply voltage. When the pull-up transistor is turned on when the voltage rises above the threshold voltage of the up transistor, a leakage current from the output terminal Dout to the power voltage is generated.

Therefore, an object of the present invention is to compare the voltage level of the two nodes with each other, a high voltage selection circuit that delivers a higher voltage level to the output stage, and the power supply at the output stage when the potential level of the data output stage is higher than the power potential using this high voltage selection circuit It is to provide a data output buffer with reduced leakage current flowing to the potential.

In order to achieve the above object, the high voltage selection circuit of the present invention has a PMOS transistor MP2 having a drain and a bulk connected to an output node, a gate connected to a second voltage, a source connected to a first voltage, and a drain connected to a second voltage. A PMOS transistor MP3 connected to the output voltage, the gate connected to the first voltage, the source and the bulk connected to the output node.

In order to achieve the above object, the data output buffer of the present invention is a pull-up transistor for transmitting a power supply voltage to the output terminal, a pull-down transistor for transmitting a ground voltage to the output terminal, the voltage of the power supply voltage and the output terminal High voltage selection means for comparing the levels and outputting a high voltage level to the bulk bias of the pull-up transistor to prevent latch-up is provided.

In order to achieve the above object, another data output buffer of the present invention includes a pull-up transistor for transmitting a power supply voltage to an output terminal, a pull-down transistor for transmitting a ground voltage to an output terminal, and a gate of the pull-up transistor. A boost strap means for boosting the voltage of the input data to be supplied to the bulk data of the pull-up transistor by supplying a voltage having a high voltage level by comparing a power supply voltage and a high voltage to the bulk and the boost strap means of the pull-up transistor; And a high voltage selecting means for preventing the latch-up of the boosting means and the latch-up of the boosting means.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 shows the high voltage selection circuit of the present invention, where the drain and bulk are connected to the output terminal out, the gate is connected to the second voltage, the source is connected to the first voltage, and the drain is the second voltage. PMOS transistor MP3 connected to the first voltage, the source and bulk connected to the output terminal out, and the operation is performed when the first voltage is higher than the second voltage. Transistor MP2 is turned on and the first voltage is transmitted to the output terminal out. When the voltage level of the second voltage is higher than the first voltage, the transistor MP3 is turned on and the voltage level of the second voltage is transmitted to the output terminal out. do.

3 is a circuit diagram showing a first embodiment of a data output buffer according to the present invention, and is constructed by combining the high voltage selection circuit shown in FIG. 2 with the data output buffer of FIG.

Its configuration is that the drain and bulk are connected to the node N3, the gate is connected to the output node Dout, the source is connected to the power supply voltage, the PMOS transistor MP2, the drain is connected to the output node Dout and the gate is connected to the power supply voltage. The PMOS transistor MP3, whose source and bulk are connected to the node N3, is a circuit further configured in the data output buffer of FIG.

Referring to the operation of the high voltage selection circuit (hereinafter, referred to as a high voltage selection circuit section) 11, when the power supply voltage is higher than the voltage of the output node Dout, the PMOS transistor MP2 is turned on to supply the power supply voltage. When the voltage level of the output node N3 is higher than that of the power supply voltage, the PMOS transistor MP3 is turned on so that the voltage level of the output node N3 is transmitted to the node N3.

4 is a simulation diagram of the data output buffer shown in FIG. 3, wherein the voltage level of the node N3 applied to the N-well initially follows the power supply voltage, and then the voltage level of the output terminal Dout becomes higher than the power supply voltage. It can be seen that it follows the voltage level.

FIG. 5 is a second simulation diagram comparing and analyzing leakage current generated when the data output buffers shown in FIG. 3 and FIG. 3 are operated. The voltage level of the data output terminal Dout is changed while the power supply voltage is fixed at 5V. While comparing the amount of leakage current.

In FIG. 5, (A) shows the current flowing through the N-well of the conventional data output buffer shown in FIG. 1, and (B) shows the pull-up transistor MP1 of the data output buffer shown in FIG. (C) shows the current flowing through the pull-up transistor MP1 of the data output buffer shown in FIG. 2, where the data output buffer according to the first embodiment of the present invention is used. It can be seen that the current flowing through the N-well is only the amount flowing through the junction diode in the reverse bias state, and this amount is very small.

FIG. 6 is a circuit diagram showing a second embodiment of the data output buffer according to the present invention, and further includes a high voltage selection circuit section 21, a high voltage transmission circuit section 22, and a bootstrap element 23 in FIG. .

The high voltage selection circuit portion 21 is connected between a power supply voltage and a node N3, a gate is connected to a high voltage, an N-type bulk is connected between a high voltage and a node N3, and a gate is connected between a high voltage and a node N3. N-type bulk and PMOS transistor MP5 connected to node N3. The high voltage selection circuit section 21 has the same operation and configuration as the high voltage selection circuit section 11 in FIG. 2 except that the power supply voltage and the potential level of the high voltage are compared to output a voltage having a higher potential level to the node N3. do.

The high voltage transfer circuit section 22 is connected between a high voltage and a node N5 and a PMOS transistor MP6 having a gate connected to the node N1 and an N-type bulk connected to a high voltage is connected between the node N5 and the ground voltage and a gate is input. An NMOS transistor MN2 connected to a node N4, a PMOS transistor MP7 connected between a high voltage and a node N1, a gate connected to the node N5, and an N-type bulk connected to a high voltage, and connected between the node N1 and a ground voltage and a gate The NMOS transistor MN3 to which the signal of the input node N1 is inverted by the inverter G1 is applied.

When the potential level of the input node N4 is high, the NMOS transistor MN2 and the PMOS transistor MP7 are turned on, and a high voltage is transmitted to the output node N1. On the other hand, when the potential level of the output node N1 is low, the NMOS transistor MN3 becomes low. Turned on to bring the potential of output node N1 low.

The bootstrap element 23 is for maintaining the potential level of the output node N1 of the high voltage transfer circuit unit 22 at a power supply voltage. The bootstrap element 23 is connected between the power supply voltage and the node N1 and has a gate connected to a high voltage. The bulk consists of a PMOS transistor MP8 connected to the node N3.

When the high voltage selection circuit unit 21, the high voltage transfer circuit unit 22, and the bootstrap element 23 are configured in combination with the data output buffer, the gate of the pull-up transistor MP1 is controlled through the high voltage transfer circuit unit 22. A high voltage having a voltage level higher than that of the power supply voltage is applied to the node N1, and a voltage having a higher voltage level is obtained by comparing the high voltage and the power supply voltage through the high voltage selector circuit 21 to N- of the pull-up transistor MP1 and the switch element MP8. Due to the well, the node N1 is raised to the power supply voltage level only when the high voltage is lower than the power supply voltage at the initial power supply to the semiconductor device.

The data output buffer of FIG. 6 does not appear as a leakage current of (C) shown in FIG. 5 because the voltage level rises to a high voltage at which the gate voltage is higher than the power supply voltage when the pull-up transistor MP1 is turned off. do.

In addition, a high voltage selection circuit unit 21 for comparing the power voltage included in the data output buffer of FIG. 6 with the voltage level of the high voltage is included in the high voltage generation circuit (not shown), the gate is controlled by the high voltage, and the power supply voltage is sourced. The drain of the PMOS transistor MP8, which is applied and uses the output of the high voltage selection circuit section 21 as a bulk bias, is connected to the high voltage output terminal of the high voltage generation circuit, so that the voltage level of the high voltage output terminal is initially supplied to the power supply voltage. You can pull up to the level quickly.

As described above, when the high voltage selection circuit of the present invention and the data output buffer including the same are implemented in the semiconductor memory device, when the voltage level of the data output terminal Dout is higher than the power supply voltage, the data output terminal Dout is converted into the power supply voltage. There is an effect that can reduce the power consumption by preventing the leakage current of. In addition, when the high voltage output terminal of the high voltage generation circuit is precharged using the high voltage selection circuit of the present invention, an effect of increasing the voltage level of the high voltage in a short time can be obtained.

Claims (6)

In a high voltage selection circuit that compares the voltage levels of two nodes and outputs a voltage having a high voltage level, a drain and a bulk are connected to an output node, a gate is connected to a second voltage, and a source is connected to the first voltage. And a PMOS transistor MP3 connected to an output node with a source connected to a first voltage, a gate connected to a first voltage, a source connected to a source, and a bulk connected to the output node. In a data output buffer of a semiconductor memory device, a pull-up transistor for transmitting a power supply voltage to an output terminal, a pull-down transistor for transmitting a ground voltage to an output terminal, and a voltage level of the power supply voltage and the output terminal are compared. And a high voltage selecting means for outputting a high voltage level to the bulk bias of the pull-up transistor to prevent latch-up. 3. The first PMOS transistor of claim 2, wherein the high voltage selecting means comprises: a first PMOS transistor having a drain and a bulk connected to an output node applied to an N-well of the pull-up transistor, a gate connected to a data output terminal, and a source connected to a power supply voltage. And a second PMOS transistor having a drain connected to a data output terminal, a gate connected to a power supply voltage, and a source and a bulk connected to an output node in common. 1. A semiconductor memory device comprising: a pull-up transistor for transferring a power supply voltage to an output terminal, a pull-down transistor for transferring a ground voltage to an output terminal, and a voltage of input data to be supplied to a gate of the pull-up transistor; And a boosting means for supplying a voltage having a high voltage level by comparing a power supply voltage and a high voltage to the bulk of the pull-up transistor and the boosting means to latch-up and boosting the pull-up transistor. And a high voltage selecting means for preventing latch-up of the data output buffer. 5. The apparatus of claim 4, wherein the high voltage selecting means comprises: a transmission line commonly connected to the bulk of the pull-up transistor and the boost strap means, a drain connected to the transmission line, a gate connected to the power supply voltage, and the And a second PMOS transistor having a source connected to a high voltage, a drain connected to the power supply voltage, a gate connected to the high voltage, and a source connected to the transmission line. 5. The first node of claim 4, wherein the high voltage is applied according to a voltage on a second node (N1) connected between the high voltage and the first node (N5) and connected to the boost device applied to its gate. The first node N5 according to the logic value of the PMOS transistor MP6 transmitted to the N5 and the input data on the input node N4 connected between the first node N5 and the ground voltage and applied to its gate. NMOS transistor MN2 for passing the voltage on the ground voltage to the ground voltage and the high voltage according to the voltage on the first node N5 connected between the high voltage and the second node N1 and applied to its gate. The PMOS transistor MP7 transmitting to the second node N1 and the input node N4 connected between the second node N1 and the ground voltage and applied to its gate via the inverter G1. Input data Comprising an NMOS transistor (MN3) is driven complementary to the NMOS transistor (MN2) in accordance with a logic value to bypass the voltage on the second node (N1) toward the ground voltage to the boost strap means and the input data And a high voltage transmission means for matching the data output buffer.