KR960000229B1 - Making method of vertical channel mosfet using trench structure - Google Patents
Making method of vertical channel mosfet using trench structure Download PDFInfo
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- KR960000229B1 KR960000229B1 KR1019920027310A KR920027310A KR960000229B1 KR 960000229 B1 KR960000229 B1 KR 960000229B1 KR 1019920027310 A KR1019920027310 A KR 1019920027310A KR 920027310 A KR920027310 A KR 920027310A KR 960000229 B1 KR960000229 B1 KR 960000229B1
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- trench
- oxide film
- semiconductor substrate
- formulating
- ion implantation
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- 238000000034 method Methods 0.000 title claims description 3
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 238000005468 ion implantation Methods 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
제1도는 LDD구조를 갖는 종래의 트랜지스터 단면도.1 is a cross-sectional view of a conventional transistor having an LDD structure.
제2도는 본 발명에 따른 트렌치형 트랜지스터 제조 공정도.2 is a process diagram of manufacturing a trench transistor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 채널영역1 semiconductor substrate 2 channel region
3 : 게이트 산화막 3′ : 게이트 전극3: gate oxide film 3 ': gate electrode
4 : 저농도 불순물 이온 주입 영역 5 : 고농도 불순물 이온 주입 영역4: low concentration impurity ion implantation region 5: high concentration impurity ion implantation region
6 : 스페이서 산화막 7 : 완충 산화막6 spacer oxide film 7 buffer oxide film
8 : 트렌치 9 : 폴리실리콘막8: trench 9: polysilicon film
10 : 산화막 11 : 금속막10 oxide film 11: metal film
본 발명은 MOSFET 소자의 제조 기술로서 DRAM, SRAM, ROM 등의 반도체 소자에 적용할 수 있는 트렌치(Trench) 구조를 이용한 수직 채널을 갖는 모스트랜지스터(MOSFET) 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOSFET having a vertical channel using a trench structure applicable to semiconductor devices such as DRAM, SRAM, ROM, and the like.
일반적으로 반도체 제품의 고집적화(64M, 256M, DRAM...) 실현을 위해 소자의 크기가 소형화됨에 따라 게이트 산화막의 두께 및 채널 길이의 감소로 단채널(Short channel), DIBL(Drain Induced Barrier Lowering), 펀치쓰로우(Punchthrough) 특성등이 크게 저하되어 정상적인 소자의 동작이 불가능하게 된다. 따라서 채널 (Channel)의 불순물 이온 주입 농도를 높여 왔다.In general, as the size of the device is miniaturized to realize high integration (64M, 256M, DRAM ...) of semiconductor products, short channel (Drain Induced Barrier Lowering) due to the reduction of the thickness and channel length of the gate oxide layer As a result, the punch-through characteristic is greatly deteriorated, and normal operation of the device becomes impossible. Therefore, the impurity ion implantation concentration of the channel has been increased.
종래의 반도체 소자 제조 방법을 제1도를 통하여 살펴보면, 도면에서 1은 반도체 기판, 2는 채널영역, 3은 게이트 산화막, 3′는 게이트 전극 4는 저농도 불순물 이온 주입 영역, 5는 고농도 불순물 이온 주입 영역, 6은 스페이서 산화막을 각각 나타낸다.Referring to FIG. 1, a semiconductor substrate, a channel region, a gate oxide film, a gate electrode 4, a low concentration impurity ion implantation region, and a high concentration impurity ion implantation are shown in FIG. Regions 6 denote spacer oxide films, respectively.
도면에 도시된 바와 같이 종래의 MOS 트랜지스터는 LDD(Lightly Doped Drain ; 이하 LDD라 칭함) MOSFET 구조로서, 반도체 기판(1) 상에 게이트 산화막 (3)을 형성하고 상기 게이트 산화막(3) 밑 부분위의 반도체 기판(1)에 고농도 불순물 이온을 주입하여 문턱전압 조절을 하여 채널 영역(2)을 형성한다. 이어서, 상기 게이트 산화막(3)상에 게이트전극(3′)을 형성하고 저농도의 불순물을 주입하여 저농도 불순물이 이온 주입 영역(4)을 형성한다. 끝으로, 상기 게이트 전극 측벽에 스페이서 산화막(6)을 형성한 다음에 고농도 불순물을 주입하여 고농도 불순물 이온 주입 영역(5)를 형성해 왔다.As shown in the drawing, the conventional MOS transistor is an LDD (Lightly Doped Drain) MOSFET structure, which forms a gate oxide film 3 on a semiconductor substrate 1 and is located below the gate oxide film 3. A high concentration of impurity ions are implanted into the semiconductor substrate 1 to control the threshold voltage to form the channel region 2. Subsequently, a gate electrode 3 'is formed on the gate oxide film 3, and a low concentration of impurities are implanted to form an ion implantation region 4 with low concentration of impurities. Finally, a high concentration impurity ion implantation region 5 has been formed by forming a spacer oxide film 6 on the sidewall of the gate electrode and then implanting a high concentration impurity.
그러나 상기 종래의 MOS 트랜지스터는 채널 농도의 증가로 캐리어(carrier)의 이동도(mobility)가 감소한다. 그로 인하여 채널의 전도도(Transconductance (Gm) ) 및 전류특성의 감소와 고에너지 전자에 의한 소자의 신뢰성이 저하되는 문제점이 있었다.However, in the conventional MOS transistor, carrier mobility decreases due to an increase in channel concentration. As a result, there is a problem in that the conductivity (Gm) and current characteristics of the channel are decreased, and the reliability of the device due to high energy electrons is deteriorated.
따라서, 상기 문제점을 해결 하기 위하여 안출된 본 발명은 낮은 농도의 긴 채널을 형성하여 트랜지스터의 성능을 향상 시킬 수 있는 트렌치(Trench) 구조를 이용한 수직 채널을 갖는 모스트랜지스터(MOSFET)제조 방법을 제공 하는데 그 목적이 있다.Accordingly, the present invention devised to solve the above problems provides a method of manufacturing a MOSFET having a vertical channel using a trench structure that can improve the performance of a transistor by forming a long channel of low concentration. The purpose is.
상기 목적을 달성 하기 위하여 본 발명은, 반도체 기판 상에 완충 산화막을 형성하고 문턱전압 조절을 위한 고농도 이온 주입을 하여 채널 영역을 형성하는 제1단계, 상기 제1단계 후에 소오스 및 드레인 형성을 위해 고농도 불순물 이온 주입 영역을 형성하는 제2단계, 상기 제2단계 후에 상기반도체 기판의 일정부위를 식각하여 트렌치를 형성하는 제3단계, 및 상기 제3단계 후에 게이트 산화막, 폴리실리콘막을 차례로 증착하여 상기 트렌치가 형성되어 있는 부위의 폴리실리콘을 제외하고 선택적으로 상기 폴리실리콘막을 식각하여 게이트 전극을 형성하는 제4단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a first step of forming a channel region by forming a buffer oxide layer on a semiconductor substrate and implanting high concentration ions for controlling a threshold voltage, and high concentration for source and drain formation after the first step. A second step of forming an impurity ion implantation region, a third step of forming a trench by etching a predetermined portion of the semiconductor substrate after the second step, and after the third step, a gate oxide film and a polysilicon film are sequentially deposited to form the trench A fourth step of forming a gate electrode by selectively etching the polysilicon film except for the polysilicon of the portion is formed.
이하, 첨부된 도면 제2도를 참조하여 본 발명에 따른 일실시예를 상세히 설명하면, 도면에서 2는 채널영역, 5는 고농도 불순물 이온 주입 영역, 7은 완충 산화막, 8은 트렌치, 9는 폴리실리콘막, 10은 산화막, 11은 금속막을 각각 나타낸다.Hereinafter, an embodiment according to the present invention will be described in detail with reference to FIG. 2. In the drawings, 2 is a channel region, 5 is a high concentration impurity ion implantation region, 7 is a buffer oxide layer, 8 is a trench, and 9 is a poly The silicon film, 10 is an oxide film, and 11 is a metal film, respectively.
먼저, 종래이 LDD MOSFET 구조의 단점을 보완하기 위하여 반도체 기판(1)상에 완충 산화막(7)을 형성하고(제2도(a)).First, the buffer oxide film 7 is formed on the semiconductor substrate 1 in order to compensate for the disadvantages of the conventional LDD MOSFET structure (FIG. 2 (a)).
문턱전압 조절을 위하여 고농도 이온 주입을 하여 채널 영역(2)을 형성한다 (제2도(b)).In order to control the threshold voltage, a high concentration of ion implantation is performed to form the channel region 2 (FIG. 2B).
이어서 소오스 및 드레인 형성을 위해 고농도 불순물을 주입하여 고농도 불순물 이온 주입 영역(5)을 형성한다(제2도(c)).Subsequently, a high concentration impurity ion implantation region 5 is formed by implanting a high concentration impurity to form a source and a drain (FIG. 2C).
계속하여 상기 반도체 기판(1)의 일정부위를 식각하여 트렌치(8)를 형성한다(제2도(d)).Subsequently, a portion of the semiconductor substrate 1 is etched to form a trench 8 (FIG. 2D).
상기 트렌치(8)형성 후에 게이트 산화막(3), 폴리실리콘막(9)을 차례로 증착한다(제2도(e)).After the trench 8 is formed, the gate oxide film 3 and the polysilicon film 9 are sequentially deposited (FIG. 2E).
끝으로, 상기 트렌치(8)가 형성되어 있는 부위의 폴리실리콘을 제외하고 선택적으로 상기 폴리실리콘막(9)을 식각하여 게이트 전극(3′)을 형성한 다음에 산화막 (10)을 증착하고 상기 산화막(10)을 선택 식각하여 콘택홀을 이루어 금속막(11) 증착으로 소오스 및 드레인 콘택을 이룬다(제2도(f)).Finally, except the polysilicon of the portion where the trench 8 is formed, the polysilicon film 9 is selectively etched to form a gate electrode 3 ', and then an oxide film 10 is deposited. The oxide film 10 is selectively etched to form contact holes to form source and drain contacts by depositing the metal film 11 (FIG. 2F).
상기 본 발명의 트랜지스터는 고농도로 이온 주입된 채널 지역의 농도와 채널의 길이로서 문턱 전압과 펀치쓰로우를 억제하게 된다. 따라서 채널 지역의 농도도 이온 주입 영역 부근을 제외하고는 기판의 웰(well) 농도 수준으로 낮기 때문에 종래의 LDD 구조에서와 같이 채널 농도의 증가로 인하여 이동도 감소, 채널의 전도도(Gm) 및 전류의 감소를 방지할 수 있다. 그리고 채널이 트렌치 구조로 형성됨으로써 효과적인 채널 길이가 증가되어 단채널 효과(short channel effect), 펀치쓰로우 특성이 종래의 구조보다 향상되는 효과가 있다. 또한 소오스 및 드레인 불순물 이온 주입후 게이트를 형성함으로써 마스크 미스얼라인(Mask misalign)에 의한 영향이 적은 효과가 있다.The transistor of the present invention suppresses the threshold voltage and the punch-throw as the concentration and the length of the channel region implanted at a high concentration. Therefore, since the concentration in the channel region is low to the well concentration level of the substrate except near the ion implantation region, the mobility is decreased due to the increase of the channel concentration, the conductivity of the channel (Gm) and the current as in the conventional LDD structure. Can be prevented. In addition, since the channel is formed in the trench structure, the effective channel length is increased, so that the short channel effect and the punch-through characteristic are improved than the conventional structure. In addition, since the gate is formed after the source and drain impurity ions are implanted, the effect of the mask misalignment is reduced.
Claims (1)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920027310A KR960000229B1 (en) | 1992-12-31 | 1992-12-31 | Making method of vertical channel mosfet using trench structure |
| JP5335976A JPH06232395A (en) | 1992-12-31 | 1993-12-28 | Manufacture of transistor containing vertical channel of trench structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920027310A KR960000229B1 (en) | 1992-12-31 | 1992-12-31 | Making method of vertical channel mosfet using trench structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940016927A KR940016927A (en) | 1994-07-25 |
| KR960000229B1 true KR960000229B1 (en) | 1996-01-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920027310A KR960000229B1 (en) | 1992-12-31 | 1992-12-31 | Making method of vertical channel mosfet using trench structure |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH06232395A (en) |
| KR (1) | KR960000229B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101147314B1 (en) * | 2010-10-25 | 2012-05-18 | 고려대학교 산학협력단 | Vertical electrode structure using trench and method for fabricating the vertical electrode structure |
| US8455942B2 (en) | 2005-12-28 | 2013-06-04 | Hynix Semiconductor Inc. | Semiconductor device having vertical-type channel |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101867337B1 (en) * | 2012-01-30 | 2018-06-15 | 삼성전자주식회사 | An image sensor and method of manufacturing the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61239669A (en) * | 1985-04-16 | 1986-10-24 | Citizen Watch Co Ltd | Semiconductor integrated circuit |
-
1992
- 1992-12-31 KR KR1019920027310A patent/KR960000229B1/en not_active IP Right Cessation
-
1993
- 1993-12-28 JP JP5335976A patent/JPH06232395A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8455942B2 (en) | 2005-12-28 | 2013-06-04 | Hynix Semiconductor Inc. | Semiconductor device having vertical-type channel |
| US8981467B2 (en) | 2005-12-28 | 2015-03-17 | SK Hynix Inc. | Semiconductor device having vertical-type channel |
| KR101147314B1 (en) * | 2010-10-25 | 2012-05-18 | 고려대학교 산학협력단 | Vertical electrode structure using trench and method for fabricating the vertical electrode structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06232395A (en) | 1994-08-19 |
| KR940016927A (en) | 1994-07-25 |
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