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KR950034828A - Manufacturing method and gate structure of MOS transistor using copper electrode - Google Patents

Manufacturing method and gate structure of MOS transistor using copper electrode Download PDF

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KR950034828A
KR950034828A KR1019940011922A KR19940011922A KR950034828A KR 950034828 A KR950034828 A KR 950034828A KR 1019940011922 A KR1019940011922 A KR 1019940011922A KR 19940011922 A KR19940011922 A KR 19940011922A KR 950034828 A KR950034828 A KR 950034828A
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material layer
diffusion barrier
barrier material
copper
forming
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KR1019940011922A
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KR0150986B1 (en
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이종호
문종
주석호
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

구리전극을 갖는 모스 트랜지스터의 제조방법 및 게이트 구조가 개시되어 있다. 반도체기판 상에, 게이트전극이 형성될 부위를 개구시키도록 질화막 패턴을 형성한다. 질화막 패턴의 측면부에 불순물이 도우프된 스페이서를 형성하고, 열처리 공정에 의해 스페이서 내의 불순물을 기판으로 확산시켜 제1소오스 및 드레인영역을 형성한다. 스페이서에 의해 노출된 기판 상에 게이트절연막을 형성한 다음, 결과물상에 확산 방지 물질층 및 구리막을 차례로 형성한다. 게이트전극이 형성될 부위 이외의 구리막 및 확산 방지 물질층을 식각하여, 구리막으로 이루어진 게이트전극을 형성한 다음, 질화막 패턴을 제거한다. CMP방법 또는 에치백 방법과 고체간 접촉에 의한 확산방법으로 구리전극을 적용한 0.1㎛의 게이트길이를 갖는 모스 트랜지스터를 제조할 수 있다.A manufacturing method and a gate structure of a MOS transistor having a copper electrode are disclosed. On the semiconductor substrate, a nitride film pattern is formed so as to open a portion where a gate electrode is to be formed. A spacer doped with impurities is formed on the side surface of the nitride film pattern, and the first source and drain regions are formed by diffusing impurities in the spacer onto the substrate by a heat treatment process. A gate insulating film is formed on the substrate exposed by the spacers, and then a diffusion barrier material layer and a copper film are sequentially formed on the resultant. The copper film and the diffusion barrier material layer other than the portion where the gate electrode is to be formed are etched to form a gate electrode made of a copper film, and then the nitride film pattern is removed. A MOS transistor having a gate length of 0.1 μm to which a copper electrode is applied may be manufactured by a CMP method or an etch back method and a diffusion method by contact between solids.

Description

구리전극을 적용하는 모스 트랜지스터의 제조방법 및 게이트 구조Manufacturing method and gate structure of MOS transistor using copper electrode

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

Claims (10)

반도체기판 상에, 게이트전극이 형성될 부위를 개구시키도록 질화막 패턴을 형성하는 단계; 상기 질화막 패턴의 측면부에 불순물이 도우프된 스페이서를 형성하는 단계; 열처리 공정에 의해 상기 스페이서 내의 불순물을 상기 기판으로 확산시켜 제1소오스 및 드레인영역을 형성하는 단계; 상기 스페이서에 의해 노출된 상기 기판 상에 게이트절연막을 형성하는 단계; 상기 결과물 상에 확산 방지 물질층 및 구리막을 차례로 형성하는 단계; 게이트전극이 형성될 부위 이외의 상기 구리막 및 확산 방지 물질층을 식각하여, 상기 구리막으로 이루어진 게이트전극을 형성하는 단계; 및 상기 질화막 패턴을 제거하는 단계를 구비하는 것을 특징으로 하는 반도체장치의 제조방법.Forming a nitride film pattern on the semiconductor substrate so as to open a portion where a gate electrode is to be formed; Forming a spacer doped with an impurity on a side surface of the nitride film pattern; Diffusing impurities in the spacers to the substrate by a heat treatment process to form first source and drain regions; Forming a gate insulating film on the substrate exposed by the spacer; Sequentially forming a diffusion barrier material layer and a copper film on the resultant; Etching the copper layer and the diffusion barrier material layer other than a portion where a gate electrode is to be formed to form a gate electrode formed of the copper layer; And removing the nitride film pattern. 제1항에 있어서, 상기 확산 방지 물질층 및 구리막을 형성하는 단계는, 상기 제1소오스 및 드레인영역이 형성된 결과물 상에 확산 방지 물질층을 형성하는 단계; 상기 물질층 상에 포토레지스트를 도포하는 단계; 상기 포토레지스트를 에치백하여, 게이트전극이 형성될 부위에만 상기 포토레지스트를 남기는 단계; 상기 잔류하는 포토레지스트를 마스크로서 사용하여, 게이트전극이 형성될 부위 이외의 상기 확산 방지 물질층을 식각하는 단계; 상기 잔류하는 포토레지스트를 제거하는 단계; 및 상기 잔류하는 확산 방지 물질층 상에 선택적으로 구리를 증착하여 구리막을 형성하는 단계로 이루어진 것을 특징으로 하는 모스트랜지스터의 제조방법.The method of claim 1, wherein the forming of the diffusion barrier material layer and the copper film comprises: forming a diffusion barrier material layer on a resultant material on which the first source and drain regions are formed; Applying a photoresist on the material layer; Etching back the photoresist, leaving the photoresist only at a portion where a gate electrode is to be formed; Etching the diffusion barrier material layer other than a portion where a gate electrode is to be formed by using the remaining photoresist as a mask; Removing the remaining photoresist; And selectively depositing copper on the remaining diffusion barrier material layer to form a copper film. 제1항에 있어서, 상기 확산 방지 물질층은 CMP방법에 의해 식각되는 것을 특징으로 하는 모스트랜지스터의 제조방법.The method of claim 1, wherein the diffusion barrier material layer is etched by a CMP method. 제1항에 있어서, 상기 구리막 및 확산 방지 물질층은 CMP방법에 의해 식각되는 것을 특징으로 하는 모스트랜지스터의 제조방법.The method of claim 1, wherein the copper film and the diffusion barrier material layer is etched by a CMP method. 제1항에 있어서, 상기 스페이서를 구성하는 물질로서 불순물이 도우프된 폴리실리콘을 사용하는 것을 특징으로 하는 모스 트랜지스터의 제조방법.2. The method of claim 1, wherein polysilicon doped with impurities is used as a material for forming the spacer. 제1항에 있어서, 상기 제1소오스 및 드레인영역을 형성하는 단계 후, 상기 스페이서를 마스크로서 사용하여 트랜지스터의 문턱전압 조절을 위한 불순물 이온을 주입하는 단계를 더 구비하는 것을 특징으로 하는 모스트랜지스터의 제조방법.The method of claim 1, further comprising, after forming the first source and drain regions, implanting impurity ions for controlling the threshold voltage of a transistor using the spacer as a mask. Manufacturing method. 제1항에 있어서, 상기 질화막 패턴을 제거하는 단계 후, 상기 게이트전극을 마스크로서 사용하여 제2소오스 및 트레인영역을 형성하기 위한 불순물 이온을 주입하는 단계를 더 구비하는 것을 특징으로 하는 모스 트랜지스터의 제조방법.The MOS transistor of claim 1, further comprising, after removing the nitride layer pattern, implanting impurity ions for forming a second source and a train region using the gate electrode as a mask. Manufacturing method. 반도체기판; 서로 떠렁져서 상기 반도체기판 상에 형성된 한쌍의 스페이서; 상기 스페이서 사이의 노출된 반도체기판 상에 형성된 게이트절연막; 상기 게이트절연막 상에 형성된 확산 방지 물질층; 및 상기 확산 방지 물질층 상에 형성된 구리전극을 구비하는 것을 특징으로 하는 반도체장치의 게이트 구조.Semiconductor substrates; A pair of spacers floating on each other and formed on the semiconductor substrate; A gate insulating film formed on the exposed semiconductor substrate between the spacers; A diffusion barrier material layer formed on the gate insulating layer; And a copper electrode formed on the diffusion barrier material layer. 제8항에 있어서, 상기 게이트절연막은 상기 스페이서 상에도 형성된 것을 특징으로 하는 반도체장치의 게이트 구조.10. The gate structure of claim 8, wherein the gate insulating film is also formed on the spacer. 제8항에 있어서, 상기 스페이서는 불순물이 도우프된 폴리실리콘으로 이루어진 것을 특징으로 하는 반도체장치의 게이트 구조.10. The gate structure of claim 8, wherein the spacer is made of polysilicon doped with impurities. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940011922A 1994-05-30 1994-05-30 Manufacturing method for mos transistor with copper electrode and its gate structure KR0150986B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100866113B1 (en) * 2002-06-29 2008-10-31 매그나칩 반도체 유한회사 Method for forming gate in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100866113B1 (en) * 2002-06-29 2008-10-31 매그나칩 반도체 유한회사 Method for forming gate in semiconductor device

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