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KR950015727A - 반도체 장치 및 그 제조방법 - Google Patents

반도체 장치 및 그 제조방법 Download PDF

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Publication number
KR950015727A
KR950015727A KR1019930024581A KR930024581A KR950015727A KR 950015727 A KR950015727 A KR 950015727A KR 1019930024581 A KR1019930024581 A KR 1019930024581A KR 930024581 A KR930024581 A KR 930024581A KR 950015727 A KR950015727 A KR 950015727A
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South Korea
Prior art keywords
printed circuit
circuit board
semiconductor chip
semiconductor device
electrode connection
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KR1019930024581A
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English (en)
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KR970000214B1 (ko
Inventor
권영신
안승호
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김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019930024581A priority Critical patent/KR970000214B1/ko
Priority to CN94117079A priority patent/CN1041254C/zh
Priority to JP6285124A priority patent/JP2966300B2/ja
Priority to US08/345,385 priority patent/US5594275A/en
Publication of KR950015727A publication Critical patent/KR950015727A/ko
Application granted granted Critical
Publication of KR970000214B1 publication Critical patent/KR970000214B1/ko

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  • Wire Bonding (AREA)
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Abstract

BGA패키지(Ball Grid Array Pakage)에 있어서, 종래의 BGA패키지의 2차원적 평면실장의 범주를 벗어나서 현재 적용되고 있는 주기판상의 실장공정과 완전한 호환성을 유지하며 3차원적 표면실장이 가능하도록 인쇄회로 기판의 하면에 적어도 하나의 반도체 칩이 탑재되어 있고, 상기 반도체 칩의 전극단자와 인쇄회로기판의 단자사이가 와이어로 본딩되어 있으며, 반도체 칩 및 와이어의 접속부가 봉지 수지로 본지가 되어 있는 반도체 장치에 있어서; 상기 인쇄회로기판은 역으로 실장되고, 이 기판의 단자는 관통공에 의해 외부 단자와 접속되며, 상기 인쇄회로기판의 상면에 적어도 하나의 상기 반도체 장치가 적층되어 있으며, 상기 각각의 반도체 장치는 솔더복을 매개로 층간 접속을 하여 외부 단자인 리드에 의해 또 다른 인쇄회로기판상에 실장되는 3차원 구조의 반도체 장치를 마련하였다. 따라서 SOJ 패키지 내부에 적층이 가능한 BGA 패키지를 이용하여 층간 접속을 행하는 3차원적 실장구조를 채택하여 실장효율을 향상시킨 반도체 장치의 제조에 적용된다.

Description

반도체 장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 이 발명에 따른 반도체 장치의 일실시예를 나타내는 수직 단면도,
제3도는 주기판상에 형성된 랜드패턴, 관통홀 및 전극연결단자의 형성을 도시한 제2도의 일부 평면도.

Claims (10)

  1. 주기판의 하부 표면과 상부 표면의 양끝단의 중심부에 관통공을 형성하는 공정과; 상기 관통공을 중심으로 카파(Cu), 니켈(Ni) 및 골드(Gu)를 차례로 도금하여 금속 도금층을 형성하는 프래팅 공정과; 상기 주기판의 하부 및 상부 표면에 형성된 금속 도금층 주면에 랜드패턴, 전극 연결단자 및 볼 그리드 어레이를 일정한 패턴 형상으로 마련하는 패턴닝 공정과; 상기 주기판의 중앙에 접착제를 매개로 하여 반도체 칩을 실장하고, 상기 전극 연결단자와 와이어 본딩한 후, 패키지 몸체를 형성하는 공정과; 상기 볼 그리드 어레이에 일정한 형태의 솔더볼을 실장하는 공정을 구비함을 특징으로 하는 반도체 장치의 제조방법.
  2. 주기판의 하부 표면의 양끝단에 형성되어 있는 관통공 및 전극연결단자를 포함하는 다수개의 랜드패턴과, 상기 주기판의 상부 표면의 양끝단에 형성되어 있는 다수개의 볼 그리드 어레이와, 상기 주기판의 볼 그리드 어레이에 실장되어 있는 다수개의 솔더볼과, 상기 주기판의 하부표면의 중심부에 접착제를 매개로 하여 반도체 칩이 실장되고 전극연결단자와 와이어 본딩되며 EMC로 몰딩되어 있는 패키지 몸체를 구비하는 것을 특징으로 하는 반도체 장치.
  3. 인쇄회로기판의 하면에 적어도 하나의 반도체 칩이 탑재되어 있고, 상기 반도체 칩의 전극단자와 인쇄회로 기판의 단자사이가 와이어로 본딩되어 있으며, 반도체 칩 및 와이어의 접속부가 봉지 수지로 봉지가 되어 있는 반도체 장치에 있어서; 상기 인쇄회로기판은 역으로 실장되고, 이 기판의 단자는 관통공에 의해 외부 단자와 접속되며, 상기 인쇄회로기판의 상면에 적어도 하나의 상기 반도체 장치가 적층되어 있으며, 상기 각각의 반도체 장치는 솔더볼을 매개로 층간 접속을 하여 외부 단자인 리드에 의해 또 다른 인쇄회로기판상에 실장되는 3차원 구조의 반도체 장치.
  4. 제3항에 있어서, 인쇄회로기판은 BT(Bismaleimidetriazine) 레진, 내열 에폭시등의 내열성 기판으로 표면에는 0.5㎛ 정도의 금(Au)이 도금되어 있는 것을 특징으로 하는 3차원 구조의 반도체 장치.
  5. 제3항에 있어서, 상기 솔더볼을 매개체로 접속되어 있는 인쇄회로기판의 단자부가 링 또는 원형인 것을 특징으로 하는 3차원 구조의 반도체 장치.
  6. 제3항에 있어서, 상기 솔더볼을 매개체로 층간 접속되는 인쇄회로기판의 상/하면이 관통공 또는 비어(via)홀로 도통되도록 하는 것을 특징으로 하는 3차원 구조의 반도체 장치.
  7. 제3항에 있어서, 상기 인쇄회로기판 하면의 층간 접속단자는 관통공과 연결되어 있으며, 솔더볼로 접속되는 그 이외의 전도부와 관통공 부분을 각각 솔더 레지스트로 도포하는 것을 특징으로 하는 3차원 구조의 반도체 장치.
  8. 제3항에 있어서, 상기 인쇄회로기판의 외부단자인 리드는 카파 또는 얼로이로 프래팅되어 있는 것을 특징으로 하는 3차원 구조의 반도체 장치.
  9. 관통공, 전극 연결단자 및 랜드패턴을 포함하는 주기판 하부표면의 중심부에 접착제를 매개로 하여 반도체 칩이 실장되고 전극연결단자와 와이어 본딩된 후, EMC로 몰딩되어 있는 주패키지 몸체가 역방향으로 실장되어 있고; 상기 랜드패턴상에 제1 관통공, 제1 전극연결단자 및 제1 랜드패턴을 포함하는 제1 기판하부표면의 중심부에 접착제를 매개로 하여 제1 반도체 칩이 실장되고 제1 전극연결단자와 와이어 본딩된 후, EMC로 몰딩되어 있는 제1 패키지 몸체가 제1 솔더볼을 매개로 하여 역방향으로 실장되어 있으며; 상기 제1 랜드패턴상에 외부리드, 제2관통공, 제2 전극연결단자 및 제2 랜드패턴을 포함하는 제2 기판 하부표면의 중심부에 접착제를 매개로 하여 제2 반도체 칩이 실장되고 제2 전극연결단자와 와이어 본딩된 후, EMC로 몰딩되어 있는 제2 패키지 몸체가 제2 솔더볼을 매개로 하여 역방향으로 실장되어 있고; 상기 제2 랜드패턴상에 제3 관통공, 제3 전극연결단자 및 제3 랜드패턴을 포함하는 제3 기판 하부표면의 중심부에 접착제를 매개로 하여 제3 반도체 칩이 실장되고 제3 전극연결단자와 와이어 본딩된 후, EMC로 몰딩되어 있는 제3 패키지 몸체가 제3 솔더볼을 매개로 하여 역방향으로 실장되어 있는 3차원 구조의 반도체 장치.
  10. 제9항에 있어서, 상기 외부 단자인 리드가 표면 실장을 위해 J폼 또는 걸핑윙의 형상을 갖도록 절곡된 것을 특징으로 하는 3차윈 구조의 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930024581A 1993-11-18 1993-11-18 반도체 장치 및 그 제조방법 KR970000214B1 (ko)

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CN94117079A CN1041254C (zh) 1993-11-18 1994-10-05 三维结构的半导体器件
JP6285124A JP2966300B2 (ja) 1993-11-18 1994-11-18 半導体装置及びその製造方法
US08/345,385 US5594275A (en) 1993-11-18 1994-11-18 J-leaded semiconductor package having a plurality of stacked ball grid array packages

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