KR950001440Y1 - Dnl error mesurement circuit of a/d converter - Google Patents

Abstract

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Description

DNL error measurement circuit of analog / digital converter

1 is a block diagram of a DNL error measurement of a conventional analog / digital converter.

2a and 2b is a DNL error test block diagram of the present invention analog / digital converter.

(A)-(o) of FIG. 3 are the waveform diagrams of each part of FIG.

(A)-(c) of FIG. 4 are LSB change waveform diagrams of the A / D conversion output code according to the present invention.

5 illustrates an example DNL error of a 3-bit A / D converter.

* Explanation of symbols for main parts of the drawings

100: data output unit 200: latch control unit

300: data latch unit 400: input voltage range calculation unit

500: DNL error calculation unit 600: limit error range determination unit

11: clock generator 12, 21, 22: counter

13: Reference D / A Converter 14: Deuty

15: reference A / D converter 31-36: latch

4l-45, 51-53, 61, 62: adders 46, 54: multiplexer

The present invention relates to a DNL (Differential Nonlinearity) error test circuit in an analog / digital conversion circuit. In particular, the present invention can shorten the time required to detect an error and calculate a median value of a conversion noise section of an output code. The present invention relates to a DNL error measuring circuit of an analog / digital converter, which is suitable for detecting an error even in a test apparatus for a semiconductor integrated circuit capable of processing only a digital signal.

FIG. 1 is a block diagram of a DNL error measuring system of a conventional analog / digital converter. As shown in FIG. 1, the DUT 1 (A / D converter) corresponding to a device under test (DUT) is shown. Digital comparator 2A which compares and measures the digital codes inputted from the memory and stores the measurement result in the memory 2B, and analyzes the relationship between the data stored in the memory 2A and the input voltage and calculates an INL error. And an analog signal generator (2D) for outputting the analog signal divided by the control unit (2C) and the control unit (2C) to the measurement target DUT1 step by step. The operation of the system is described as follows.

The central processing unit 2C of the integrated circuit test apparatus 2 controls the analog signal generating unit 2D so that the analog signal subdivided within the input voltage range of the deut 1 from the deut 1 is The DU 10 accordingly converts an input analog signal into a digital signal and outputs the digital signal.

The digital comparator 2A of the integrated circuit test apparatus 2 repeatedly receives a digital code from the digital unit 1 and stores the digital code in the memory 2B.

In addition, the CPU 2C analyzes the relationship between the digital code stored in the memory 2B and the input voltage, calculates an analog voltage corresponding to the midpoint of each output code, and calculates the analogy from the value. In addition to calculating the DNL error of (1), an error is tested.

For example, when the number of bits applied to the de-uty 1 is 8 bits and the input voltage range is 0-5 [V], the number of bits applied to the integrated circuit test apparatus 2 is generally used for enhancing the resolution. 12 bits are used. In such a case, the step voltage inputted to the deunit 1 becomes approximately 122 MV (5V / 2 ¹² -1), and the measurement time of 10 MS is taken for each step, so that 0 [V] The total time taken from 1.22MV step to 5V is 4096 × 10MS ≒ 40sec.

As described above, in the conventional experimental apparatus, there is a defect that takes a relatively long time to measure, and there is a defect that lacks economic efficiency because it is a high-performance equipment capable of simultaneously processing analog signals and digital signals.

The present invention devised a DNL error measuring circuit that can satisfy the high measurement speed and low interval in order to solve such a conventional defect, it will be described in detail by the accompanying drawings.

2 is a block diagram of the DNL error measuring circuit of the present invention analog / digital converter. As shown in FIG. 2, a digital signal is generated using a clock generator and a counter, and the digital signal corresponding to the analog output is tested. Of the data output unit 100 and the data output unit 100 to generate respective A / D conversion outputs to be supplied to the input of the reference A / D converter having a higher resolution than that of the deut. A latch control unit 200 for outputting a latch control signal for latching each reference A / D converted code output from the data output unit 100 using the digital code output from the apparatus under measurement, and the latch control unit ( A data latch unit 300 for latching each of the reference A / D converted codes under the control of 200, and for outputting each code based on a code latched by the data latch unit 300; An input voltage calculator 400 for calculating a range of analog input voltages and calculating a center point of an output code when the output of the device under measurement is unstable due to transition noise; and an analog output from the input voltage calculator 400 The difference between the input voltage data and the data corresponding to 1 LSB of the device under measurement is obtained, and the DNL error calculation unit 500 generates an error signal according to the difference degree, and the degree of the DNL error is the limit of the error of a preset specification. It is composed of a limit error range determination unit 600 for determining whether the range is exceeded and outputs a determination signal according to the above, and will be described in detail with reference to FIGS. 3 to 5 attached to the operation and effect of the present invention. As follows.

For convenience of explanation, it is assumed that the deut 14 is a 3-bit A / D converter, the analog input range is 0V-7V, and the limit of the DNL specification (SPEC) is 1LSB.

Since Deuit 14 is a 3-bit A / D converter, 1 LSB = 7 / (2 ³ -1) = 1V, counter 12, reference D / A converter 13, and reference A / D converter 15 ) Uses 4 bits, 7 bits more than that for enhanced resolution.

The DNL error is measured using 2 ⁷ = 128 clocks supplied sequentially from the clock generator 11, and the counter 12 counts the clocks supplied from the clock generator 11 so that its output is " 0000000 " → " 0000001 " → >"" 1111111 ", and this output is supplied to the input of the reference D / A converter 13 so that the reference D / A converter 13 converts the analog voltage corresponding to the input. Will print.

At this time, when the output range of the reference A / D converter 15 is 0V-7V, 1 LSB = 7V / (2 ⁷ −1) ≒ 55MV. That is, each time the clock is increased, the output of the D / A converter 13 is increased by 55 MV, and this output is supplied to the inputs of the deutility 14 and the reference A / D converter 15.

When the input voltage of the deutility 14 increases and its LSB output Q ₀ is converted from the first " 0 " to " 1 " at the sixth clock (point A in FIG. 4 (c)), the reference The output data " 0000110 " of the A / D converter 15 is supplied to the latches 31, 32, 34 and 35, at which time the output Q ₀ of the deunit 14 " 1 " Is enabled, and the output data " 0000110 " of the reference A / D converter 15 is latched to the latch 32. "

Thus, because at the same time "1" is supplied to one side input terminal of the D yuti 14 output (Q ₀₎ "1" and NAND gate (ND21), the AND gate (AD21) by the output "1" of the counter 21 Is cleared to start counting, but its output (Q ₂ ) remains "0", so the output (Q) of flip-flop (FF22) also remains "0" and is inverted through inverter (I26). The flip-flop FF21 is released by the " 1 " outputted to the reference A / D converter 15 because the latch 31 is enabled by the output Q " 1 ". Data "0000110" is latched in the latch 31, and the latched data is supplied to the input terminals A ₀ -A _{A + 3} of the adder 41.

On the other hand, as shown in (c) of FIG. 4, the output Q ₀ of the deuit 14 drops to "0" at the seventh clock due to the transition noise of the deuit 14. Upon rising back to " 1 " at the ninth clock, the latch 32 is again latched enabled by its output Q ₀ to re-latch the output data " 0001001 " of the reference A / D converter 15 at this time. On the other hand, since the output Q ₂ of the counter 21 keeps the value "0", the output Q of the flip-flop FF21 continues to maintain the value "1", and thus the latch ( 31) continues to latch the previously latched data '0000110'.

Thereafter, after the output Q ₀ of the deuit 14 is stabilized to “1”, the output Q ₂ of the counter 21 is turned on at the fourth clock (the ninth clock of FIG. 3A). Is converted to " 1 ", thereby enabling the latch 33 to latch the data " 000100 " latched to the latch 32, and the latched data " 0001001 " It is supplied to the input terminal (B ₀ -B _{n + 3} ) of 41).

Accordingly, the adder 41 adds the data "0000110" and "0001001" supplied through the input terminals A ₀ -A _{n + 3} and (B ₀ -B _{n + 3} ), and the least significant bit of the result value "0001111". Discarding "1" and outputting the remaining data "0000111", this data "0000111" means the W point, that is, the middle point of 6 and 9 in Fig. 4 (c), wherein the D The voltage input to the utility 14 is 55 MV x 7 x 385 MV, which is the threshold voltage V _TH converted from the code "0" to the code "1".

After the outputs Q ₂ ) of the counters 21 and 22 are converted to “1”, the DNL test is started, and the outputs Q ₂ of the counters 21 and 22 occur from the beginning to the third time. Since the interval to be obtained is the first process of obtaining the DNL value, the determination output to the adder 62 until this time is ignored.

Since the output Q ₀ is inverted from " 1 " to " 0 " at the time when the 23 < th >"1" is outputted to the output terminal Q, and the latch "34" is enabled by the output "1", so that the data "0010111" output from the deutility 14 is the latch 34. Is latched in.

At the same time, the output Q ₀ of the deunit 14 is inverted to " 1 " through the inverter I31, and then supplied to the latch 35 to enable it, so The output data " 0010111 " is latched to the latch 35, and then the output Q ₂ becomes " 1 " the moment the counter 22 counts " 4 " Since the output Q ₀ of 14 maintains the stable state of "0", the latch 34 continues to latch the previously latched data "0010111", and at this time, the output of the flip-flop FF24 ( Q) The latch 36 is enabled by "1", and the data "0010111" latched in the latch 35 is latched in the latch 36.

Accordingly, the adder 42 adds data "0010111" and "0010111" respectively input through the input terminals A ₀ -A _{n + 3} and (B ₀ -B _{n + 3} ) to calculate the result value "0101110". After this, since the least significant bit "0" is discarded, data "0010111" and carry "0" are outputted therefrom. The data "0010111" is inverted back to "1101000" through the inverters I41-I43. It is output to the input terminal A ₀ -A _{n + 3} of the two's complement adder 43.

This means that at the 23rd clock, the output Q ₀ of the deunit 14 is stabilized after being converted from "1" to "0", where the voltage input to the deunit 14 is 1.265V. In Fig. 4 (c), X is the threshold point V _TH which is converted from the code " 1 " to " 2 ".

The complementary adder 43 of 2 receives data “1101000” input through the input terminals A ₀ -A _{n + 3} and data “0000001” input through the input terminals B ₀ -B _{n + 3} . In addition, data "1101001" is output therefrom, which is supplied to the input terminal B ₀ -B _{n + 3} of the adder 44.

Accordingly, the adder 44 stores data "0000111" input through the input terminals A ₀ -A _{n + 3} and two's complement "1101001" input through the input terminals B ₀ -B _{n + 3} . In addition, data "1110000" and carry "0" are outputted therefrom, and this data "1110000" is directly supplied to the input terminals A ₀ -A _{n + 3} of the multiplexer 46 and the inverters I44-I46 are supplied. After inverting to " 0001111 ", it is supplied to the input terminals A ₀ -A _{n + 3 of the} two's complement adder 45, which is input through the input terminal BB _{n + 3} in the adder 45. In addition to the data "0000001", the result value "001000" is supplied to the input terminal B ₀ -B _{n + 3} of the multiplexer 46.

The multiplexer 46 selects data supplied to the input terminals A ₀ -A _{n + 3} when the carry output Carry output from the adder 44 is "1", and input terminal B when "0". ₀ -B _{n + 3} ) to select the data input. In this case, since the carry output is "0", the data "001000" supplied through the input terminal B ₀ -B _{n + 3} is selected. It outputs to the input terminal A ₀ -A _{n + 3} of the adder 52. This value is the intermediate value between the W point and the X point in (c) of FIG. Belongs to.

On the other hand, when the 1 LSB level signal (which is 1V in this case) of the deutility 14 is input to the reference A / D converter 15, the data “0010010” output therefrom is transmitted through the inverters I51-I53. Inverted, " 1101101 " is supplied to the input terminal A ₀ -A _{n + 3} side of the two's complement adder 51, which is input through the input terminal B ₀ -B _{n + 3} in the adder 51. The data "0000001" input through the data to be added and the data "1101110" outputted therefrom are supplied to the input terminals B ₀ -B _{n + 3} of the adder 52.

Accordingly, the adder 52 adds data "0010000" supplied through the input terminals A ₀ -A _{n + 3} and data "1101110" supplied through the input terminals B ₀ -B _{n + 3} . The result value "1111110" is supplied to the input terminals A ₀ -A _{n + 3} of the multiplexer 54 and the carry output "0" is supplied to the selection terminal S side of the multiplexer 54, on the other hand, the result value. The data " 1111110 " is inverted to " 0000001 " via the inverters I54-I56 and supplied to the input terminals A ₀ -A _{n + 3 of the} two's complement adder 53, which is input from the adder 53. In addition to the data "0000001" supplied through the terminals B ₀ -B _{n + 3} , the resulting value "0000010" is supplied to the multiplexer 54 to the input terminals B ₀ -B _{n + 3} .

In this case, since the carry output of the adder 52 is "0", the multiplexer 54 selects and outputs the data "0000010" supplied through the input terminals B ₀ -B _{n + 3} . The DNL error value in the output code 1 of the deutility 14 is 1/8 ≒ 0.1LSB, which is the input terminal B ₀ of the adder 62 for GO / NOGO determination. -B _{n + 3} ) side.

When the DNL specification level (in this case, 1 LSB is defined as 1 V) is input to the reference A / D converter 15, the code output therefrom is "0010010", which is used to drive the inverters I61-I63. After being inverted to " 1101101 ", it is supplied to the input terminals A ₀ -A _{n + 3 of the} two's complement adder 61, which is input through the input terminals B ₀ -B _{n + 3} . 0000001 "and" 1101110 "are supplied from the adder 61 to the input terminal B ₀ -B _{n + 3} of the adder 62.

Therefore, the adder 62 is connected through the DNL level and the input terminals B ₀ -B _{n + 3} of the first output code of the Deuit 14 inputted through the input terminals A ₀ -A _{n + 3} . It adds two's complement of the limit specification level of the input DNL error, and as a result, the carry outputs "0", which is input to the to-be-deleted side of the input terminal A ₀ -A _{n + 3} of the adder 62. It means less than the supervision on the terminals (B ₀ -B _{n + 3} ), that is, since the DNL error 0.1LSB in the first code of the Deuit 14 is smaller than the limit spec level 1LSB, it is determined to be normal. do.

After the measurement of the first code through the above process, the clock increases again, and at the 36 th clock, the latches 31 and 32 latch the output data “0100100” of the reference A / D converter 15 and 40 At the first clock, the latch 33 latches the data " 0100100 " corresponding to the point Y in FIG.

As a result, the adder 41 outputs "1001000" and carry "0", where the least significant bit is discarded and the remaining data "0100100" and carry "0" are input terminals A ₀ -A of the adder 44. _{n + 3} ) side, which is added to the two's complement data "1101001" of the X point data "0010111" input through the input terminals B ₀ -B _{n + 3} , and as a result, the data is deata "0001101" and The carry "1" is outputted, and since the carry is "1", the multiplexer 46 selects and outputs the data "0001101" supplied through the input terminals A ₀ -A _{n + 3} , which is an adder. Supplied to the input terminal A ₀ -A _{n + 3} of 52 and added via the input terminals B ₀ -B _{n + 3} to the data " 1101110 " Data "1111011" and carry "0" are output to the input terminals A ₀ -A _{n + 3} of the multiplexer 54.

The output data " 111011 " of the adder 52 is inverted to " 0000100 " via the inverters I54-I56 and supplied to the input terminals A ₀ -A _{n + 3 of the} two's complement adder 53. It is added with data "0000001" input through the input terminals B ₀ -B _{n + 3} , and as a result, "000101" is output from the adder 53, which is an input terminal B ₀ of the multiplexer 54. -B _{n + 3} ) will be output.

Since the carry of the adder 52 is "0", the multiplexer 54 selects the data "0000101" input through the input terminals B ₀ -B _{n + 3} and outputs the same, which is the DUT14. The DNL error level in the second code of). That is, since the values of the output terminals Q ₀ and Q ₂ are "1", the DNL level is 5/16 ≒ 0.3LSB, and this data is the input terminals A ₀ -A _{n + 3} of the adder 62. Is added to the data " 0000001 "supplied to its input terminal (B ₀ -B _{n + 3} ) side, the result is a carry of " 0 " The DNL error 0.3LSB is within 1 LSB of the limit specification, meaning that it is determined to be normal.

In this way, when measuring the N-bit A / D converter DNL, 2 ^{n + 4} clocks are supplied through the clock generator 11, and the output terminal Q ₂ of the counters 21 and 22 is "1." Whenever "is outputted, the carry output of the adder 62 is monitored, and if a carry is generated therefrom, it is determined to fail, and if no carry is generated, a pass is determined.

In this way, when the DNL of an 8-bit A / D converter is measured at a clock frequency of 2KHZ (T = 0.5MS), it takes 2 ^{(8 + 4)} × 0.5MS ≒ 2 seconds to achieve 41 seconds. It can be seen that it is significantly shortened to the extent that it is not compared.

As described in detail above, the present invention greatly reduces the DNL measurement time, provides convenience in use, and enables the measurement to be extended even by using an integrated circuit test equipment that can process only digital signals. It works.

Claims (7)

The digital signal is generated by using a clock generator and a counter, and the digital signal is supplied to the input of the digital unit to which the corresponding analog output is tested, and also to the input of the reference A / D converter having a higher resolution than the digital unit. A reference A / D output from the data output unit 100 using a data output unit 100 for generating an A / D conversion output of the digital output unit and a digital code output from the apparatus under measurement of the data output unit 100. A latch control unit 200 for outputting a latch control signal for latching each converted cog, a data latch unit 300 for latching each of the reference A / D converted codes under the control of the latch control unit 200; Based on the code latched by the data latch unit 300, a range of analog input voltages for outputting each code is calculated, and if the output of the device under measurement is unstable due to transition noise, The difference between the input voltage calculating unit 400 for calculating the center point of the data, and the analog input voltage data output from the input voltage calculating unit 400 and the data corresponding to 1 LSB of the device to be measured is calculated according to the difference degree. DNL error calculation unit 500 for generating an error signal and a limit error range determination unit 600 for determining whether the degree of the DNL error exceeds an error limit range of a preset specification and outputting a determination signal accordingly. Features DNL error measurement circuits for analog / digital converters. The apparatus of claim 1, wherein the data output unit (100) includes a clock generator (11) for generating a basic clock required by the system, a counter (12) for counting a clock supplied from the clock generator (11), A reference D / A converter 13 that receives the output of the counter 12 and outputs a reference D / A converted signal, and converts an analog signal output from the reference D / A converter 13 into a digital signal The digital signal output from the reference D / A converter 13 to measure the digital unit 14 and the DNL of the digital signal converted by the digital unit 14 is higher than that of the digital unit 14. A DNL error measurement circuit of an analog / digital converter, comprising: a reference A / D converter (15) for converting. 2. The latch control unit (200) of claim 1, wherein the latch control unit (200) is a counter (21) that is cleared to start counting when the least significant bit output of the unity (14) is changed from high to low, and the least significant bit of the unity (14). The counter 22, which is cleared when the output transitions from low to high and starts counting, and under the control of the output Q ₂ of the counter 21, the least significant bit output of the deity 14 is initially low to high. The flip-flop (FF21) outputs the latch enable signal when converted to, the flip-flop (FF22) for outputting the latch enable signal each time it is converted from low to high, and the output (Q ₂ ) of the counter (22). Under control, the flip-flop FF23 outputs a latch enable signal when the lowest bit output of the deity 14 is first changed from high to low, and a flip outputs a latch enable signal whenever it is converted from high to low. Consists of flops (FF24) Characterized in that the analog / digital converter of the DNL error measurement circuit for. The data latch unit 300 of claim 1, wherein the data latch unit 300 is enabled by the control of the flip-flop FF21 and latches data output from the reference A / D converter 15. Each time the output of the least significant bit of 14 becomes high, the latch 32 latches data output from the reference A / D converter 15, and the latch 32 is enabled by the control of the flip-flop FF22. A latch 33 for latching data latched on the latch), a latch 34 for latching data output from the reference A / D converter 15 enabled by the control of the flip-flop FF23, Whenever the output of the least significant bit of (14) goes low, a latch 35 for latching data output from the reference A / D converter 15 and the control of the flip-flop FF24 enable the latch ( 35) a latch 36 for latching data latched to DNL error measurement circuit. The method according to claim 1, wherein the input voltage range calculator 400 adds the output data of the latches 31 and 33 to each other, and then calculates an intermediate value thereof, a latch 34, After the output data of (36) are exhausted, an adder 42 for calculating the intermediate value thereof, an adder 43 and an inverter I41-I43 for calculating a two's complement to the output of the adder 42, An adder 44 that adds the output data of the adders 41 and 43 to each other, an adder 45 and an inverter I44-I46 for calculating a two's complement to the output of the adder 44, and the adder And a multiplexer (46) for selecting the output data of the adder (44) or the output data of the adder (45) according to the carry output of (44). The DNL error calculating unit 500 calculates two's complement of the data output from the 1 LSB level signal of the de-ut 14 when it is input to the reference A / D converter 15. Adder 51 and an inverter I51-I53, an adder 52 that adds the outputs of the adders 46, 51, and an adder that calculates two's complement of the output data of the adder 52. (53) and inverters (I54-I56), and a multiplexer (54) for selectively outputting the output of the adder (52) or the output of the adder (53) according to the carry output of the adder (46). DNL error measurement circuit of analog / digital converter. The adder 61 of claim 1, wherein the limit error range determination unit 600 calculates a two's complement for data output from the DNL specification level signal when it is input to the reference A / D converter 15. And an adder 62 which adds the output data of the adder 61 to the output data of the multiplexer 54 and determines the range of the marginal error based on the result of the inverters I61-I63. DNL error measurement circuit of digital converter.