KR950005094Y1 - Data sense amplifier circuit - Google Patents

Abstract

No content.

Description

Data sense amplifier circuit

1 is a conventional data sense amplifier circuit diagram.

2 is a sense amplifier circuit diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

10, 10 ': Amplifier performance means 11: Data detection and differential amplifier

IN1, IN2: input Q1, Q2: output

P1 to P6: PMOS transistors M1 to M3: NMOS transistors

VDD: Power Supply Voltage

The present invention relates to a data sense amplifier that reads data from a memory cell, and more particularly, to a data sense amplifier circuit that increases driving force and increases amplification rate to reduce driving time.

In the conventional configuration of the data sense amplifier circuit, as shown in FIG. 1, a data sense amplifier using a data sense amplifier using a differential amplifier is mainly used, and the inputs IN1 and IN2 are enMOS transistors M1 and M2. The NMOS transistors M1 and M2 are grounded through the current source I ₀ , and the drains are connected to the output terminals Q2 and Q1, respectively, and are simultaneously connected to the PMOS transistors. The gates of the PMOS transistors P1 and P2 connected to the sources of P1 and P2 and the power supply voltage VDD applied to the drains are connected to the sources of the PMOS transistors P2. Data is input from the bit line amplifier to the data sense amplifier while IN2) is pre-charged to a constant voltage, and the data sense amplifier of FIG. 1 is re-amplified again to increase the driving force to output lines Q1 and Q2. to Produce. At this time, when the input (IN1) data is amplified, it is amplified by the differential amplifier and transferred to the output with large driving force.

However, the input (IN2) data is a current mirror type differential amplifier, which is connected to the gate and the drain of the PMOS transistor, so that the amplification rate is charged and the driving force is small. Cannot be delivered.

As described above, in the conventional data sense amplifier, since the driving force and the required time vary according to the selected input, the characteristics of the entire sense amplifier deteriorate.

Accordingly, the technical configuration of the data sense amplifier according to the present invention, which solves the above disadvantages, will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a data sense amplifier according to the present invention.

As shown in FIG. 2, the data sense amplifier circuit diagram according to the present invention includes two MOS transistors P5 and P6 having two inputs IN1 and IN2 applied to respective gates and a source grounded to function as an amplifier. And an amplifier capable means consisting of PMOS transistors P1 and P2, wherein each drain of PMOS transistors P5 and P6 is connected to a source and a gate and a voltage power supply VDD is applied to each drain to act as a bias. (10) (10 '), PMOS transistors P3 and P4 to which the source of PMOS transistors P1 and P2 are connected to the gates, and a power supply voltage VDD is applied to the drains, and two inputs respectively. The input includes a data sensing and differential amplification means (11) consisting of en-MOS transistors (M1, M2) connected to the sources of the PMOS transistors (P3, P4), so that the two inputs (IN1, IN2) These are each symmetric The same amplification factor is applied to the MOS transistors M1 and M2 of the data sensing and differential amplification means 11 and by the PMOS transistors P1P5 and P2P6 which are symmetrical amplifier power means 10 and 10 ', respectively. It is applied to the symmetric data sensing and differential amplification means (P3, P4), respectively, so that the data has a fast driving force by eliminating the difference in the amplification factor according to the selection of the input line.

That is, in the data sense amplifier circuit according to the present invention, two inputs IN1 and IN2 are amplified by the data sensing and differential amplification means 11, the EnMOS transistors M1 and M2 and the amplifier power means 10 and 10 '. PMOS transistors P5 and P6, which are input to the gates of the PMO transistors P5 and P6 that function, and which are source-grounded, have PMOS having a power supply voltage VDD applied to the drain to act as a bias. PMOS transistor P3 connected to the gates of the transistors P2 and P4 and the source of the PMOS transistors P1 and P2, which are data sensing and differential amplification means 11, and to which a power supply voltage VDD is applied to the drain. , The source of P4 is connected to the drains of the enMOS transistors M1 and M2, respectively, and to the output terminals Q2 and Q1, and the sources of the enmost transistors M1 and M2 are respectively connected to the drains of the enMOS transistors M3. Connected to the drain and applied to the gate of the voltage source (VDD) of the OSU is configured grounded.

In the operation of the data sense amplifier circuit according to the present invention, when data through the bit line sense amplifier is input to the data sense amplifier circuit through two inputs IN1 and IN2, the data sense and differential amplification are directly performed through the connection points a and b. It is input to the gates of the MOS transistors M1 and M2 of the means, amplified by the MOS transistors P5 and P6 of the amplifier power means 10 and 10 ', and is connected to the PMOS transistors through the connection points e and f. Since it is input to (P1, P2), the amplification ratio of the data sensing and differential amplification means 11 is increased, and the amplification ratio at the output terminals (c, d) is the same. It is possible.

At this time, since both ends of the data sensing and differential amplification means composed of the PMOS transistors P3 and P4 and the NMOS transistors M1 and M2 have a symmetrical structure, the characteristic values of both devices are the same, and thus the output stages c and d are identical. Amplification factor in

Therefore, the data sense amplifier circuit according to the present invention has a large driving force, and the two output stages have the same amplification ratio, so that there is no difference in driving time according to the input signal selection, thereby reducing the driving time.

Claims (1)

Two inputs IN1 and IN2 are applied to the respective gates, the source is grounded, and the PMOS transistors P5 and P6 functioning as amplifiers, and the drains of the PMOS transistors P5 and P6 are respectively source and source. A power supply voltage VDD is applied to each of the gates, and an amplifier power means 10 and 10 'is formed of PMOS transistors P1 and P2 which act as a bias and the PMOS transistors P1, PMOS transistors P3 and P4 having a source of P2 connected to the gate and a power supply voltage VDD applied to the drain, two inputs being input to the respective gates, and drains of the PMOS transistors P3 and P4. It comprises a data sensing and differential amplification means (11) consisting of en-MOS transistors (M1, M2) connected to the source of, so that the two inputs are applied to the data sensing and differential amplification means (M1, M2) symmetrical to each other, respectively. Each standing at the same time The symmetrical amplification means P1, P5 (P2, P6) are increased to the same amplification factor and are applied to the symmetrical data sensing and differential amplification means P3, P4, respectively, so that the data is amplified according to the selection of the input line. A data sense amplifier circuit characterized by removing a car to have a fast driving force.