KR940008139B1 - Amplifing circuit in semiconductor memory device - Google Patents

Abstract

The data sense amplifying circuit includes a signal amplifying circuit, a first MOS capacitor with the gate connected to a first bit line and the source and drain commonly connected to the signal amplifying circuit, and a second MOS capacitor with the gate connected to a second bit line and the source and drain commonly connected to the signal amplifying circuit, thereby rapidly sensing data.

Description

Data sense amplification circuit of semiconductor memory device

1 is a conventional circuit diagram.

2 is a circuit diagram of the present invention.

3 is an operational waveform diagram of FIG.

4 is a waveform diagram of a MOS capacitor.

* Explanation of symbols for main parts of the drawings

10: light circuit 20: memory 쎌

30: signal amplifier 40: detection amplifier

50: transmission circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data sensing circuit of a semiconductor memory device, and more particularly to a circuit capable of quickly sensing data by amplifying a weak information signal at a data sharing point between a memory chip and a bit line.

Dynamic random access memory (hereinafter referred to as " DRAM "), which is a semiconductor memory device, charges or discharges data accumulated in a memory X selected by a row decoder from a bit line connected to the drain of a X transistor. The information presented in the form of voltage difference in the phase is sensed and amplified by sense amplifiers connected in parallel to the bit lines and read out. In addition, the read data is charged or discharged again to have a dynamic memory function. However, as the overall density of the memory device is increased and the high speed operation is performed, the capacitance of the memory cell is reduced, which is a result of the load being increased by the capacitance of the bit line. Therefore, of course, the fast detection of the data must be close to the capacitance of the bit line of the memory chip.

FIG. 1 is a conventional general circuit diagram for sensing data stored in a memory cell, and the conventional data sensing operation will be described based on the configuration of FIG. An equalization voltage for half vcc generator precharge is applied to jar 9, where Assume that First, the first and second bit lines BL, before reading data from the memory array including the enMOS transistor 22 and the capacitor 23 in the memory array array 20, are read. In order to precharge the terminal 11, the terminal 11 applies a high level equalization signal? EQ. Therefore, the enMOS transistors 12 to 14 are turned on so that the first and second bit lines 31 and 32 Precharge and equalize at the level. After that, when the word line 21 is selected by the row decoder, the NMOS transistor 22 is turned on, so that the storage data level of the capacitor 23 appears as the drain of the NMOS transistor 22. Therefore, a charge sharing operation occurs between the capacitor 23 and the first bit line BL.

Then, the data level of the first bit line BL is sensed and amplified by the PMOS transistors 42 and 43 and the enMOS transistors 45 and 46 which are cross-connected to the first and second bit lines 31 and 32. By doing so, the logic of the data is determined. When the data logic is determined by the sense amplifier 40, a high level separation signal is applied to the line 51 to conduct the enMOS transistors 52 and 53, which are transfer gates, thereby providing the first and second bits. Line (BL, Logic state of the first and second input and output lines (IO, Is sent). Therefore, the first and second bit lines BL, )of After pre-charging to low, when an address is given from the outside, a specific word line is selected to transfer the information of the corresponding memory 으로 to the bit line. However, since the capacitance of the bit line is larger than that of the memory 쎌, the information transmitted is very weak. To improve this, it is necessary to increase the capacitor capacity of the memory chip or reduce the capacitance capacity of the bit line, which causes the disadvantage of increasing the area of the memory chip.

Accordingly, an object of the present invention is to provide a circuit capable of quickly stabilizing information in a memory chip by first amplifying a weak information signal generated at the point of data sharing between the memory chip and a bit line in a semiconductor memory device before detection and amplification. .

In order to achieve the object of the present invention, the present invention, the word line, the first and second bit line, an equalization circuit for precharging the first and second bit line to an intermediate voltage level when the equalization signal is generated; 10. A semiconductor memory device comprising: a memory 연결 connected to the word line and a bit line and storing predetermined data; and a sense amplifier configured to sense and amplify information of the first and second bit lines. A signal amplification means enabled after a predetermined time after enabling, a first MOS capacitor having a gate connected to the first bit line, and a source and a drain commonly connected to the signal amplification means, and a gate connected to the second bit line. And a second MOS capacitor connected to the signal amplification means in common with a source and a drain, wherein the first and second MOS capacitors are voltages of a gate node. Capacitance capacitance is changed by a bias to amplify the voltage difference between the first and second bit lines before the sense amplifier, so that the sense amplifier is a data sensing amplifier circuit of the semiconductor memory device which operates to perform a fast and stable sensing function It is done.

Hereinafter, the present invention will be described in detail with reference to the drawings.

2 is a view showing an embodiment of a data sensing amplifier circuit of a semiconductor memory device according to the present invention. The structure is composed of enMOS transistors 12 to 14, and a gate is commonly connected to the equalization line 11 so that the first and second bit lines BL, )of The first circuit stores information stored in the capacitor 23 when the word line 21 is enabled by the equalization circuit 10, the enMOS transistor 22, and the capacitor 23, which are precharged to a low level. A memory 2020 that is output to the bit line BL, and the first and second bit lines BL, Are respectively connected to the signal amplification means 31, and the drain and the source are connected to the signal amplification means 31 so that the signal amplification means 31 is enabled. First and second bit lines BL, A signal amplifier 30 for first amplifying the weak information signal of the first and second bit lines BL, The first and second bit lines BL, which are primarily amplified by two PMOS transistors 42 and 43 and an enMOS transistor 45 and 46 having their gates cross-connected to A sensing amplifier 40 for detecting and amplifying an information signal of the signal and determining a logic level of the information, and the first and second bit lines BL, ) And first and second input output lines IO, Is composed of two transfer enMOS transistors 52 and 53 respectively connected between the first and second bit lines BL, Information signals of the first and second input / output lines IO, It is composed of a transmission circuit 50 for transmitting to.

3 is an operation waveform diagram of the signal amplifier 30 according to the present invention, and FIG. 3A is an operation waveform diagram when the information of the memory V is data "1" and FIG. 3B is the data waveform "0" when the information of the memory V is temporary. The operation waveform of. 4 is a characteristic diagram of capacitance versus voltage of an NMOS transistor.

Based on the above configuration, the operating characteristics of the present invention will be described in detail.

Referring to the equalization process, when the equalization signal ψEQ is applied to the equalization line 11 in the read or write mode of the memory device, the NMOS transistors 12 to 13 are turned on, so that the first and second bit lines BL, ) Is output from the half vcc generator Equalize and precharge to voltage levels. Then, when an address is supplied from the outside, the word line 21 corresponding to the address is selected. When the word line 21 is enabled, the NMOS transistor 22 of the memory element 20 is turned on so that the first bit line BL is turned on. The charge sharing operation is generated based on the voltage and the information of the capacitor 23. At this time, when the word line 21 is enabled and a charge sharing operation occurs, the voltage of the first bit line BL is changed according to the information of the capacitor 23. It becomes larger by ΔV or smaller by ΔV than the voltage. At this time, when the signal amplification means 31 is enabled, the first and second MOS capacitors 32 are turned on, so that the first bit line BL and the second bit line B are respectively applied. First amplify the signal. Here, when a voltage is applied to one end of the electrode (here, the channel side of the MOS capacitor 32 or 33 of FIG. 2) by the coupling effect of the common capacitor, the other end of the electrode (here, the MOS capacitor of FIG. 2) It is well known that the gate side of 32 or 33) also rises or falls in response to the applied voltage level. In this case, the first and second MOS capacitors 32 and 33 have a characteristic curve as shown in FIG. In other words, the enhancement type enmos transistor has a high capacitance within a predetermined voltage range (Vmin-Vmax), and a low capacitance results in a low capacitance.

Therefore, the first and second bit lines BL, Since the biasing of () is different, the amplitudes amplified by the first and second MOS capacitors 32 and 33 also have different values. On the other hand, the technology of changing the capacitance of the capacitor according to the bias voltage is described in detail by PAUL RICHMAN between pages 53 to 67 of the aforementioned "MOS Field-Effect Transistors and Integrated Circuits".

First, the operation process of the information stored in the capacitor 23 of the memory module 20 when the data is "1" will be described. First, if the equalization line 11 is enabled, the first and second bit lines BL, )silver The voltage is equally precharged. Then, when the word line is enabled as shown in (A1) of 3A, since the NMOS transistor 22 is turned on, the charge charged in the capacitor 23 is transferred to the first bit line through the NMOS transistor 22. To BL). Therefore, the second bit line ( ) Is the same as (A4) in FIG. 3A. The pre-charged state is maintained by the voltage, but the first bit line BL is controlled by the information of the memory V as shown in FIG. 3A (A3). Rise to +1 voltage level. In this case, the one voltage becomes a small voltage by data " 1 " Therefore, the first and second bit lines BL, ) Will have a very small voltage difference of V1. After the word line 21 is enabled as shown in (A1) of FIG. 3A, and the signal amplification means 31 is enabled as shown in (A2), the first and second MOS capacitors 32 and 33 are respectively First and second bit lines BL, ) Will first amplify the signal. In this case, the first and second MOS capacitors 32 and 33 have the same characteristics as those of FIG. 4. here At the voltage level, the MOS capacitors 32 and 33 are set to have an intermediate value between Cox and Cmin. Accordingly, when the signal amplification means 31 is enabled, the first MOS capacitor 32 having a gate connected to the first bit line BL is connected to the second bit line (B). ) Has a greater degree of amplification than the second MOS capacitor 33 having a gate connected thereto. This is because the capacitance of the capacitance varies according to the voltage value biased to the gate node of the MOS capacitor as described above. When the signal amplification means is enabled, the first and second bit lines BL having a difference of one voltage are provided. )

As described above, the first and second bit lines BL, When the voltage difference increases between two levels, the sense amplifier 40 quickly senses the logic of the data and amplifies the data. That is, if Vcc level power is supplied to the line 41 and VSS level power is supplied to the line 42, the PMOS transistor 43 is not conducted by the signal voltage level of the first bit line BL. The transistor 42 is turned on so that the first bit line BL rises to the Vcc voltage level. In addition, when the first bit line BL rises to the Vcc voltage level, the NMOS transistor 46 is turned on so that the second bit line BL may be turned on. Signal drops quickly to the VSS voltage level. Therefore, the first and second bit lines BL, by the signal amplifier 30, By increasing the voltage difference between the first bit line () ) Rises to the Vcc voltage level and the second bit line ( The time that the) falls to the VSS voltage level is faster, which allows for a faster transition time and a stable sensing operation. Secondly, the operation of when the information stored in the capacitor 23 of the memory module 20 is data "0" will be described. First, through the equalization process, the first and second bit lines BL, )of If the word line 21 is enabled as shown in (B1) of FIG. 3 after precharging to a voltage, the NMOS transistor 22 is turned on to conduct the first bit line BL. By the voltage, the capacitor 23 performs the charging operation.

Therefore, as shown in (B4) of FIG. 3, the second bit line ( ) Maintains the Vcc / 2 voltage, but the first bit line BL is the same as (B3) in the third mode. -1 drops to voltage level. Subsequently, when the signal amplifying means 31 is enabled as shown in (B2) of FIG. Are biased to have one voltage difference, and according to the characteristics of FIG. 4, the first MOS capacitor 32 amplifies the signal of the first bit line BL as shown in (B3) of FIG. The capacitor 33 has a second bit line (B4) as shown in FIG. Amplify the signal. Therefore, the first and second bit lines BL, ), There is a difference of two voltages, and in this case, the second bit line ( It can be seen that the voltage of) becomes larger.

As described above, the signal amplifier 31 has the first and second bit lines BL, By amplifying the voltage difference between the two circuits larger, the sensing amplifier 40 performs a fast and stable sensing operation as described above. That is, since the PMOS transistor 43 is conductive, the second bit line ( ) Is rapidly raised to the Vcc voltage level, and the enMOS transistor 45 conducts, so that the first bit line BL is rapidly lowered to the VSS voltage level. According to the experiment, when the size of the MOS capacitors 32 and 33 is 5 mm 2, the amplification degree is about 30 mV. In addition, when the channel injection concentration of the MOS transistor and the injection concentration of the MOS capacitor are different, the amplification rate of the MOS capacitor can be increased. In addition, it is effective to set the capacitance of the first MOS transistor 32 and the capacitance of the second MOS capacitor 33 to be the same. Therefore, after the word line is enabled, it is generated by charge sharing between the information in memory 와 and the bit line, so that the voltage difference is first amplified before driving the sense amplifier to make the voltage difference larger, so that the sense amplifier can detect the signal quickly and stably. You will be able to perform the function.

Claims (2)

A word line, first and second bit lines, an equalization circuit for precharging the first and second bit lines to an intermediate voltage level when an equalization signal is generated, and connected to the ad and first bit lines A semiconductor memory device having a memory 하는 for storing data and a sense amplifier for sensing and amplifying information of the first and second bit lines, comprising: signal amplification means enabled after a predetermined time after the word line is enabled; A first MOS capacitor having a gate connected to the first bit line and having a source and a drain connected to the signal amplification means, a gate connected to the second bit line and a source and a drain connected to the signal amplification means in common. And a first capacitance of the first and second capacitors, the capacitance of which is changed by a voltage bias of the gate node, The first voltage difference of the second bit line than the first amplified sense amplifier so that the sense amplifiers sense data quickly and the semiconductor memory device characterized in that it operates to perform stable detection amplifier circuit. The data sensing amplifier circuit of claim 1, wherein the capacitance of the first MOS capacitor is equal to the capacitance of the second MOS capacitor.