KR930003904Y1 - Stabilized clock recycling circuit - Google Patents

Abstract

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Description

Instantaneous stable clock regeneration circuit

1 is a conventional clock regeneration circuit diagram.

2 is a clock reproduction circuit diagram according to the present invention.

3 is an operation waveform diagram of a conventional clock regeneration circuit.

4 is an operation waveform diagram of a clock regeneration circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

2.5.101.103. Capacitor 3.102. : crystal

7: inverter

The present invention relates to a clock regeneration circuit configured to enable stabilization because of a short time required for stabilization when the clock is regenerated temporarily.

In the related art, as shown in FIG. 1, the nodes 1 and 4 at both ends of the crystal 3 are connected to the input and the output of the inverter 7 and are respectively connected to both of the feedback resistors composed of the NMOS transistors 6. have.

Capacitors 2 and 5 are connected between the ground nodes (1) and (4), respectively. The input gate 8 of the NMOS transistor 6, which is a feedback resistor, is connected to Vcc.

The conventional structure having the above-described configuration is a typical crystal oscillator circuit, which has a potential of the output 4 of the inverter 7 when the power is turned off, and this potential is charged in the capacitor 5. In addition, due to this charged charge, the crystal 3 enters an oscillation state, and the voltage excited by the oscillation is charged again in the capacitor 2. This charged voltage causes the input 1 of the inverter 7 to have a potential and this input voltage causes the inverter 7 to enter an operating state, so that the voltage at the output stage 4 has a potential at the input terminal 1. This input voltage causes the inverter 7 to enter an operating state, so that the voltage at the output stage 4 is changed by the voltage at the input stage 1. Repeating this process, the voltages of the input (1) and the output (4) gradually approaches the Vcc voltage and complete oscillation after a certain time.

The conventional structure takes a lot of time to stabilize when disabling and re-enabling Croolol, which results in a decrease in overall system performance in a system in which Croke is frequently disabled and enabled. It became.

The present invention is devised to solve this problem, which will be described in detail. The PMOS transistors 105 and 106 are connected in parallel between the Vcc and the node 10 and the NMOS transistors 107 and 109 are grounded in series. The inputs of the PMOS transistor 105 and the NMOS transistor 107 to node 104, the inputs of the PMOS transistor 106 and the NMOS transistor 109 to node 113, and the gate input to Vcc. And an NMOS transistor 111 coupled to both nodes 104 and 110 thereof, the gate input of which is connected to node 131 to node 104 and node 110 in parallel with NMOS transistor 111. And an odd number of inverter strings including a PMOS transistor 112 connected to each other, and generating a pulse having a time width corresponding to a propagation delay time, connected between the node 113 and the node 128, and the node 128. PMOS transistors (132) and (134) as inputs And the output thereof is connected to the input of the PMOS transistor 112, which will be described in more detail. As shown in FIG. 2, the node 104, which is connected and the connection point thereof, is parallel to the PMOS transistor 105. The NMOS transistor 107 and the NMOS transistor 109 are connected in series, and the source of the NMOS transistor 109 is connected to the ground.

The PMOS transistor 106 and the NMOS transistor 109 receive input from the node 113.

The output 110 of this structure is connected to the other side of the crystal 102.

This output 110 is also connected to two feedback resistors in which node 104 is connected in parallel, one of which is a high resistance resistor composed of NMOS transistors 111 and its input is connected to Vcc.

The other is connected to node 131, which is a low resistance resistor consisting of PMOS transistor 112.

The node 131 is an output of a circuit including a PMOS transistor 129 and a PMOS transistor 130 connected in parallel with Vcc, and an NMOS transistor 132 and an NMOS transistor 134 connected in series with ground. In this circuit, the inputs of the PMOS transistor 130 and the NMOS transistor 134 are connected to the node 113, and the PMOS transistor 129, the NMOS transistor 132 is composed of the PMOS transistor 126 and the NMOS transistor 127. It is connected to the output 128 of the inverter.

In the same manner, five inverters are connected in series between the node 113 and the node 128.

Referring to the operation of the instantaneous stable clock regeneration circuit according to the present invention, as shown in FIG. 4, even when Vcc is applied, the node 113 is in the "low" state, and the NMOS transistor 109 is in the "off" state and the PMOS is performed. Transistor 106 is frozen and node 110 goes high with Vcc.

In this state, however, the oscillation circuit cannot oscillate and is therefore in a disabled state. At this time, when the input of the node 113 is raised to the high state, the PMOS transistor 106 is in an affair state and the NMOS transistor 109 is in an unset state so that the PMOS transistor 105 and the NMOS transistor 107 can operate. do.

In this case, oscillation starts in the same manner as described in the above-described operation of the conventional circuit. When the node 113 becomes high, the charge of the node 131 is discharged in combination with the high level voltage charged in the node 128. Will fall into a state.

However, as soon as the node 128 falls to the low level through the inverter spring, the NMOS transistor 132 is in an affirmative state, and the PMOS transistor 129 is in a frozen state, and the node 131 is reduced to a high state.

As a result, a pulse of a time delayed by the number of inverter springs is generated at the node 131. The momentary pulse is applied to the PMOS transistor 112 to instantaneously have a potential level between the node 104 and the node 110. This maximizes the gain of the oscillator circuit and enables stable oscillation in a short time.

Therefore, according to the present invention, the oscillation circuit can be oscillated only for a desired time by enabling and disabling the oscillation circuit at an arbitrary time, and the oscillating circuit system makes the oscillation stable in the fastest time when it is enabled in the disabled state. There are many advantages such as preventing the loss of performance.

Claims (1)

PMOS transistors 105 and 106 are connected in parallel between Vcc and node 110 and NMOS transistors 107 and 109 are connected in series between ground and the inputs of PMOS transistor 105 and NMOS transistor 107 are An NMOS transistor applied to node 104 and having inputs of PMOS transistor 106 and NMOS transistor 109 connected to node 113, gate input connected to Vcc and connected to both nodes 104 and 110 thereof. 111, and a gate input is applied to node 131 to include a PMOS transistor 112 connected to node 104 and node 110 in parallel with NMOS transistor 111, by a propagation delay time. An odd number of inverter strings generating pulses having a time width are connected between the node 113 and the node 128 and receive inputs from the nodes 128 and 113 and the NMOS PMOS transistors 129 and 130. PMOS transistors connected between transistors 132 and 134 and receiving inputs from nodes 128 and 113. 129, 130 and NMOS transistors 132, 134 to its output time stable clock recovery circuit, characterized in that configured is connected to the input of the PMOS transistor 112 comprises a.