KR910002621B1 - Interface in collect callexchange - Google Patents

Abstract

Circuit adopts RS-232C interface which makes easy connection between the two systems, and improves a distance problem and transmission speed. Interfaceing circuit is installed inside the magnetic tape (M/T) system, and RS-232C is used to interconnect the two systems. The circuti includes telephone system (10), RS-232C line (11), serial IN/OUT circuit (20), fourth parallel IN/OUT (30), printer (40), sync/Async transceiver (50), operator terminal (60), ROM (70) for M/T control system program and reference data, RAM (80) for temporal data storage, CPU (100), reset circuit (90) for CPU, RsDnAc (200,201), first second parallel IN/OUT circuit (300)(400), third parallel IN/OUT circuit (600), timer-counter (500) and MIT interface (700) which has interconnection with two cables of 50 limes each.

Description

Interface circuit for data leads / lights from collective telephone exchanges to magnetic tape

1 is a circuit diagram according to the present invention.

2 is a read timing diagram according to the present invention.

3 is a write timing diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

10: group telephone switching system 20: serial input / output circuit

300, 400, 600, 30: 1-4 parallel input / output circuit 40: printer

50: general purpose synchronous and asynchronous transceiver 60: terminal

70: Roman 80: Ram

100: central processing unit 90: reset circuit

500: Counter Timer

200, 201: transmission / reception direct memory access control circuit

700: M / T interface circuit

The present invention relates to an interface circuit for read / write of magnetic tape in a collective telephone exchange, and in particular, RS-232C between the collective telephone exchange and the magnetic tape (hereinafter referred to as "M / T") system. Data read / write to magnetic tape in a collective telephone exchange that can be interfaced in a way to simplify the connection of the M / T system and to easily read data to the M / T without being restricted by the distance of the M / T system. It relates to an interface circuit. M / T systems have been used to store backup data of auxiliary storage devices (HDD, FDD) in microcomputers or exchange systems. Data storage capacity is 20Mbyte or more, and it is a device that can be stored in advance for use in case of breakage of data worked in auxiliary memory device due to instantaneous power failure or peripheral cause in microcomputer or exchange system.

When a conventional M / T system is connected to an exchange system to store backup data, the M / T system interface circuit is mounted in the exchange system so that the control for reading and writing when connecting the M / T system from the exchange system is practical. Only two cables with 50 lines to transmit signals and data could be used to interface M / T systems.

As described above, the interface is complicated by two cables, which complicates the control due to the complicated structure, and as the distance between the M / T systems increases, the transmission distance and speed are limited, and the line length of the cable is increased. There was a point.

Therefore, the present invention is to implement the interface circuit to the M / T system, and then to interface the M / T system from the group telephone exchange in the RS-232C method to quickly and easily data to the M / T without being limited to the connection distance It is to provide a circuit that can be read / written.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram according to the present invention, in which a serial group switching system 10 is interfaced with a group telephone switching system 10 via a line 11 in an RS-232C manner to serially communicate parallel data in series. Receives data on the same address bus AD and data bus DA, the control signal and the interrupt signal terminal INT applied to the input / output circuit 20 and the serial input / output circuit 20, and transmits the data in parallel. A control bus for outputting the fourth parallel input / output circuit 30 to output, the printer 40 for printing the output data of the fourth parallel input / output circuit 30, and the data of the address bus AD and the data bus DA. By the signal of (CD), it is interfaced with the general purpose synchronous and asynchronous transport transceiver 50 which transmits both synchronously and asynchronously, and the said general synchronous and asynchronous transceiver 50 and the line 51 of RS-232C system. Input / output of user's data ROM 60 containing a terminal 60, a system program for controlling M / T and reference data, and a RAM 80 for temporarily storing data to be stored in the control program of the ROM 70 and M / T. And control the data on the RAM 80 to be processed by the printer 40 and the terminal 60 by the program of the ROM 70 according to an input command through the terminal 60 and record and reproduce by M / T. A central processing unit (100) for controlling the control unit, a reset circuit (90) for generating a reset signal of the central processing unit (100), and a bus request and recognition signal terminal of the central processing unit (100) (101, 102). Transmission and reception direct memory access circuits 200, 201 and M / T signals of the M / T system, which receive the control right by the control signal and control to directly access the data on the RAM 80 according to the read and write to the M / T. By generating the interrupt signal of the long-term central processing unit 8100 And a first parallel input / output circuit 300 for generating a control signal of the M / T system according to the hand setting of the data on the data buses AD and DA and a status signal of the M / T system. A second parallel input / output circuit 400 for generating an intercept signal of the central processing unit 100 and outputting the address and data bus (AD, DA) data in parallel according to a control signal, and the address and data bus. Transmit and receive ready signals (RX RDY, TX RDY) of the transmit / receive direct memory access circuit 200 by controlling the data on the (AD, DA) data and access the data accessed from the RAM 80 in parallel and hand setting. The third parallel input / output circuit 600 that reads / writes the M / T system and generates an interrupt signal of the CPU 100, and counts predetermined values by setting the address and data buses AD and DA. M / T data When connected to a timer town 500 that generates a signal indicating that the last data, and two cables having 50 lines with the M / T system to facilitate the transmission of data according to the lead / write and control signal transmission It is composed of the M / T interface circuit 700.

2 is a read timing diagram according to the present invention, where (2a) is an M / T system operation enable signal type, (2b) is a read strobe transmit / receive signal type, (2c) is read data, and (2d) Is a reception wait signal, and 2e is a data read waveform diagram of the third parallel input / output circuit 600.

3 is a write timing diagram according to the present invention, where 3a is an M / T system operation enable signal type, 3b is a light strobe transmission / transmission signal waveform, 3c is a transmission dash signal, (3d) is a data line waveform diagram of the third parallel input / output circuit 600, and (3e) is a signal generated from the counter / timer 500 and is a signal generated when the last data is loaded on the data line.

Therefore, a specific example of the present invention will be described in detail with reference to FIGS. 1 to 3, and in order to carry out the present invention, the central processing unit 100 in which the controller is used is used as a memory unit using at least Z-80A. It is possible to configure 70 at 32K bytes and RAM 80 at 32K bytes, for a total of 64K bytes.

First, upon application of power to the system, the system program and reference data of the ROM 70 are loaded into the RAM 80 and placed in a standby state where the central processing unit 100 can process according to the input command. At this time, when the user inputs a predetermined command to read data from the M / T of the M / T system, the CPU 100 checks this and processes it by the control program of the RAM 80 to process the M / T according to the corresponding read command. Each part control signal is generated to read data from T. In this case, when the address 80 is designated as the write mode of the RAM 80 and the address and data generated from the CPU 100 are input to the first parallel I / O circuit 300, the transfer address to M / T is selected by the signal (2a). And generates various commands and control signals and is applied to the M / T system through the M / T interface circuit 700. The first parallel input / output circuit 300 has ports A and B. It can be used as interrupt source by DBY, FBY signal input from M / T system using strobe stage.

Modes and signals generated in the first parallel input / output circuit 300 are shown in Table 1 below.

TABLE 1

In addition, when the predetermined signal of the address bus AD of the central processing unit 100 controls the receiving side direct memory access control circuit 200, the receiving side direct memory access control circuit 200 is transferred to the central processing unit 100. Request bus control. When the central processing unit 100, which has received the bus control right, transmits a recognition signal according to the bus request to the receiving side direct memory access control circuit 200, all bus control rights are received from the receiving side direct memory access control circuit (RxDMAC) 200. ) Is controlled and operated in the input / output (I / O) -to-memory mode, wherein the Rx DMAC 200 is initialized to transfer necessary input / output (I / O) data from the CPU 100 to the memory. When the Rx DMAC 200 is enabled, the Rx DMAC 200 supplies the address signals of the RAM 80 and the third parallel input / output circuit 600 and supplies the address signals to the A and B ports of the second parallel input / output 400. According to the first signal received through the one parallel input / output circuit 300, the signal data is read in the operation state of the M / T system. In this case, the second parallel input / output circuit 400 can read the system status from the A and B port output terminals A0-A7 and B0-B7 as shown in Table 2 below, and the signal marked with “*” is an interrupt source signal. It is used to apply to the central processing unit 100 and each part.

TABLE 2

In the M / T system, as shown in Table 1, the FEL signal is "low" and the TEST signal is "low". The logic of the P melter in the M / T system is disabled.

The test signal goes “low” during the board test, turning off the FEN to disable the pomelter and activating the buffers needed for the test FAD, TAD0, and TAD1 are latched on the pomelter by the GO pulses and FAD and TAD The selection of the pomelter and the transmission port is as follows: Since four transmission ports can be controlled per 1 pomelter, eight transports can be controlled by controlling two pomelters with one M / T. The method for address selection of the pomelter is shown in Table 3 below.

TABLE 3

As shown in Table 1, the command signal (reverse, write, write, erase, write file mark) received by the pomelter is decoded by the Go pulse so that the operation is performed as shown in Table 4 below. Here, RWD and OFL commands are sent directly to the transmission port without going through the pomelter in pulse form so that the tape rewind and offline mode can be set respectively.

TABLE 4

The operation of Table 4 relates to a conventional basic operation of the M / T system, and a detailed description thereof will be omitted.

Accordingly, the read strobe signal is input from the M / T system through the M / T interface circuit 700 to the third parallel input / output circuit 600 through the line 701 as shown in (2b) and through the data line 703. When the read data is output through the M / T interface circuit 700 as shown in (2c), the third parallel input / output circuit 600 receives the received ready signal to the receiving direct memory accept control circuit 200 as shown in (2d). (Rx RDY) is applied, and at the same time (2e), the (2c) data is read and read from the M / T to the RAM 80 in accordance with the address signal generated by the receiving direct memory accept control circuit 200. The data is output to the collective telephone exchange system 10 and the printer 40 or the terminal 60 by the control of the central processing unit 100 until the data is sequentially stored and filled.

On the other hand, when writing data to the M / T system, the user command data given from the terminal 60 is input to the central processing unit 100 through the legal synchronous and asynchronous transceiver 50, the central processing unit 100 is a RAM ( The RAM 80 is set to the write mode by controlling the input command according to the program stored in 80) and the serial I / O circuit 20 is controlled to receive data from the collective telephone switching system 10 to the designated RAM 80. At the same time, the storage may be printed to the printer 40 or displayed on the terminal 60 through the fourth parallel I / O circuit 30. At this time, the central processing unit 100 requests the central processing unit 100 to transfer the bus control right by controlling the direct-side memory accepting zero circuit (hereinafter referred to as "Tx DNAC") 201 by the address signal of the central processing unit 100. If the central processing unit 100 receives the TxDMAC 201, the bus control right is performed by the Tx DMA 201. In addition, when the data control signal on the address and data buses AD and DA according to the data recording of the M / T system output from the central processing unit 100 is inputted to the first parallel input / output circuit 300, it becomes like (3a). As shown in Table 1, the Go signal outputs the control signal according to the light to the A and B ports of the first parallel input / output circuit 300, and the second input / output circuit 400 of the first parallel input / output circuit 300 The status signal of the converted M / T system is read by the signal, and each interrupt source signal is generated as shown in Table 2 above.

The Tx DMAC 201 is operated in a Memo-To-I / O mode and is controlled by the Tx DMAC 201 according to a value in which the CPU 100 sets the Tx DMAC 201 to a predetermined initialization state. When the predetermined number of data is received from the RAM 80, the data is transmitted to the third parallel input / output circuit 600, and the third parallel input / output circuit 600 receives the light strobe signal generated by the M / T system as shown in (3h). Transmit ready signal to TxDMAC 201 as shown in (3c) so that TxDMAC 201 transmits data one by one to M / T system via M / T interface circuit 700 at the same write timing as (3d). do. When the desired number of data transfers occur during the transfer, the countertimer 500 transmits the last word data to the M / T system as shown in (3e) to indicate that the data transfer is completed.

In order to store a lot of information using the low-cost M / T as described above, it is possible to connect M / T without limiting the connection distance from the exchange by using the RS-232C interferless method and transmit data because it is a RS-232C transmission method. There is a good efficiency.

Claims (1)

In the interface circuit of the collective telephone exchange system and the M / T system, the serial telephone exchange system (10) and the serial input and output circuit (20) for interlacing the parallel data serially interlaced with the line 11 of the RSA-232C system; And a fourth parallel input / output in which data on the same address bus AD and data bus DA and signals of a control signal and an interrupt signal terminal INT applied to the serial input / output circuit 20 are output in parallel. The printer 40 which prints the output data of the circuit 30 and the general-purpose which transfers the data of the said address bus AD and the data bus DA synchronously and asynchronously by the signal of the control bus CD. A system for controlling the M / T and the terminal 60 for interfacing with the synchronous and asynchronous transceiver 50, the general-purpose pottery and asynchronous transceiver 50, and a line 15 of the RS-232C system. Program and A ROM 70 incorporating air data, a RAM 80 temporarily storing the control program of the furnace 70 and data to be stored in the M / T, and the ROM in response to an input command through the terminal 60. A central processing unit (100) for controlling data on the RAM (80) to be processed by the printer (40) and the terminal (60) by a program of (70), and controlling to be recorded and reproduced by M / T; The reset circuit 90 generating the reset signal of the apparatus 100 and the control signal of the bus request and recognition signal stages 101 and 102 of the central processing unit 100 are directly controlled on the RAM 80. Transmit and receive direct memory access circuits 200 and 201 for controlling data to be accessed according to reads and writes to M / T, and M / T signals of M / T systems to generate interrupt signals of the central processing unit 100, and Data on dress and data bus (AD, DA) by control signal The parallel signal of the central processing unit 100 is generated by the first parallel input / output circuit 300 generated as a control signal of the M / T system and the status signal of the M / T system according to the handshaking in parallel. The second parallel I / O circuit 400 outputs the data on the address and data buses AD and DA in parallel in accordance with a control signal, and the transmission and reception by the data and control signals on the address and data buses AD and DA. A third generation signal for transmitting and receiving signals (Rx RDY, Tx RDY) of the direct memory access circuit 200 and reading / writing the data accessed from the RAM 80 to the M / T system according to handshaking in parallel; The parallel input / output circuit 600 generates an interrupt signal of the central processing unit 100 and is predetermined counted by setting the address and the datums AD and DA to indicate that the data is the last data when the M / T data is written. God M / T interface circuit 700 is connected to two cables having a timer counter 500 and 50 lines with the M / T system to facilitate the transmission of data and control signals according to read / write. Interface circuit for data read / write from a collective telephone exchange to a magnetic tape.

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