KR910002357B1 - Channel alloting circuit in digital exchange - Google Patents

Abstract

The circuit processes the channel assigning data of a digital exchange in parallel so that the channels are assigned rapidly and the state of channel assigning data is displayed. The circuit includes a channel data latch and control unit (23) for latching the data in put through a data bus by a first control signal input through a control input terminal and for transmitting the data through the data bus by a second control signal, an I/O control signal generator (22) for generating and transmitting the first and the second control signal to the channel data latch and control unit (23), a counter unit (26) for counting a first clock signal so that 32 channel data can be transmitted during one frame, and a comparator (24) for transmitting the channel assigned when the channel assigning data and the counted channel data are same.

Description

Channel Assignment Circuit of Digital Exchange

1 is a conventional channel allocation circuit diagram.

2 is a channel allocation circuit diagram according to the present invention.

3 is a detailed circuit diagram of one embodiment of FIG.

4 is a channel assignment operation waveform diagram of FIG.

* Explanation of symbols for main parts of the drawings

21: CPU 22: I / O control signal generator

23 channel allocation data latch and control unit 24 comparator

25: output control unit 26: counter unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel assignment circuit of a digital switchboard subscriber circuit, and more particularly, to a channel assignment circuit for allocating channel timeslots in parallel to process channel assignment in parallel.

In general, a time slot of a predetermined number of channels is set in one frame of a digital switchgear using a TDM (Time Division Mutiplexing) scheme. The time slot is used to communicate data (voice data or non-voice data). It is. In the 32-channel TDM digital exchange, 32 time slot channels are set in one frame (125 sec), and data of each channel is composed of 8 bits. The 32-channel transmission rate is 2.048 Mbps, and the transmission clock uses 2.048 MHz.

Therefore, 32 channel digital switchboard is configured with 32 channels in one frame, so it is possible to multiplex 32 subscribers' voice or non-voice data into one frame. Will be allocated and sent.

In order to transmit and receive subscriber data in its own channel in the TDM digital exchange, there must be a time slot assignment circuit, and the channel assignment circuit is embedded in the subscriber circuit and the subscriber and the subscriber It assigns its own channel among 1 frame (32 channels) to make a call.

The conventional channel allocation circuit for realizing this is a CPU (Central Processing Unit) 10 which outputs channel allocation data and control signals as shown in FIG. 1, and parallel channel allocation output from the CPU 10. The data is inputted to the signal and converted into serial data, and the parallel / serial conversion and control clock generator 11 for generating the first clock signal and the parallel / serial conversion and control clock generator 11 output the data. The parallel conversion processing unit 12 converts (restores) the channel allocation data serially converted by the first clock signal into parallel data, and outputs the second clock, and the parallel conversion processing unit 12 outputs the second clock. A latch unit 13 which maintains and outputs parallel channel allocation data for a predetermined period by the second clock, and a system clock signal and a third clock signal synchronized with the system synchronization signal are inputted so that data of 1 to 32 channels are received. When the two channel data values are the same by comparing the sequentially generated counter 15, the channel assignment data output from the latch unit 13, and the channel data output from the counter 15, the corresponding channel assignment signal Comparator 14 which outputs (CHA).

The parallel conversion processing section 12, latch section 13, counter 15, and comparator 14 in the dashed line in the configuration of FIG. 2 are serial data channel assignment circuits for channel assignment by serial channel assignment data and input. It is made of one chip. For example, such a circuit is incorporated in a time slot assignment circuit (TP3155), a product of National Semiconductor Corporation, a semiconductor manufacturer based in the United States.

The operation of the conventional channel assignment circuit constructed as shown in FIG. 1 will be described.

The CPU 10 for controlling the system converts the address signal, the control signal, and the parallel channel assignment data for channel assignment through the address bus, the control bus, and the data bus to the parallel / serial conversion and control click signal generator 11. When input, the parallel / serial conversion and control clock signal generation unit 11 converts the parallel channel allocation data into serial channel allocation data in series by a control signal output from the CPU 10 and simultaneously outputs the first clock. A signal is generated and input to the parallel conversion processing section 12 of the serial channel assignment circuit. At this time, the parallel / serial conversion and control clock signal generator 11 converts the input parallel data into serial and transmits the weight to the CPU 10 until the parallel conversion processing unit 12 in the serial channel allocation circuit is completed. Output the signal (W). Therefore, the CPU 10 remains in a weighted state until the output parallel channel allocation data is input to the parallel conversion processing unit 12. On the other hand, the parallel conversion processing unit 12 inputting serially converted channel allocation data parallelizes the input serial channel allocation data by the first clock signal output from the parallel / serial conversion and control clock signal generation unit 11. It converts the channel assignment data, generates a second clock signal, and outputs them to the latch unit 13. Output to the latch unit 13. The latch unit 13 latches the parallel channel allocation data output from the parallel conversion processing unit 12 by the input of the second clock signal and inputs the same to the comparator 14.

On the other hand, the counter 15 for inputting the frame synchronization signal and the third clock signal is reset to the system synchronization signal input every frame (125 μsec in one frame period) and receives the third clock signal inputted to the system synchronization signal before and after 32. The binary counting outputs 32 channel data to the comparator 14 at each clock input.

Accordingly, the comparator 14 compares the channel data of the system output from the counter 15 with the channel allocation data output from the latch unit 13 and compares the channel allocation data when the two channel data values are the same. (CHA) is output through the output line 16.

However, in the conventional circuit operated as described above, a channel assignment circuit composed of the parallel conversion processing section 12, the latch section 13, the counter 15, and the comparator 14 inputs the channel assignment data in series to provide a channel assignment signal. The parallel / serial conversion and control clock signal generator 11 for converting parallel channel allocation data output from the CPU 10 into serial channel allocation data was required. In the case of allocating consecutive channels immediately after allocating channels, interference between signals is generated because there is no time between adjacent channels, and the CPU 10 until the output data processing of the CPU 10 is serially converted and output is completed. Since there is a standby state, there is a problem in that the output channel allocation data cannot confirm whether the data is correct.

Accordingly, an object of the present invention is to provide a circuit capable of making the movement of the channel assignment data fast and the channel assignment quick by the simple circuit configuration by processing the channel assignment data in parallel in the subscriber circuit of the digital switch. .

It is still another object of the present invention to provide a circuit capable of checking the status of output channel assignment data.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

)와 리이드(Read) 신호(

)를 발생하는 입출력 제어신호 발생부이고, 23은 상기 입출력 제어신호 발생부(22)의 라이트(Write) 신호(

) 및 리이드(Read) 신호(

)의 출력에 따라 상기 CPU(21)로 부터 출력되는 채널 할당 데이타를 래치하고, 래치된 채널 할당 데이타를 상기 CPU(21)로 출력하는 데이타 래치 및 제어부이며, 26은 프레임 동기신호(Frame Sync)와 제1클럭(CLKA)을 입력하며, 하나의 프레임 기간내에 입력되는 상기 제1클럭을 32진 카운트하여 32개의 채널 데이타를 인크리스 출력하는 카운터부이고, 24은 상기 채널 할당 데이타 래치 및 제어부(23)로 부터 출력되는 채널 할당 데이타와 상기 카운터부(26)로부터 출력되는 채널 데이타를 비교하여 비교값이 값을 때 해당 채널을 할당하는 채널 할당 신호를 출력하는 비교기부이고, 25은 상기 비교기부(24)로부터 출력되는 해당 채널 할당 신호를 상기 채널 할당 데이타 래치 및 제어부(23)의 출력제어 신호와 소정주기를 가지는 제2클럭 신호(CLKB)에 의해 최종 출력을 결정하는 출력제어부이다.2 is a block diagram according to the present invention, reference numeral 21 in the figure inputs and outputs channel allocation data through a data bus, and outputs an address signal and a control signal to an address bus ADD and a control bus CNTS. It is a CPU (Central Processing Unit; Microprocessor) to control collectively, 22 is inputted and decoded the address signal and the control signal, and according to the decoded signal channel allocation data and write signal (

) And read signal (

) Is an input / output control signal generator that generates a signal, and 23 denotes a write signal of the input / output control signal generator 22.

) And read signal (

Is a data latch and a control unit for latching channel allocation data output from the CPU 21 and outputting the latched channel allocation data to the CPU 21 according to the output of the CPU 21, and 26 denotes a frame sync signal. And a counter for inputting a first clock (CLKA), and counting the first clock input within one frame period by 32 digits and increating 32 channel data. A comparator unit for comparing the channel assignment data outputted from 23) with the channel data outputted from the counter unit 26 and outputting a channel assignment signal for allocating the corresponding channel when the comparison value is determined, and 25 denotes the comparator unit. The final output is determined by the corresponding channel assignment signal outputted from 24 by the second clock signal CLKB having the predetermined period and the output control signal of the channel assignment data latch and control unit 23. It is the output control section.

이다. 제2클럭(CLKB)는 시스템 데이타전송 클럭으로서

이다.The frame sync signal in the above-described configuration is a signal string indicating a head of a frame and having a "high" or "low" signal for a 488 sec period every 125 sec. The first clock CLKA is a signal for dividing one frame into 32 equal frequencies and has a frequency of 3.906 sec.

to be. The second clock CLKB is a system data transmission clock.

to be.

3 is a detailed circuit diagram of the block diagram of FIG. 2 according to the present invention, in which the decoders 31 and 32 correspond to the input / output control signal generator 22, and the latch circuit 33 and the buffer 34 are channels. Corresponding to the allocation data latch and control unit 23, the exclusive oar gates 35-39 and the no-gate 40 correspond to the comparator unit 24, and the counters 42 and 43 correspond to the counter unit ( 26, the flip-flop 41 and the end gate 44 correspond to the output control unit 25.

이다. 그리고 (c)(d)(e)(f)(g)는 카운터부(26)의 출력파형이며 (h)는 비교기(24)의 출력 노오드 (X)의 출력 파형도로서, 채널 할당 데이타가 Φ채널인 경우이다.4 is an operation waveform diagram of a part of FIG. 3, (a) is a waveform of the frame sync signal (Fram Syne) (FS), and (b) is an input waveform of the first clock CLKA.

to be. And (c) (d) (e) (f) (g) are output waveforms of the counter section 26, and (h) is an output waveform diagram of the output node X of the comparator 24, and channel assignment data. Is the case of Φ channel.

이며, (C),(D),(E),는 (B)의 제2클럭(CLKB)을 분주한 파형도로서,

이며, (F)는 (E)의 클럭이 위상지연된 것으로 제1클럭(CLKA)

이다. (G)는 노오드(X)의 출력 파형이고, (H)는 플립플롭(41)의 출력파형이며, (I)는 앤드게이트(44)의 출력파형이다.5 is an operational waveform diagram of a part of FIG. 3, (A) is a waveform of the frame synchronizing signal FS, and (B) is an input waveform of the second clock stage CLKB.

(C), (D), (E), are waveform diagrams in which the second clock CLKB of (B) is divided,

(F) is the clock of (E) is phase delayed and the first clock (CLKA)

to be. (G) is an output waveform of the node X, (H) is an output waveform of the flip-flop 41, and (I) is an output waveform of the AND gate 44.

An operation example of FIG. 3, which is an exemplary embodiment according to the present invention, will now be described in detail with reference to FIGS. 2, 4, and 5.

를 데이타버스, 어드레스버스(ADD), 제어버스(DNTS)를 통해 각각 출력하면, 상기 병렬 채널 할당 데이타는 채널 데이타 래치 및 제어부(23)내 래치회로(33)에 입력되고, 어드레스(A0,A1) 및 기입제어 신호

는 입출력 제어신호 발생부(22)내 디코더(31)에 입력되어진다. 이때 상기 디코더(31)는 CPU(21)로부터 출력된 기입제어신호

에 의해 인에이블되어 상기 CPU(21)로부터 출력된 어드레스신호(A0,A1)를 디코딩하여 출력하는데, 상기 어드레스신호(A0,A1)가"ΦΦ "이라면 래치회로(33)의 클럭단자(CK)에 접속된 출력단자(Y0)로 디코딩 신호를 출력한다.Parallel channel assignment data and addresses (A0, A1) and subscription control signals for allocating a call channel of an arbitrary subscriber by the CPU 21, which now collectively controls the system.

Is output via the data bus, the address bus ADD, and the control bus DNTS, respectively, the parallel channel allocation data is input to the channel data latch and the latch circuit 33 in the control section 23, and the addresses A0 and A1. ) And write control signal

Is input to the decoder 31 in the input / output control signal generator 22. At this time, the decoder 31 writes the control signal output from the CPU (21)

Is decoded and output by the address signals A0 and A1 output from the CPU 21. If the address signals A0 and A1 are " Φ ", the clock terminal CK of the latch circuit 33 is output. The decoded signal is outputted to an output terminal Y0 connected to.

Accordingly, the latch circuit 33 latches the parallel channel allocation data input through the data bus by the decoding output of the decoder 31 so that the input terminal I0-I5 and the exclusive of the buffer 34 are exclusive. Input to each terminal of the OA gate (hereinafter referred to as "EX-OR") (35-39).

)의 "로우"신호 입력에 의해 클리어되어진 후 차기의 프레임 동시신호(

)가 입력되는 기간동안 제1클럭(CLKA)를 제4도(c)(d)(e)(f)(g)와 같이 32진 카운팅하여 프레임내 채널 데이타를 BX-OR(35-39)의 각각의 타측단으로 출력한다.On the other hand, the counter in the counter unit 26 for inputting the frame synchronizing signal FS as shown in FIG. 4 (a) and the first clock CLKA as shown in FIG. 42 and the counter 43 cascaded to the counter 42 are the frame sync signal (

The next frame simultaneous signal (after cleared by "low" signal input)

During the period in which the first clock CLKA is inputted, 32-bit counting is performed as shown in FIG. 4 (c) (d) (e) (f) (g) and BX-OR (35-39) Output to each other end of.

)인 제2클럭(CLKB)를 제5도(e)와 같이 8분주한

의 클럭을 388nsec정도 지연시킨 클럭으로 제5도 (F)와 같다. 따라서 카운터부(26)은 프레임 동기신호(

)의 구간(125μsec)은 3.906μsec의 주기를 갖는 제1클럭(CLKA)으로서 Φ부터 31까지 32진 카운팅하여 32채널 데이타를 카운팅 출력하게된다.At this time, the first clock CLKA is an inverted system clock synchronized with the frame synchronizing signal FS as shown in FIG.

The second clock (CLKB) is divided into 8 as shown in Fig. 5 (e).

This clock is delayed by about 388nsec. As shown in FIG. Therefore, the counter 26 is a frame synchronizing signal (

) Section 125μsec is the first clock CLKA having a period of 3.906μsec and counts 32 channels from Φ to 31 to count 32 channels of data.

Therefore, each of the EX-ORs 35-39 outputs a "low" signal to the noble gate 40 when the input signals of the two input terminals coincide with each other.

For example, in the state where the above-described CPU 21 outputs parallel channel data MSB1 0 0 0 0 LSB for selecting the? Channel which is the first channel among 32 channels, and the latch circuit 33 latches it, the counter If the unit 26 is cleared by the frame synchronizing signal FS and outputs counting data ΦΦΦΦΦ to the output terminals Q4-Q0, the inputs of both terminals of each of the EX-ORs 35-39 are all input. (The most significant bit Q5 (MSB) among the outputs of the latch circuit 33 is an output control signal bit.) Therefore, each of the EX-ORs 35-39 is a gate of a logic " low " signal. Output to (40).

Therefore, the noble gate 40 outputs a logic "high" as shown in FIG. 4 (h), which is counter 42 and 43 of the counter unit 26 counting the first clock CLKA. It remains as shown in FIG. 4 (h) until the MSB 00001 LSB (decimal "1") is output to the output terminals Q4-Q0.

)에 동기된 시스템 클럭인 제5도(a)와 같은 제2클럭(CLKB)

이 입력되어진다.The output of the noah gate 40 output as shown in FIG. 4 h is simultaneously input to the input terminal D and the end gate 44 of the flip-flop 41. At this time, the clock input terminal CK of the flip-flop 41 has a frame synchronization signal (

The second clock (CLKB) as shown in FIG.

Is inputted.

Accordingly, the flip-flop 41 outputs the output of the NOA gate 40 output as shown in FIG. 5 (g) (the same signal as in FIG. 4 (h)) to the second clock (FIG. 5B). CLKB) and outputs a delay of about 100 nsec as shown in FIG. Therefore, the AND gate 44 outputs the NOR gate 40 as shown in FIG. 5G and the output terminal Q5 of the flip-flop 41 as shown in FIG. 5H and the latch circuit 33. The output control signal output as logic " 1 " at " " is multiplied and output as shown in FIG.

Therefore, the operation of the flip-flop 41 results in a margin of about 100 nsec between the X point and the output of the AND gate 44, which are the output points of the NOA gate 40. In case of sequentially assigning channel 1, signal interference can be prevented.

를 출력하면 이는 디코더(32)로 입력한다. 이때 디코더(32)는 상기 리이드 제어신호

에 의해 인에이블 되어 CPU(21)가 출력한 어드레스(A0,A1)을 디코딩 하여 버퍼(34)의 인에이블 단자

로 "로우"신호를 출력한다. 따라서 입력단자(I0-I6)가 상기 래치회로(33)의 출력단자(Q0,Q5)와 연결된 버퍼(34)는 입력단자(I0-I5)로 입력되는 상기 래치회로(33)의 출력데이타를 출력단자(Y0-Y5)로 출력하여 이를 데이타 버스로 출력한다. 따라서 상기 CPU(21)는 어드레스와 리이드 제어 신호를 출력함으로서 데이타버스를 통해서 이전에 출력한 병렬 채널 할당 데이타를 확인할 수 있다.When the CPU 21 wants to check the output parallel channel allocation data, the address signals A0 and A1 and the read control signal are transmitted through the address bus ADD and the control signal bus CNTS.

Outputs it to the decoder 32. At this time, the decoder 32 is the lead control signal

Enable terminal of the buffer 34 by decoding the addresses A0 and A1 output by the CPU 21

Outputs a "low" signal. Accordingly, the buffer 34 having the input terminals I0-I6 connected to the output terminals Q0 and Q5 of the latch circuit 33 receives the output data of the latch circuit 33 input to the input terminals I0-I5. Output to the output terminal (Y0-Y5) and output it to the data bus. Therefore, the CPU 21 can check the parallel channel allocation data previously output through the data bus by outputting an address and lead control signal.

As described above, the present invention provides an advantage in that the channel assignment data can be processed in parallel in the subscriber circuit of the digital switchboard, so that the channel can be allocated at a high speed with a simple circuit configuration, and the movement of the channel assignment data can be made flexible. This has the advantage that you can check the output channel assignment data.

Claims (3)

1. A channel assignment circuit of a digital exchange having a CPU 21 for inputting and outputting channel assignment data to a data bus and outputting an address signal and a control signal to an address bus and a control bus, respectively, to control channel assignment. The channel allocation data of the CPU 21 connected to the data bus with a control terminal for inputting a control signal is latched and output by a first control signal input to the control terminal, and A channel data latch and control unit 23 for outputting the latched channel allocation data to the data bus by a second control signal input to a control terminal, and the control of the CPU 21 and the channel data latch and control unit 23 A first control signal and a second control signal are decoded between the terminals and decoded from the CPU 21 to output the first control signal and the second control signal. Input / output control signal generator 22 outputting to latch and controller 23, frame synchronizing signal and first clock CLKA are input, and the first clock input in one frame is counted and 32 frames are included in the frame. The counter section 26 for outputting channel data is compared with the channel assignment data output from the channel assignment data latch and control section 23 and the counter section 26 and the channel data counted, respectively, and the two channels match when the two values match. A comparator unit 24 for outputting an allocation signal and an input terminal are connected to an output terminal of the comparator unit 24. The channel assignment signal inputted to the input terminal has a predetermined phase difference from the first clock CLKA. Is an output control section (25) for outputting a synchronous delay with a second clock (CLKB). 2. The channel assignment data latch and control unit (23) according to claim 1, wherein an input terminal (D0-D5) is connected to the data bus and an output terminal (Q0-Q4) is connected to one input terminal of the comparator unit (24). And a latch 33 connected to the input / output terminal to latch channel allocation data via the data bus according to a first control signal of the input / output control signal generator 22, and outputting the output of the latch 33 to the input / output terminal. And a buffer (34) which is enabled by a second control signal of a control signal generator (22) and outputs to the data bus. 3. The comparator portion 24 is connected to an output terminal Q0-Q4 of the latch 33, one terminal of each of which is connected to the output terminal of the counter portion 26, and the other. EX-OR (35-39) for the exclusive OR of the signal input to each of the two terminals, and the oragate 40 for negative logic output to the output of the EX-OR (35-39) Channel assignment circuit of the digital exchange.

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