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KR900001325Y1 - Synchronizing devision circuit for satelite signal receiver - Google Patents

Synchronizing devision circuit for satelite signal receiver Download PDF

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Publication number
KR900001325Y1
KR900001325Y1 KR2019870011544U KR870011544U KR900001325Y1 KR 900001325 Y1 KR900001325 Y1 KR 900001325Y1 KR 2019870011544 U KR2019870011544 U KR 2019870011544U KR 870011544 U KR870011544 U KR 870011544U KR 900001325 Y1 KR900001325 Y1 KR 900001325Y1
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KR
South Korea
Prior art keywords
resistor
circuit
transistor
capacitor
devision
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KR2019870011544U
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Korean (ko)
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KR890003873U (en
Inventor
박의준
권희성
이준호
Original Assignee
삼성전자주식회사
안시환
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Priority to KR2019870011544U priority Critical patent/KR900001325Y1/en
Publication of KR890003873U publication Critical patent/KR890003873U/en
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Publication of KR900001325Y1 publication Critical patent/KR900001325Y1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals
    • H04N5/10—Separation of line synchronising signal from frame synchronising signal or vice versa
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/16—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level
    • H04N5/18—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level by means of "clamp" circuit operated by switching circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/20—Adaptations for transmission via a GHz frequency band, e.g. via satellite

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Astronomy & Astrophysics (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronizing For Television (AREA)

Abstract

내용 없음.No content.

Description

위성방송 수신기의 온스크린 기능을 위한 동기분리장치Synchronous Separator for On-Screen Function of Satellite Broadcast Receiver

제1도는 본 고안에 따른 회로도.1 is a circuit diagram according to the present invention.

제2도는 본 고안에 따른 제1도의 동작 파형도.2 is an operational waveform diagram of FIG. 1 according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 클램프회로 R1-R10 : 저항10: clamp circuit R1-R10: resistance

D1 : 다이오드 C1-C2 : 캐패시터D1: Diode C1-C2: Capacitor

Q1-Q2 : 트랜지스터Q1-Q2: transistor

본 고안은 위성방송 수신기의 온스크린에 필요한 비디오 동기 분리회로에 관한 것으로써, 특히 클램프(Clamp)회로를 이용하여 동기를 진폭분리한후 수평동기와 수직동기를 분리할수 있는 회로에 관한 것이다.The present invention relates to a video synchronization separation circuit required for on-screen of a satellite broadcasting receiver, and more particularly to a circuit capable of separating horizontal and vertical synchronization after amplitude separation using a clamp circuit.

일반적으로 동기분리 방식에는 진폭분리방식과 PLL방식등이 있다. PLL방식은 동기분리가 안정화되나 부품수가 증가하여 원가상승의 문제가 되고 있으며, 진폭분리 방식은 집적회로화되어 있긴하나 고가인 결점이 있었다.Generally, synchronous separation includes amplitude separation and PLL. The PLL method stabilizes synchronous separation but increases the number of parts, which is a problem of cost increase. The amplitude separation method has an integrated circuit but has an expensive defect.

따라서 본 고안은 종래의 문제점을 해결하기 위해 최소의 부품으로 위성 방송 수신기내의 클램프회로를 이용하여 동기의 진폭분리를 하고 수평동기에서 수직동기를 분리하여 위성수신기의 온스크린용으로 사용할수 있는 동기분리 회로를 제공함에 있다.Therefore, in order to solve the conventional problems, the present invention uses a clamp circuit in a satellite broadcasting receiver to minimize the amplitude of the synchronization, and separate the vertical synchronization from the horizontal synchronization, which can be used for the on-screen of the satellite receiver. In providing a circuit.

이하 본 고안을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1도는 본 고안에 따른 회로도로써, 제1도중 R1-R10은 저항, D1은 다이오드, Q1-Q2는 트랜지스터, C1-C2는 캐패시터 10은 클램프회로이며, 비디오 신호는 상기 클램프회로(10)에 입력하여 일정레벨로 클램핑한 후 저항(R1)과 다이오드(D1)를 지나 트랜지스터(Q1)의 베이스에 연결되는데, 상기 저항(R1)은 트랜지스터(Q1)의 보호용이고, 다이오드(D1)는 드레쉬홀더 레벨조절용이다. ,1 is a circuit diagram according to the present invention, in which R1-R10 is a resistor, D1 is a diode, Q1-Q2 is a transistor, C1-C2 is a capacitor 10 is a clamp circuit, and a video signal is connected to the clamp circuit 10. After input and clamped to a predetermined level, it is connected to the base of the transistor Q 1 through the resistor R 1 and the diode D 1 , and the resistor R1 is for protecting the transistor Q1 and the diode D1. Is for adjusting the dresser level. ,

상기 트랜지스터(Q1)의 콜렉터에 전원(VCC)이 저항(R6)을 통해 인가되고, 또한 저항(R2)으로부터 캐패시터(C1)는 적분기로 구성되며, 상기 방전회로로부터 저항(R3)는 적분기로 구성되며, 상기 방전회로로부터 저항(R3)에 캐패시터(C2)를 연결하여 Low Pass Filter가 되고 저항(R9)을 통해 트랜지스터(Q2)의 베이스에 연결되도록 구성된다.The power supply VCC is applied to the collector of the transistor Q1 through the resistor R6, and the capacitor C1 is formed of an integrator from the resistor R2, and the resistor R3 is formed of an integrator from the discharge circuit. The capacitor C2 is connected to the resistor R3 from the discharge circuit to form a low pass filter and is connected to the base of the transistor Q2 through the resistor R9.

제2도는 본 발명에 따른 동작 파형도로서 (2a)파형은 클램프회로(10)에서 클램프 전압(Vc)에 클램핑된 영상신호이고, (2b)는 수평동기(Hsync)신호로 트랜지스터(Q1)의 출력이며, (2C)는 저항 (R2)과 캐패시터(C1)에 의한 적분신호이고, (2d)는 저항(R3)과 캐패시터(C2)에 의한 필터링 신호이며, (2e)는 트랜지스터(Q2)의 출력 수직동기(Vsync)신호이다.FIG. 2 is an operating waveform diagram according to the present invention, where waveform (2a) is an image signal clamped to the clamp voltage Vc in the clamp circuit 10, and (2b) is a horizontal synchronous (Hsync) signal of the transistor Q1. (2C) is an integrated signal by the resistor (R2) and the capacitor (C1), (2d) is a filtering signal by the resistor (R3) and the capacitor (C2), (2e) is the output of the transistor (Q2) Output vertical sync (Vsync) signal.

따라서 본 고안의 구체적 일실시예를 제1,2도를 참조하여 상세히 설명하면 수신기로부터 입력된 영상신호가 클램프 회로(10)를 지나면 제2도의 (2a)파형과 같이 클램프레벨(Vc)로 클램핑된다. 이때 Vc=1.4가 된다고 가정하면 1.4보다 작은 동기신호에서 스위칭 트랜지스터(Q1)은 오프되고, 1.4보다 큰 신호에서는 온되어 트랜지스터(Q1)의 콜렉터에는 (2b)파형과 같이 수평동기(Hsync)신호가 발생된다. 이어서 저항(R2)을 통해 캐패시터(C1)에 충전되는데, 트랜지스터(Q1)의 온/오프에 따라 충방전하고, 적분하여 (2C)와 같이 출력된다. 이 신호가 저항(R3)과 캐패시터(C2)에 의한 저역필터를 통과하면(2d)와 같이 출력되어 트랜지스터(Q2)을 온/오프한다. (2d)파형의 "하이"에서 트랜지스터(Q2)를 온하면 (2e)파형과 같이 반전되어진 수직동기(Vsync)를 얻을 수 있다.Therefore, when a specific embodiment of the present invention is described in detail with reference to FIGS. 1 and 2, when the image signal input from the receiver passes through the clamp circuit 10, it is clamped to the clamp level Vc as shown in the waveform (2a) of FIG. do. Assuming that Vc = 1.4, the switching transistor Q1 is turned off at a synchronous signal smaller than 1.4, and turned on at a signal greater than 1.4, so that the horizontal sync (Hsync) signal is applied to the collector of the transistor Q1 as shown by the waveform (2b). Is generated. Subsequently, the capacitor C1 is charged through the resistor R2. The capacitor C1 is charged and discharged according to the on / off of the transistor Q1, and is integrated and output as (2C). When the signal passes through the low pass filter by the resistor R3 and the capacitor C2 (2d), it is output as shown in 2d to turn the transistor Q2 on and off. The transistor Q2 is turned on at the "high" of the (2d) waveform to obtain the vertical inverted Vsync inverted like the (2e) waveform.

상술한 바와같이 위성방송 수신기에 클램프 회로를 사용하므로써 동기분리를 안정하게 할 수 있고 집적회로를 사용하는 것보다도 저렴하게 구성할수 있으며, 수직동기를 분리할때 많은 리플이 타고 있지만 저역필터를 통과하면 깨끗한 신호가 되어지므로 더욱 안전한 수직동기를 분리할 수 있는 이점이 있다.As described above, by using the clamp circuit in the satellite broadcasting receiver, the synchronous separation can be stabilized and can be configured cheaper than using the integrated circuit. Since it is a clean signal, there is an advantage of separating the safer vertical synchronization.

Claims (1)

수직, 수평동기 분리회로에 있어서, 수신영상의 동기를 일정 클램프 레벨(Vc)로 클램핑하는 위성수신기내의 클램프 회로를 이용하는 제1수단과 상기 클램핑된 신호를 직렬 연결된 저항(R1)과 드레쉬홀드 레벨조정용 다이오드(D1)로 입력하고 트랜지스터(Q1)의 베이스에 입력하여 수평동기를 분리해내는 제2수단과, 상기 제2수단의 출력을 저항(R2)과 캐패시터(C1)에 의해 충방전하고 적분하며, 저항(R3)과 캐패시터(C2)에 의해 필터링하고 트랜지스터(Q2)의 베이스에 인가하여 수직 동기를 분리해 내는 제3수단으로 구성됨을 특징으로 하는 회로.In the vertical and horizontal synchronous separation circuits, a first means using a clamp circuit in a satellite receiver which clamps synchronization of a received image to a constant clamp level (Vc), and a resistor (R1) and a threshold level connected in series with the clamped signal. A second means for inputting to the adjusting diode D1 and input to the base of the transistor Q1 to separate horizontal synchronism, and the output of the second means is charged and discharged by the resistor R2 and the capacitor C1 and integrated; And third means for filtering by a resistor (R3) and a capacitor (C2) and applying it to the base of the transistor (Q2) to separate vertical synchronization.
KR2019870011544U 1987-07-14 1987-07-14 Synchronizing devision circuit for satelite signal receiver KR900001325Y1 (en)

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KR2019870011544U KR900001325Y1 (en) 1987-07-14 1987-07-14 Synchronizing devision circuit for satelite signal receiver

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Application Number Priority Date Filing Date Title
KR2019870011544U KR900001325Y1 (en) 1987-07-14 1987-07-14 Synchronizing devision circuit for satelite signal receiver

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KR900001325Y1 true KR900001325Y1 (en) 1990-02-20

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010029300A (en) * 1999-09-30 2001-04-06 백명기 vending machine having a cleaning machine of water
US7710717B2 (en) 2005-07-18 2010-05-04 Samsung Electronics Co., Ltd. Buffer for disk drive and disk drive assembly having the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010029300A (en) * 1999-09-30 2001-04-06 백명기 vending machine having a cleaning machine of water
US7710717B2 (en) 2005-07-18 2010-05-04 Samsung Electronics Co., Ltd. Buffer for disk drive and disk drive assembly having the same

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Publication number Publication date
KR890003873U (en) 1989-04-14

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