KR840000227B1 - Tuning control apparatus of receiver - Google Patents

Abstract

The tuning control apparatus uses a voltage-controlled oscillater (VCO) to produce a local oscillator signal. The control voltage for the VCO is provided in response to the division rate of a programmable divider. The S-curve tracing AFC loop supplies control votage to the VCO in response to the S-curve signals obtained from a frequency detecting circuit.

Description

Receiver tuning device

1 is a block diagram of one embodiment of the present invention.

2 (a) to 2 (e) are timing charts during the PLL operation of the present invention.

FIG. 3 is a detailed circuit diagram of the second charge pump 20 of FIG.

4 is a detailed circuit diagram of the first charge pump 13 of FIG.

5 (a) and 5 (b) are waveform diagrams for explaining FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tuning control apparatus for a receiver for electronically controlling a DC voltage applied to a variable capacitance diode (variable diode) based on a digital resin corresponding to a broadcasting frequency to perform tuning of the receiver.

In general, there are two types of tuner devices of a receiver, a PLL synthesizer method using PLL technology and a voltage synthesizer method by D / A exchange. The PLL synthesizer method produces a local oscillation frequency necessary for reception by a PLL loop based on a modified reference frequency, and thus has good tuning accuracy and stability. However, the noise characteristic tends to be deteriorated due to the fluctuation of the harmonic loops of the divider signal in the PLL loop.

In addition, there is a drawback that the dynamic adjustment density of the receiver depends on the nonuniformity of the ceramic filter of the intermediate frequency. On the other hand, since the D / A switching voltage synthesizer system controls a local oscillation circuit having a voltage controlled oscillator with a DC voltage, there is an advantage that a high S / N ratio is easily obtained by using a conventional tuner technology. There was a problem.

The present invention takes this into consideration, and the tuning operation of the receiver is performed by the PLL synthesizer method, and after tuning, the S-curve following automatic frequency which controls the local oscillation frequency by using the S-line signal obtained by the output of the detection circuit. A correction (S trunk line tracking AFC) operation is to provide a novel tuning control device for putting a receiver in a reception state.

EMBODIMENT OF THE INVENTION Hereinafter, it demonstrates, referring drawings for an Example.

In Fig. 1, reference numeral 1 denotes a general EM receiver, and at the antenna 2, the received signal is amplified by the radio frequency amplifier 3, and converted in the mixing circuit 4 to an intermediate frequency. After being amplified by the intermediate frequency amplifier circuit 5, detected by the detector circuit 6 again, and amplified by the low frequency amplifier circuit 7, the sound is emitted through the speaker 8.

(9) is an S-line following AFC operation loop, (10) is a local oscillation circuit having a voltage controlled oscillator, and its oscillation frequency is changed in accordance with the DC voltage value applied through the low pass filter (11). Denoted at 12 is a DC amplifier for directly amplifying the S-line signal from the FM detector 6, and at 13, a comparator having a minimum ttnneshhold level of two values. The first charge pump generates three digital values corresponding to the output (a first non-state "H" level, a second state "L" level, and a third state "high impedance").

Next, (14) is a PLL loop, (15) is a frequency division circuit for dividing at a predetermined frequency at the central oscillation frequency, and (16) is a value stored in the pre-memory memory (17) from the frequency division circuit (15). Programmable divider that re-splits the output of a. 18 is a phase detection circuit for comparing the phase of the reference frequency from the reference frequency generator circuit 19 by correction with the local oscillation frequency divided by the programmer divider 16, and 20 is a phase detection circuit. The second charge pump generates three digital values (first state "H" level, second state "L" level, and third state "high impedance") corresponding to the output of.

Here, the local oscillation circuit 10 and the low pass filter 11 are commonly used in the PLL loop and the S-line following AFC operation loop.

The switching between the PLL operation and the S-line following AFC operation is performed by the switch 22 controlled by the switch switching signal P / S generated by the control circuit 21.

Reference numeral 23 denotes a lock detection circuit for detecting that the PLL loop is locked, and reference numeral 24 denotes an IF level detection circuit for detecting a signal level of an intermediate frequency. 25 denotes a channel key, 26 denotes an advance decoder, and when pre-selection turns on the channel key 25, the contents of the transpose memory 17 at the designated address are changed to the programmer divider 16. Is sent to, and tuning is performed.

In addition, (27) is a ringing key, (28) is a falling key, and when the channel key 25 is off, the value set to the programmer divider 16 is increased (+1) and reduced (-1), respectively. In this state, when the recording key 29 and the channel key 25 are turned on, the weight or the reduced value is stored in the transpose memory 17 at the address designated by the advanced decoder 26.

Hereinafter, the operation of the present invention will be described with reference to the drawings. First, when the channel key 25 is turned on, the contents of the designated pre-memory memory 17 are set in the programmer divider 16, and at the same time, the control circuit 21 switches the switch 22 to the switch 22 (P / S). Is applied, the point P side circuit of FIG. 1 is connected, and a PLL loop is formed.

For this reason, the local oscillation frequency is divided by the division circuit 15 and the programmer divider 16 and applied to the first input terminal of the phase detection circuit 18. On the other hand, the reference frequency of the reference frequency issuing circuit 19 is applied to the second input terminal of the phase detection circuit 18, and the phase and frequency of both input signals are compared.

Regularly, as shown in the timing table of FIG. 2, when the divided local oscillation frequency f _P is ahead of the reference frequency f ₀ , the first output signal of the phase detection circuit 18 ( When u) generates an "L" level and the phase is delayed, the second output signal D generates an "H" level. Therefore, when the phases coincide, the first output signal u becomes "H" level and the second output signal D becomes "L" level.

According to the first output signal u and the second output signal D of the phase detection circuit 18, the second charge pump 20 generates a digital value of three values, and the digital value is a low pass filter ( 11), D / A conversion is applied to the varactors of the local oscillation circuit 10 and the radio frequency amplifier circuit 3 as DC voltages. According to the level of this DC voltage, the local oscillation frequency is determined.

Here, the specific example of the 2nd charge pump 20 is shown in FIG. As shown in the drawing, the second charge pump 20 is composed of a P-channel MOS transistor (abbreviated as P-MOS) and an n-channel MOS transistor (abbreviated as n-MOS). If the first output signal u of 18) is " H " and the second output signal D is " L ", then the P-MOS and n-MOS are turned off together, and the output is " high impedance " When the first output signal u and the second output signal D are "H" together, the P-MOS is turned on and the n-MOS is turned off to set the "H" level. When the signal u and the second output signal D together are "L", the P-MOS is turned off and the n-MOS is turned on to output the "L" level. That is, as shown in the second (e), the output signal C ₂ of the second charge pump 20 has a divided local oscillation frequency f _{P in} phase with the reference frequency f ₀ . If it is delayed, the first state "H" level, if the phase is advanced, the second state "L" level, and if the phases match, the third state "high impedance" is obtained.

However, in order to make the divided local oscillation frequency f _P coincide with the reference frequency f ₀ , if the frequency f _P is ahead of the reference frequency f ₀ , the frequency f _P When the phase is delayed and the phase is delayed, it is necessary to raise the frequency f _P. Therefore, in the present embodiment, the local oscillation frequency is lowered by the direct current voltage corresponding to the "L" level signal of the second charge pump 20 by the direct current voltage corresponding to the "H" level signal. By raising, it is possible to match the frequency f _P with the reference frequency f ₀ .

As described above, the PLL loop is locked and the tuning operation is completed by the PLL operation. At this point in time, the low pass filter 11 stores the tuning voltage obtained by the PLL operation.

Next, when the PLL loop is locked and the output signal of the lock detection circuit 23 is generated, the switch switching signal P / S is applied to the switch 22 in the control circuit 21, so that the circuit is on the S side. Is connected to the S-line following AFC operation.

In the S-line following AFC operation, first, the S-line signal of the detection circuit 6 is amplified by the DC amplifier 12 and applied to the first charge pump 13. The first charge pump 13 has two values of at least the level of the level (V _SL ), (V _SH ), (V _S ^L > V _SH ), and as shown in FIG. When the S main line signal V _S is higher than the first minimum value level V _SL , the outputs of the first operational amplifier 30 and the second operational amplifier 31 are both "L" and P- MOS is on and n-MO S is off. Therefore, the first charge AF 13 outputs the "H" level. In addition, when the S-line signal V _S is between the minimum level V _SL and the minimum level V _SH , the output of the first operational amplifier 30 is "H", so that the P-MOS is turned off. Since the output of the second operational amplifier 31 is "L", the n-MOS is also turned off, so that the output of the first primary pump jeep 13 is "high impedance".

Next, when the S main line signal V _S is lower than the second minimum level V _SH , the outputs of the first operational amplifier 30 and the second operational amplifier 31 are both "H", so that the P-MOS Is turned off, the n-MOS is turned on, and the first charge pump 13 outputs the "L" level. This figure is shown in FIG. 5, where FIG. 5 (a) shows the DC line signal V _S amplified by DC, and FIG. 5 (b) shows the output C of the first charge pump 13. ₁ ) is shown. In FIG. 5 (a), the period A is a period during which the output signal (SL signal) of the first continuous signal 30 is generated when the S trunk line signal V _S is higher than (V _SL ). Is the period during which the output signal (SH signal) of the second operational amplifier 31 occurs when the S main line signal (V _S ) is lower than (V _SH ), and the period B is a tuning period.

As shown, the SL signal is generated when the local oscillation frequency is lower than the tuning point. In this case, as shown in FIG. 5 (b), the first charge pump 13 outputs an "H" level. . In addition, the SH signal is generated when the local oscillation frequency is higher than the tuning point. In this case, the first charge pump 13 outputs an "L" level. The output of the azimuth pump 13 is "high impedance".

The output signal of the first charge pump 13 is converted into a direct current voltage by the low pass filter 11, and this voltage is added to the preset voltage obtained by the PLL operation to generate the local oscillation circuit 10, It is applied to the varactor of the radio frequency amplifier circuit 3. Therefore, as in the case of the second charge pump 20, the local oscillation frequency is raised by the DC voltage corresponding to the "H" level signal of the first charge pump 13, and corresponding to the "L" level signal. By the DC voltage, the local oscillation frequency is lowered, so that the receiver can be tuned.

However, in the case where the intermediate frequency is the weak power after pre-tuning, the IF level detection circuit 2 does not generate an output signal (SD signal), so that the control circuit 21 determines the unauthorized state of the SD signal, Instead of switching to the S-line following AEC operation by the switch 22, the reception operation is performed by the PLL operation to ensure reception safety.

As described above, the digital full-tuning method of the present invention performs the tuning operation of the receiver by the RLL synthesizer method, and when there is a broadcast signal after the tuning, the S-track line following AFC operation and when there is no broadcast signal. Since the receiver is placed in the reception state by the PLL operation, there are no mis-stations of adjacent channel stations, the reliability of the station can be obtained, and a reception method having excellent noise characteristics and coordination density of the reception system can be realized.

Further, in the above embodiment, the low pass filter is shared in the PLL loop and the S-line following AFC operation loop, but the main point of the present invention is not limited to these configurations. For example, the electric vehicle tuning device of the present invention can be realized even if a low pass filter is separately installed in each of the loops.

In the embodiment, since the FM receiver has been described, it is not necessary to provide a special circuit for generating the S-line characteristic. However, when the present invention is used for the AM receiver, the AM intermediate frequency amplifier circuit and the DC amplifier circuit are used. An S-line generating circuit is required.

Claims (1)

In a receiver comprising a voltage-controlled oscillator as a local oscillation circuit, at the time of preset tuning, the programmer divider sets division ratio data corresponding to a broadcasting station, and sets a control voltage according to this division ratio data to the voltage controlled oscillator. A S-curve following AFC loop for supplying a control voltage to the voltage-controlled oscillator in accordance with a PLL loop to be supplied to the voltage control circuit and a S-curve signal obtained from a frequency discriminating circuit connected to the intermediate frequency amplifier circuit of the receiver; Switching means for switching the S-curve following AFC loop, and an IF level detection circuit for detecting the output level of the intermediate frequency amplifying circuit, and switching after the preset selection operation in accordance with the output signal of the IF level detection circuit. Controlling means to switch from said PLL loop to said S-curve following AFC loop Tuning the controller of a receiver according to claim.

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