KR810001365Y1 - Fet switching circuit - Google Patents
Fet switching circuit Download PDFInfo
- Publication number
- KR810001365Y1 KR810001365Y1 KR2019800007499U KR800007499U KR810001365Y1 KR 810001365 Y1 KR810001365 Y1 KR 810001365Y1 KR 2019800007499 U KR2019800007499 U KR 2019800007499U KR 800007499 U KR800007499 U KR 800007499U KR 810001365 Y1 KR810001365 Y1 KR 810001365Y1
- Authority
- KR
- South Korea
- Prior art keywords
- fet
- gate
- potential
- capacitor
- switching circuit
- Prior art date
Links
- 239000003990 capacitor Substances 0.000 claims description 8
- 239000000843 powder Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/34—Muting amplifier when no signal is present or when only weak signals are present, or caused by the presence of noise signals, e.g. squelch systems
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- Noise Elimination (AREA)
Abstract
내용 없음.No content.
Description
제1도는 2전원 제어방식의 FET 스위치회로.1 is a FET switch circuit of a two power supply control system.
제2도는 1전원 제어방식의 FET 스위치회로.2 is a FET switch circuit of the one power supply control method.
본 고안은 튜우너의 뮤우팅(muting) 등에 사용하는 스위치회로에 관한 것이다.The present invention relates to a switch circuit for use in muting of the tuner.
뮤우팅은 튜우닝시에 잡음을 커트하는 것이지만, 그것에 사용하는 스위치에는 FET가 사용되고 있다. 그러나 이 FET를 사용한 종래의 스위치에는 뮤우팅 온(ON)시에 신호의 감쇄량이 충분하지 않기 때문에 입력신호의 누화(crosstalk)가 발생하게 되고 또 뮤우팅 오프(OFF)시에 입력신호 여하에 의하여 왜율(歪率)이 충분치 못하였던 것이다.Muting cuts noise during tuning, but FETs are used for the switches used therein. However, in the conventional switch using this FET, since the amount of attenuation of the signal is not sufficient when muting on, crosstalk of the input signal occurs, and when the muting off, Distortion was not enough.
본 고안은 상기와 같은 문제를 감안하여 FET의 게이트(gate) 회로를 개량 하므로써 상기 문제점을 모두 해소한 FET 스위치 회로를 제공하려고 하는 것이다.The present invention is to provide a FET switch circuit that solves all of the above problems by improving the gate circuit of the FET in view of the above problems.
본 고안의 실시예를 첨부도면에 따라 상세히 설명하면 다음과 같다.An embodiment of the present invention will be described in detail with reference to the accompanying drawings.
제1도는 2전원(정. 부) 제어방식을 이용한 FET 스위치회로로서 FET(Q)의 소오스(source)와 드레인(drain)에는 그 각각과 접지간에 소정의 저항(R1)(R2)을 접속하여 FET의 온. 오프에 관계없이 소오스나 드레인을 대략 접지전위가 되도록 한다. 그리고 게이트와 드레인사이에는 콘덴서(C2)를 접속하여, 게이트와 드레인사이의 위상관계를 동일하게 하며, 또 게이트에는 타단에 제어전압(Vc)이 가해지는 다이오드(D1)와 저항(R3)을 통하여 접지되는 다이오드(R2)를 접속한다. 또 상기 저항(R2) 및 저항(R1)의 병렬장치는 이 다이오드(D1)의 역방향 저항(RD1)보다도 충분히 적게한다. 콘덴서(C1)는 직류분 커트용이다.FIG. 1 is a FET switch circuit using a two power supply (positive and negative) control method. A source and a drain of a FET Q have a predetermined resistance R 1 (R 2 ) between each of them and ground. Turn on the FET by connecting. Regardless of the off state, bring the source or drain to approximately ground potential. The capacitor C 2 is connected between the gate and the drain to make the phase relationship between the gate and the drain the same, and the diode D 1 and the resistor R 3 to which the control voltage Vc is applied at the other end of the gate. Connect the grounded diode (R 2 ) through). The parallel device of the resistor R 2 and the resistor R 1 is sufficiently smaller than the reverse resistance R D1 of the diode D 1 . The capacitor C 1 is for cutting the DC powder.
위에서, 제어전압(Vc)을 부(負)의 전위로하여, FET(Q)의 게이트전위(G점)를 -10v로 하면, 그 FET(Q)는 차단(cut off) 되는데, 이때 다이오드(D1)는 다이오드(D2) 및 저항(R3)에 의하여 흐르는 순방향 전류에 의하여 내부저항이 감소된다. 즉 다이오드(D1)는 바이어스되기 때문에 예컨데, FET(Q)를 통과하는 누화성분이 있더라도 그 서운은 컨덴서(C2) 및 다이오드(D1)를 통해서 바이패스되어 충분한 감쇄량을 얻을수 있게 된다.In the above, when the control voltage Vc is set to the negative potential and the gate potential (G point) of the FET Q is -10v, the FET Q is cut off. The internal resistance of D 1 ) is reduced by the forward current flowing through the diode D 2 and the resistor R 3 . That is, since the diode D 1 is biased, for example, even if there is a crosstalk component passing through the FET Q, the swell is bypassed through the capacitor C 2 and the diode D 1 to obtain a sufficient amount of attenuation.
또 이 누화성분은 다이오드(D2)에 의해서도 바이패스 된다.This crosstalk component is also bypassed by the diode D 2 .
다음에, 제어전압(Vc)는 정(正)의 전위로하여 FET(Q)의 게이트전위를 +5v로 하면, FET(Q)는 온(ON) 상태로 되고 이때의 출력(OUT)의 전위는 입력신호가 없다고 한다면,로 되지만 상기한 바와 같이 R2≪RD1으로 선택하여 두면, 출력전위(Vour)는 작고, 대략 접지전위에 가까운 전위로 된다.Next, when the control voltage Vc is a positive potential and the gate potential of the FET Q is + 5v, the FET Q is turned on and the potential of the output OUT at this time is turned on. If there is no input signal, However, if R 2 < R D1 is selected as described above, the output potential Vour is small and becomes a potential close to the ground potential.
상기한 FET(Q)가 차단시에도 FET(Q)의 게이트. 소오스간의 저항이 크기 때문에 출력전위(Vour)는 접지전위로 된다. 따라서 절환시에 발생하는 음은 매우 작아서 지장이 없게 된다.The gate of the FET Q even when the FET Q is blocked. Since the resistance between the sources is large, the output potential (Vour) becomes the ground potential. Therefore, the sound generated at the time of switching is very small so that there is no problem.
또, 상기한 바와같은 FET(Q)의 온상태에 있어서, 입력신호가 매우 큰 경우, 소오스와 게이트 사이가 역바이어스에 가까운 상태로 되고, FET(Q)를 통과하는 신호에 왜곡이 일어나지만, 드레인과 게이트와의 사이에 콘덴서(C2)를 접속하고 있기 때문에 게이트는 신호에 응하여 대략 같은 위상관계로 변화하므로, 바이어스는 일정상태로 유지되고, 왜율(歪率)은 양호하게 된다.In the ON state of the FET Q as described above, when the input signal is very large, the source and the gate are close to reverse bias, and distortion occurs in the signal passing through the FET Q. Since the capacitor C 2 is connected between the drain and the gate, the gate changes in approximately the same phase relationship in response to the signal, so that the bias is kept constant and the distortion is good.
또 다이오드(D1)·(D2)의 역저항치에 편차가 있으면, 상기한 절환음(切換音), 왜율등에 영향을 주지만, 이와같은 경우에는 다이오드(D1)에 병렬로 1OMΩ정도의 고저항(R4)을 접속하면 된다.If the reverse resistance values of diodes (D 1 ) and (D 2 ) are different, they affect the above-mentioned switching sound, distortion, etc., but in such a case, a high of about 1OMΩ in parallel with diode (D 1 ). The resistor R 4 may be connected.
제2도는 1전원(정) 제어방식을 이용한 FET 스위치 회로이다. 이때문에, 제1도의접지전위에 상당하는 전위를 ＋B 접합의 저항분할에 의하여 멎고 이다.2 is a FET switch circuit using a single power supply (positive) control method. For this reason, the potential corresponding to the ground potential of FIG. 1 is subtracted by the resistance division of the + B junction.
이 경우 제어전압(Vc)을 제어하여 게이트전위를 a점 및 b점의 전위보다 높게하면 FET(Q)는 온으로, 또 낮게하면 차단된다.In this case, when the control voltage Vc is controlled to make the gate potential higher than the potentials of points a and b, the FET Q is turned on and is lowered when it is lowered.
즉 제어전압(Vc)은 ＋B 전위와 접지전위사이에서 제어하면 된다.That is, the control voltage Vc may be controlled between the + B potential and the ground potential.
이상과 같이 본 고안은 게이트와 출력과의 사이에 콘덴서를 접속하고 제어전압 인가단자와 상기 게이트간에 일방향성소자를 접속하여 상기 제어전압 인가단자로의 인가전압의 제어에 의하여 상기 게이트와 접지간의 임피이던스와 전압을 제어하도록 한 것이다. 이 때문에 게이트전위를 제어함으로써 FET가 온. 오프하여 스위칭(switching)하는 것은 물론, 온시에는 콘덴서에 의하여 왜곡이 방지되, 오프시에는 같은 콘덴서에 의하여 입력신호의 누화성분이 바이패스하게 되어 뮤우팅회로로서 매우 양호한 것으로 된다.As described above, the present invention provides an impedance between the gate and the ground by controlling a voltage applied to the control voltage applying terminal by connecting a capacitor between the gate and the output, and connecting a control voltage applying terminal and a one-way element between the gate. To control the voltage. For this reason, the FET is turned on by controlling the gate potential. As well as switching off, the distortion is prevented by the capacitor when it is turned on, while the crosstalk component of the input signal is bypassed by the same capacitor when it is turned off, which is very good as a muting circuit.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019800007499U KR810001365Y1 (en) | 1976-07-02 | 1980-11-21 | Fet switching circuit |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019760001631 | 1976-07-02 | ||
| KR2019800007499U KR810001365Y1 (en) | 1976-07-02 | 1980-11-21 | Fet switching circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019760001631 Division | 1976-07-02 | 1976-07-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR810001365Y1 true KR810001365Y1 (en) | 1981-09-30 |
Family
ID=26625908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019800007499U KR810001365Y1 (en) | 1976-07-02 | 1980-11-21 | Fet switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR810001365Y1 (en) |
-
1980
- 1980-11-21 KR KR2019800007499U patent/KR810001365Y1/en active
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