KR20240079626A - Display device and display panel - Google Patents

Abstract

Embodiments of the present disclosure relate to a display device and a display panel, and more specifically, to a plurality of subpixels disposed in an area where a plurality of gate lines and a plurality of data lines intersect, and a plurality of subpixels arranged through the plurality of gate lines. A plurality of gate in panel (GIP) circuits that supply scan signals to the plurality of subpixels, and a plurality of scan clocks corresponding to the plurality of scan signals to the plurality of gate in panel (GIP) circuits. A scan clock line, a first dummy scan clock line disposed adjacent to a first outermost scan clock line among the plurality of scan clock lines, and adjacent to a second outermost scan clock line among the plurality of scan clock lines. A display panel including a second dummy scan clock line may be provided.

Description

Display device and display panel {DISPLAY DEVICE AND DISPLAY PANEL}

Embodiments of the present disclosure relate to a display device and a display panel, and more specifically, to a display device and a display panel that can reduce image defects caused by coupling of clock lines.

Representative display devices that display images using digital data include liquid crystal display (LCD) devices using liquid crystals and organic light emitting display devices using organic light emitting diodes (OLED).

Among these display devices, organic light emitting display devices use light emitting diodes that emit light on their own, so they have advantages in terms of fast response speed, contrast ratio, luminous efficiency, brightness, and viewing angle. In this case, the light emitting diode may be implemented as an inorganic or organic material.

This organic light emitting display device includes a light emitting diode disposed in each of a plurality of subpixels arranged on a display panel, and each subpixel emits light by controlling the current flowing through the light emitting diode. The image can be displayed by controlling the luminance.

This display device includes a gate driving circuit and a data driving circuit that can drive the display panel.

Among these, the gate driving circuit may include a plurality of gate driving integrated circuits that output a plurality of scan signals. There is a problem of horizontal line defects occurring on the display panel due to coupling between clock lines applied to the gate driving integrated circuit. It can happen.

Accordingly, the inventors of the present disclosure have invented a display device and display panel that can reduce image defects caused by clock line coupling.

Embodiments of the present disclosure can provide a display device and display panel that can improve image quality by arranging a dummy clock line adjacent to a clock line where luminance deviation may occur due to coupling.

Additionally, embodiments of the present disclosure can provide a display device and display panel that can improve image quality by applying a clock that can improve luminance deviation through a dummy clock line.

Embodiments of the present disclosure include a plurality of subpixels disposed in an area where a plurality of gate lines and a plurality of data lines intersect, and a plurality of subpixels that supply a plurality of scan signals to the plurality of subpixels through the plurality of gate lines. A gate in panel (GIP) circuit, a plurality of scan clock lines that supply a plurality of scan clocks corresponding to the plurality of scan signals to the plurality of gate in panel (GIP) circuits, and a first of the plurality of scan clock lines. 1 A display panel including a first dummy scan clock line disposed adjacent to an outermost scan clock line and a second dummy scan clock line disposed adjacent to a second outermost scan clock line among the plurality of scan clock lines. can be provided.

Embodiments of the present disclosure include a display panel on which a plurality of subpixels are arranged, a gate driving circuit including a plurality of gate driving integrated circuits configured to supply a plurality of scan signals to the display panel through a plurality of gate lines, and a plurality of gate driving circuits. a data driving circuit configured to supply a plurality of data voltages to the display panel through a data line, a timing controller configured to control the gate driving circuit and the data driving circuit, and a plurality of scan signals corresponding to the plurality of scan signals. A plurality of scan clock lines that supply clocks to the plurality of gate driving integrated circuits, a first dummy scan clock line disposed adjacent to a first outermost scan clock line among the plurality of scan clock lines, and the plurality of scan clock lines. A display device including a second dummy scan clock line disposed adjacent to the second outermost scan clock line among clock lines can be provided.

According to embodiments of the present disclosure, there is an effect of reducing image defects caused by coupling of clock lines.

Additionally, according to embodiments of the present disclosure, there is an effect of improving image quality by arranging a dummy clock line adjacent to a clock line where luminance deviation may occur due to coupling.

Additionally, according to embodiments of the present disclosure, there is an effect of improving image quality by applying a dummy clock that can improve luminance deviation through a dummy clock line.

1 is a diagram illustrating a schematic configuration of a display device according to embodiments of the present disclosure.
Figure 2 is a system diagram of a display device according to embodiments of the present disclosure.
Figure 3 is an example diagram of a circuit forming a subpixel in a display device according to embodiments of the present disclosure.
FIG. 4 is a diagram showing an example of a display panel in which a gate driving circuit is implemented as a GIP type in a display device according to embodiments of the present disclosure.
FIG. 5 is a block diagram showing a schematic configuration of a gate driving integrated circuit in a display device according to embodiments of the present disclosure.
FIG. 6 is a diagram showing the configuration of a plurality of stage circuits constituting a gate driving circuit according to embodiments of the present disclosure.
FIG. 7 is a diagram showing an example of a stage circuit constituting a gate driving circuit in a display driving circuit according to embodiments of the present disclosure.
FIG. 8 is a diagram illustrating an example of a 16-phase scan clock line arranged in one gate driving integrated circuit.
Figure 9 is a diagram showing an example of a signal waveform diagram of a 16-phase scan clock applied through a 16-phase scan clock line.
FIG. 10 is a diagram illustrating the parasitic capacitance between scan clock lines and the resulting distortion of the scan signal in the structures of FIGS. 8 and 9 as an example.
FIG. 11 is a diagram showing an example of the arrangement of scan clock lines that can reduce parasitic capacitance in a display device according to embodiments of the present disclosure.
FIG. 12 is a diagram showing an example of a signal waveform according to the arrangement of the scan clock line of FIG. 11 in a display device according to embodiments of the present disclosure.
FIG. 13 is a diagram showing an example of a case in which horizontal line defects are improved by a dummy scan clock applied through a dummy scan clock line in a display device according to embodiments of the present disclosure.
FIG. 14 is a diagram showing an example of the arrangement of a 12-phase scan clock line that can reduce parasitic capacitance in a display device according to further embodiments of the present disclosure.

Hereinafter, some embodiments of the present disclosure will be described in detail with reference to illustrative drawings. In adding reference numerals to components in each drawing, identical components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, in describing the present disclosure, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description may be omitted. When “comprises,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless “only” is used. When a component is expressed in the singular, it can also include the plural, unless specifically stated otherwise.

Additionally, in describing the components of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term.

In the description of the positional relationship of components, when two or more components are described as being “connected,” “coupled,” or “connected,” the two or more components are directly “connected,” “coupled,” or “connected.” ", but it should be understood that two or more components and other components may be further "interposed" and "connected," "combined," or "connected." Here, other components may be included in one or more of two or more components that are “connected,” “coupled,” or “connected” to each other.

In the explanation of temporal flow relationships related to components, operation methods, production methods, etc., for example, temporal precedence relationships such as “after”, “after”, “after”, “before”, etc. Or, when a sequential relationship is described, non-continuous cases may be included unless “immediately” or “directly” is used.

On the other hand, when a numerical value or corresponding information (e.g. level, etc.) for a component is mentioned, even if there is no separate explicit description, the numerical value or corresponding information is related to various factors (e.g. process factors, internal or external shocks, It can be interpreted as including the error range that may occur due to noise, etc.).

1 is a diagram illustrating a schematic configuration of a display device according to embodiments of the present disclosure.

Referring to FIG. 1, the display device 100 according to an embodiment of the present specification has a plurality of gate lines (GL) and data lines (DL) connected and a plurality of subpixels (SP) arranged in a matrix form. A display panel 110, a gate driving circuit 120 that drives a plurality of gate lines (GL), a data driving circuit 130 that supplies a data voltage through a plurality of data lines (DL), and a gate driving circuit 120. and a timing controller 140 that controls the data driving circuit 130, and a power management circuit 150.

The display panel 110 is based on a scan signal transmitted from the gate driving circuit 120 through a plurality of gate lines (GL) and a data voltage transmitted from the data driving circuit 130 through a plurality of data lines (DL). Display the video.

In the case of a liquid crystal display, the display panel 110 includes a liquid crystal layer formed between two substrates, and operates in Twisted Nematic (TN) mode, Vertical Alignment (VA) mode, In Plane Switching (IPS) mode, and Fringe Field Switching (FFS) mode. ) mode, etc. may be operated in any known mode. On the other hand, in the case of an organic light emitting display, the display panel 110 may be implemented in a top emission method, a bottom emission method, or a dual emission method.

The display panel 110 may have a plurality of pixels arranged in a matrix form, and each pixel has subpixels (SP) of different colors, for example, white subpixel, red subpixel, green subpixel, and blue subpixel. It consists of, and each subpixel (SP) may be defined by a plurality of data lines (DL) and a plurality of gate lines (GL).

One subpixel (SP) is a thin film transistor (TFT) formed in the area where one data line (DL) and one gate line (GL) intersect, and a light emitting diode such as an organic light emitting diode that charges data voltage. It may include a storage capacitor that is electrically connected to the device and the light emitting device to maintain the voltage.

For example, if the display device 100 with a resolution of 2,160 By 3,840 data lines (DL) connected to the gate line (GL) and four subpixels (WRGB), a total of 3,840 A subpixel (SP) will be placed at each point where ) and the data line (DL) intersect.

The gate driving circuit 120 is controlled by the controller 140, which sequentially outputs scan signals to the plurality of gate lines (GL) disposed on the display panel 110 to determine the driving timing for the plurality of subpixels (SP). control.

In the display device 100 with a resolution of 2,160 can do. Alternatively, as in the case of sequentially outputting scan signals from the first gate line to the fourth gate line and then sequentially outputting the scan signals from the fifth gate line to the eighth gate line, four gate lines (GL) The case where scan signals are output sequentially in units is called 4-phase drive. In other words, the case of sequentially outputting scan signals for each N gate lines (GL) can be referred to as N-phase driving.

At this time, the gate driving circuit 120 may include one or more gate driving integrated circuits (GDIC), and depending on the driving method, it may be located only on one side of the display panel 110 or on both sides. It may be located. Alternatively, the gate driving circuit 120 may be built into the bezel area of the display panel 110 and implemented in the form of a gate in panel (GIP).

The data driving circuit 130 receives image data DATA from the timing controller 140 and converts the received image data DATA into an analog data voltage. Then, the data voltage is output to each data line (DL) according to the timing when the scan signal is applied through the gate line (GL), so that each subpixel (SP) connected to the data line (DL) corresponds to the data voltage. Displays a light emitting signal with a brightness of

Likewise, the data driving circuit 130 may include one or more source driving integrated circuits (SDICs), which may use a Tape Automated Bonding (TAB) method or a Chip On Glass (COG) method. ) may be connected to a bonding pad of the display panel 110 or may be placed directly on the display panel 110.

In some cases, each source driving integrated circuit (SDIC) may be integrated and disposed on the display panel 110. In addition, each source driving integrated circuit (SDIC) may be implemented in a COF (Chip On Film) method. In this case, each source driving integrated circuit (SDIC) is mounted on a circuit film and displays the display panel through the circuit film. It may be electrically connected to the data line (DL) of (110).

The timing controller 140 supplies various control signals to the gate driving circuit 120 and the data driving circuit 130, and controls the operations of the gate driving circuit 120 and the data driving circuit 130. That is, the timing controller 140 controls the gate driving circuit 120 to output a scan signal according to the timing implemented in each frame, and on the other hand, the externally received image data (DATA) is controlled by the data driving circuit 130. ) is delivered to.

At this time, the timing controller 140 includes video data (DATA), a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable; DE), a main clock (MCLK), etc. Various timing signals are received from the external host system 200.

The host system 200 may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

Accordingly, the timing controller 140 generates a control signal using various timing signals received from the host system 200 and transmits the control signal to the gate driving circuit 120 and the data driving circuit 130.

For example, the timing controller 140 uses a gate start pulse (GSP), a gate clock (GCLK), and a gate output enable signal (Gate Output Enable) to control the gate driving circuit 120. Outputs various gate control signals including ;GOE), etc. Here, the gate start pulse (GSP) controls the timing at which one or more gate driving integrated circuits (GDIC) constituting the gate driving circuit 120 start operating. Additionally, the gate clock (GCLK) is a signal commonly input to one or more gate driving integrated circuits (GDIC), and controls the shift timing of the scan signal. Additionally, the gate output enable signal (GOE) specifies timing information of one or more gate driver integrated circuits (GDIC).

In addition, the timing controller 140 uses a source start pulse (SSP), a source sampling clock (SCLK), and a source output enable signal (Source Output Enable signal) to control the data driving circuit 130. Outputs various data control signals including ;SOE), etc. Here, the source start pulse (SSP) controls the timing at which one or more source driving integrated circuits (SDICs) constituting the data driving circuit 130 start sampling data. The source sampling clock (SCLK) is a signal that controls the timing of sampling data in a source driving integrated circuit (SDIC). The source output enable signal (SOE) controls the output timing of the data driving circuit 130.

This display device 100 supplies various voltages or currents to the display panel 110, the gate driving circuit 120, and the data driving circuit 130, or includes a power management circuit 150 that controls the various voltages or currents to be supplied. may include.

The power management circuit 150 adjusts the direct current input voltage (Vin) supplied from the host system 200 to provide the power required to drive the display panel 100, the gate driving circuit 120, and the data driving circuit 130. Occurs.

Meanwhile, the subpixel SP is located at a point where the gate line GL and the data line DL intersect, and a light emitting device may be disposed in each subpixel SP. For example, an organic light emitting display device includes a light emitting device such as an organic light emitting diode in each subpixel (SP), and can display an image by controlling the current flowing through the light emitting device according to the data voltage.

This display device 100 may be of various types such as a liquid crystal display, organic light emitting display, and plasma display panel.

Figure 2 is an exemplary system diagram of a display device according to embodiments of the present disclosure.

Referring to FIG. 2, the display device 100 according to embodiments of the present disclosure has a source driving integrated circuit (SDIC) included in the data driving circuit 130 that uses COF among various methods (TAB, COG, COF, etc.). It is implemented in a (Chip On Film) method, and the gate driving circuit 120 is implemented in a GIP (Gate In Panel) form among various methods (TAB, COG, COF, GIP, etc.).

When the gate driving circuit 120 is implemented in the GIP form, a plurality of gate driving integrated circuits (GDICs) included in the gate driving circuit 120 may be formed directly in the bezel area of the display panel 110. At this time, the gate driving integrated circuit (GDIC) can receive various signals (clock, gate high voltage, gate low voltage, etc.) necessary for generating the scan signal through the gate driving related signal wires arranged in the bezel area.

Likewise, one or more source driving integrated circuits (SDICs) included in the data driving circuit 130 may each be mounted on the source film (SF), and one side of the source film (SF) is electrically connected to the display panel 110. can be connected Additionally, wires for electrically connecting the source driving integrated circuit (SDIC) and the display panel 110 may be disposed on the source film SF.

This display device 100 includes at least one source printed circuit board (SPCB), control components, and various electrical components for circuit connection between a plurality of source driving integrated circuits (SDICs) and other devices. It may include a control printed circuit board (CPCB) for mounting devices.

At this time, the other side of the source film (SF) on which the source driving integrated circuit (SDIC) is mounted may be connected to at least one source printed circuit board (SPCB). That is, one side of the source film SF on which the source driving integrated circuit (SDIC) is mounted may be electrically connected to the display panel 110, and the other side may be electrically connected to the source printed circuit board (SPCB).

A timing controller 140 and a power management circuit 150 may be mounted on a control printed circuit board (CPCB). The timing controller 140 may control the operations of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 150 may supply driving voltage or current to the display panel 110, the data driving circuit 130, and the gate driving circuit 120, and may control the supplied voltage or current.

At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be connected circuitously through at least one connecting member, for example, a flexible printed circuit (FPC). , it may be made of a flexible flat cable (FFC), etc. Additionally, at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated and implemented as one printed circuit board.

The display device 100 may further include a set board (Set Board) 170 electrically connected to a control printed circuit board (CPCB). At this time, the set board 170 may also be referred to as a power board. A main power management circuit 160 that manages the entire power of the display device 100 may be present in this set board 170. The main power management circuit 160 may be interconnected with the power management circuit 150.

In the case of the display device 100 configured as above, the driving voltage is generated in the set board 170 and transmitted to the power management circuit 150 in the control printed circuit board (CPCB). The power management circuit 150 transmits the driving voltage required for display driving or characteristic value sensing to the source printed circuit board (SPCB) through a flexible printed circuit (FPC) or flexible flat cable (FFC). The driving voltage delivered to the source printed circuit board (SPCB) is supplied to emit or sense a specific subpixel (SP) in the display panel 110 through the source driving integrated circuit (SDIC).

At this time, each subpixel SP arranged on the display panel 110 in the display device 100 may be composed of a light emitting element and a circuit element such as a driving transistor for driving the same.

The type and number of circuit elements constituting each subpixel (SP) can be determined in various ways depending on the provided function and design method.

Figure 3 is an example diagram of a circuit forming a subpixel in a display device according to embodiments of the present disclosure.

Referring to FIG. 3, in the display device 100 according to embodiments of the present disclosure, the subpixel SP may include one or more transistors and a capacitor, and a light emitting device may be disposed.

For example, the subpixel (SP) may include a driving transistor (DRT), a switching transistor (SWT), a sensing transistor (SENT), a storage capacitor (Cst), and a light emitting diode (ED).

The driving transistor DRT has a first node N1, a second node N2, and a third node N3. The first node (N1) of the driving transistor (DRT) may be a gate node to which the data voltage (Vdata) is applied from the data driving circuit 130 through the data line (DL) when the switching transistor (SWT) is turned on. there is.

The second node N2 of the driving transistor DRT may be electrically connected to the anode electrode of the light emitting diode ED and may be a source node or a drain node.

The third node N3 of the driving transistor DRT is electrically connected to the driving voltage line DVL to which the subpixel driving voltage EVDD is applied, and may be a drain node or a source node.

At this time, during the display driving period, the subpixel driving voltage (EVDD) required to display the image may be supplied through the driving voltage line (DVL). For example, the subpixel driving voltage (EVDD) required to display the image is 27V. It can be.

The switching transistor (SWT) is electrically connected between the first node (N1) of the driving transistor (DRT) and the data line (DL), and the gate line (GL) is connected to the gate node and supplied through the gate line (GL). It operates according to the first scan signal (SCAN1). In addition, when the switching transistor (SWT) is turned on, the operation of the driving transistor (DRT) is controlled by transferring the data voltage (Vdata) supplied through the data line (DL) to the gate node of the driving transistor (DRT). I do it.

The sensing transistor (SENT) is electrically connected between the second node (N2) of the driving transistor (DRT) and the reference voltage line (RVL), and is scanned according to the second scan signal (SCAN2) supplied through the gate line (GL). It works. When the sensing transistor (SENT) is turned on, the reference voltage (Vref) supplied through the reference voltage line (RVL) is transmitted to the second node (N2) of the driving transistor (DRT).

That is, by controlling the switching transistor (SWT) and the sensing transistor (SENT), the first node (N1) voltage and the second node (N2) voltage of the driving transistor (DRT) are controlled, which causes the light emitting diode (ED) Ensure that current to drive is supplied.

The gate nodes of the switching transistor (SWT) and the sensing transistor (SENT) may be connected together to one gate line (GL) or may be connected to different gate lines (GL). Here, a structure in which the switching transistor (SWT) and the sensing transistor (SENT) are connected to different gate lines (GL) is shown as an example. In this case, the first scan signal (SCAN1) transmitted through different gate lines (GL) is shown as an example. ) and the second scan signal (SCAN2) can be used to independently control the switching transistor (SWT) and the sensing transistor (SENT).

On the other hand, when the switching transistor (SWT) and the sensing transistor (SENT) are connected to one gate line (GL), the first scan signal (SCAN1) or the second scan signal (SCAN2) transmitted through one gate line (GL) ), the switching transistor (SWT) and the sensing transistor (SENT) can be controlled simultaneously, and the aperture ratio of the subpixel (SP) can be increased.

Meanwhile, the transistor disposed in the subpixel SP may be made of not only an n-type transistor but also a p-type transistor, and here, the case of being made of an n-type transistor is shown as an example.

The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT and maintains the data voltage Vdata for one frame.

This storage capacitor Cst may be connected between the first node N1 and the third node N3 of the driving transistor DRT depending on the type of the driving transistor DRT. The anode electrode of the light emitting diode (ED) may be electrically connected to the second node (N2) of the driving transistor (DRT), and the base voltage (EVSS) may be applied to the cathode electrode of the light emitting diode (ED). .

Here, the base voltage (EVSS) may be ground voltage or a voltage higher or lower than the ground voltage. Additionally, the electromotive voltage (EVSS) may vary depending on the driving state. For example, the base voltage (EVSS) at the time of display driving and the base voltage (EVSS) at the time of sensing driving may be set differently.

The switching transistor (SWT) and sensing transistor (SENT) can be said to be scan transistors controlled through scan signals (SCAN1 and SCAN2).

The structure of this subpixel (SP) may further include one or more transistors, or in some cases, may further include one or more capacitors.

In order to effectively sense the characteristic value of the driving transistor (DRT), for example, threshold voltage or mobility, the display device 100 of the present disclosure includes a storage capacitor (Cst) in the characteristic value sensing section of the driving transistor (DRT). A method of measuring the current flowing by the charging voltage can be used, which is called current sensing.

In other words, by measuring the current flowing by the voltage charged in the storage capacitor (Cst) in the characteristic value sensing section of the driving transistor (DRT), the characteristic value or change in characteristic value of the driving transistor (DRT) in the subpixel (SP) is detected. You can find out.

At this time, the reference voltage line (RVL) not only plays the role of transmitting the reference voltage (Vref), but also serves as a sensing line for sensing the characteristic value of the driving transistor (DRT) in the subpixel. ) may also be called a sensing line or sensing channel.

More specifically, the characteristic value or change in characteristic value of the driving transistor (DRT) may correspond to the difference between the gate node voltage and the source node voltage of the driving transistor (DRT).

This characteristic value compensation of the driving transistor (DRT) is performed using an internal compensation or external compensation circuit that senses and compensates the characteristic value of the driving transistor (DRT) inside the subpixel (SP) without using any additional external configuration. It can be performed through external compensation that senses and compensates for the characteristic value of the driving transistor (DRT).

At this time, external compensation may be made before shipping the display device 100, and internal compensation may be made after shipping the display device 100. However, internal compensation and external compensation may be made together even after shipping the display device 100.

FIG. 4 is a diagram showing an example of a display panel in which a gate driving circuit is implemented as a GIP type in a display device according to embodiments of the present disclosure.

Referring to FIG. 4, in the display device 100 according to embodiments of the present disclosure, 2n gate lines (GL(1) to GL) are formed in the display area (A/A) for displaying an image on the display panel 110. (2n), n is a natural number) can be placed.

At this time, the gate driving circuit 120 is embedded and disposed in a non-display area corresponding to the outside of the display area (A/A) of the display panel 110, and has 2n gate lines (GL(1) to GL(2n). )) and may include 2n GIP circuits (GIPC) corresponding to each other.

Accordingly, 2n GIP circuits (GIPC) can output scan signals (SCAN) through 2n gate lines (GL(1) to GL(2n)).

In this way, when the gate driving circuit 120 is implemented as a GIP type, there is no need to manufacture a separate integrated circuit with a gate driving function and bond it to the display panel 110, thereby reducing the number of integrated circuits. The process of connecting the integrated circuit to the display panel 110 can be omitted. Additionally, the size of the bezel area for bonding the integrated circuit in the display panel 110 can be reduced.

In order to distinguish 2n GIP circuits (GIPC) from each other and identify their correspondence with 2n gate lines (GL(1) ~ GL(2n)), GIPC(1), GIPC(2),... It can be written as GIPC(2n).

Here, the case where 2n GIP circuits (GIPC(1) to GIPC(2n) are divided and arranged on both sides of the display area (A/A) is shown. For example, 2n GIP circuits (GIPC(1) ~ GIPC(2n)), the odd-numbered GIP circuit (GIPC(1), GIPC(3), …, GIPC(2n-1)) is the odd-numbered gate line (GL(1), GL(3), …, GL (2n-1)) can be driven among the even-numbered GIP circuits (GIPC(2), GIPC(4), …, GIPC(2n)). Can drive the even-numbered gate lines (GL(2), GL(4), …, GL(2n)).

Alternatively, 2n GIP circuits (GIPC(1) to GIPC(2n)) may be disposed on only one side of the display area (A/A).

In the non-display area corresponding to the outside of the display area (A/A) of the display panel 110, a plurality of clock lines are provided to transmit the gate clock required for generating and outputting the scan signal (SCAN) to the gate driving circuit 120. (CL) may be placed.

FIG. 5 is a block diagram showing a schematic configuration of a gate driving integrated circuit in a display device according to embodiments of the present disclosure.

Referring to FIG. 5 , in the display device 100 according to embodiments of the present disclosure, one data driving integrated circuit may include a shift register 122 and a buffer circuit 124.

The gate driving integrated circuit starts operating according to the gate start pulse (GSP) and outputs a scan signal (SCAN) according to the gate clock (GCLK). The scan signal (SCAN) output from the gate driving integrated circuit is sequentially shifted and sequentially supplied through the gate line (GL).

The buffer circuit 124 has two nodes (Q, QB) that are important for the gate driving state and may include a pull-up transistor (TU) and a pull-down transistor (TD). Here, the gate node of the pull-up transistor (TU) may correspond to the Q node, and the gate node of the pull-down transistor (TD) may correspond to the QB node.

The shift register 122 may also be referred to as a shift logic circuit, and may be used to generate a scan signal (SCAN) in synchronization with the gate clock (GCLK).

The shift register 122 can control the Q node and QB node connected to the buffer circuit 124 so that the buffer circuit 124 can output a scan signal (SCAN), and for this purpose, it includes a plurality of transistors. can do.

The shift register 122 begins to generate a scan signal (SCAN), and the output of the shift register 122 is sequentially turned on according to the gate clock (GCLK). That is, by controlling the output time of the shift register 122 using the gate clock GCLK, the logic state that determines the on/off of the gate line GL can be sequentially transmitted to the buffer circuit 124.

Depending on the shift register 122, the voltage states of each of the Q node and QB node of the buffer circuit 124 may vary. Accordingly, the buffer circuit 124 may be a signal having a voltage (e.g., a high level voltage or a low level voltage) for turning on the corresponding gate line (GL), for example, the gate high voltage (VGH). ) to the corresponding gate line (GL), or a voltage (e.g., low level voltage or high level voltage) to turn off the corresponding gate line (GL), for example, the gate low voltage (VGL) (which may be a base voltage (VSS)) can be output to the corresponding gate line (GL).

Meanwhile, one gate driving integrated circuit may further include a level shifter in addition to the shift register 122 and the buffer circuit 124.

At this time, the shift register 122 and the buffer circuit 124 constituting the gate driving integrated circuit may be connected in various structures.

FIG. 6 is a diagram showing the configuration of a plurality of stage circuits constituting a gate driving circuit according to embodiments of the present disclosure.

Referring to FIG. 6, the gate driving circuit 120 according to another embodiment of the present specification includes a first stage circuit (ST(1)) to a k-th stage circuit (ST(k)) (k is a positive integer), It includes a gate driving voltage line 131, a clock line 132, a line sensing signal line 133, a reset signal line 134, and a panel on signal line 135.

Here, each stage circuit (ST) may correspond to a gate driving integrated circuit (GDIC) or a GIP circuit constituting the gate driving circuit 120.

In addition, the gate driving circuit 120 includes a front-stage dummy stage circuit DST1 disposed before the first stage circuit ST(1) and a rear-stage dummy stage circuit disposed after the k-th stage circuit ST(k). (DST2) may be further included.

The gate driving voltage line 131 connects the high potential gate voltage (GVDD) and the low potential gate voltage (GVSS) supplied from the power management circuit 150 to first to k stage circuits (ST(1) to ST(k). ), are supplied to the front-end dummy stage circuit (DST1) and the rear-end dummy stage circuit (DST2), respectively.

The gate driving voltage line 131 includes a plurality of high-potential gate voltage lines supplying a plurality of high-potential gate voltages having different voltage levels and a plurality of low-potential gate voltage lines supplying a plurality of low-potential gate voltages having different voltage levels. It may include a gate voltage line.

For example, the gate driving voltage line 131 supplies a first high-potential gate voltage (GVDD1), a second high-potential gate voltage (GVDD2), and a third high-potential gate voltage (GVDD3) each having different voltage levels. Three high-potential gate voltage lines and three low-potential gate voltage lines each supplying a first low-potential gate voltage (GVSS1), a second low-potential gate voltage (GVSS2), and a third low-potential gate voltage (GVSS3) having different voltage levels. It may include a potential gate voltage line. However, this is just one example, and the number of lines included in the gate driving voltage line 131 may vary depending on the embodiment.

The clock line 132 connects a plurality of clocks (CLKs) supplied from the timing controller 140, such as a carry clock or a gate clock, to the first to k-th stage circuits (ST(1) to ST(k)) and the front end dummy. It is supplied to the stage circuit (DST1) and the subsequent dummy stage circuit (DST2), respectively.

The line sensing signal line 133 supplies the line sensing signal (LSP) supplied from the timing controller 140 to the first to k-th stage circuits (ST(1) to ST(k)). Optionally, the line sensing signal line 133 may be additionally connected to the front-end dummy stage circuit (DST1).

The reset signal line 134 transmits the reset signal (RESET) supplied from the timing controller 140 to the first to k-th stage circuits (ST(1) to ST(k)), the front-end dummy stage circuit (DST1), and the rear-stage dummy stage circuit (ST(1) to ST(k)). Each is supplied to the stage circuit (DST2).

The panel on signal line 135 transmits the panel on signal (POS) supplied from the timing controller 140 to the first to kth stage circuits (ST(1) to ST(k)), the previous dummy stage circuit (DST1), Each is supplied to the rear dummy stage circuit (DST2).

In addition, in addition to the lines 131, 132, 133, 134, and 135 shown here, the lines for supplying other signals are the first to k stage circuits (ST(1) to ST(k)) and the front dummy stage. It can be additionally connected to the circuit (DST1) and the rear dummy stage circuit (DST2). For example, a line for supplying the gate start pulse (GSP) to the front-end dummy stage circuit (DST1) may be additionally connected to the front-end dummy stage circuit (DST1).

The front-end dummy stage circuit (DST1) outputs the front-end carry signal (Cd1) in response to the input of the gate start pulse (GSP) supplied from the timing controller 140.

The front-end carry signal Cd1 may be supplied to any one of the first to k-th stage circuits ST(1) to ST(k).

The rear-stage dummy stage circuit (DST2) outputs a rear-stage carry signal (Cd2). The rear-end carry signal Cd2 may be supplied to any one of the first to k-th stage circuits ST(1) to ST(k).

The first to kth stage circuits (ST(1) to ST(k)) may be connected to each other in a cascaded or cascaded manner.

The first to kth stage circuits (ST(1) to ST(k)) each output n (n is a positive integer) scan signals (SCAN) and one carry signal (C). That is, an arbitrary stage circuit outputs the first to nth scan signals and one carry signal (C).

For example, each stage circuit outputs four scan signals (SCAN) and one carry signal (C). For example, the first stage circuit (ST(1)) includes a first scan signal (SCAN(1)), a second scan signal (SCAN(2)), a third scan signal (SCAN(3)), and a fourth scan signal ( SCAN(4)) and the first carry signal (C(1)) are output, and the second stage circuit (ST(2)) outputs the fifth scan signal (SCAN(5)) and the sixth scan signal (SCAN(6) )), a seventh scan signal (SCAN(7)), an eighth scan signal (SCAN(8)), and a second carry signal (C(2)) are output. Therefore, in this example j is 4.

The number of scan signals output from the first to kth stage circuits (ST(1) to ST(k)) corresponds to the number (GN) of gate lines (GL) disposed on the display panel 110. As described above, k stage circuits each output n scan signals. Therefore, the relationship n×k=GN is established.

For example, when n=4, the number of stage circuits (k) is 1/4 of the number of gate lines (GL) (GN). However, the number of scan signals output by each stage circuit is not limited to this. That is, in the embodiment of the present disclosure, each stage circuit may output one, two, or three scan signals, or may output five or more scan signals. The number of stage circuits may vary depending on the number of scan signals output by each stage circuit.

The scan signal (SCAN) output from the first to k stage circuits (ST(1) to ST(k)) may be a scan signal for sensing the threshold voltage of the driving transistor (DRT) or a gate signal for image display. there is. Additionally, the carry signal C output from the first to kth stage circuits (ST(1) to ST(k)) may be supplied to different stage circuits. Here, the carry signal supplied to any stage circuit from the previous stage circuit is referred to as the previous stage carry signal, and the carry signal supplied from the subsequent stage circuit is referred to as the subsequent carry signal.

FIG. 7 is a diagram showing an example of a stage circuit constituting a gate driving circuit in a display driving circuit according to embodiments of the present disclosure.

Referring to FIG. 7, the stage circuit according to embodiments of the present disclosure includes an M node, a Q node, and a QB node, and a line selection unit 502, a Q node control unit 504, and a Q node stabilization unit 506. , an inverter unit 508, a QB node stabilization unit 510, a carry signal output unit 512, and a scan signal output unit 514.

The line selection unit 502 charges the M node based on the front-end carry signal (C(k-2)) in response to the input of the line sensing signal (LSP). Additionally, the line selection unit 502 charges the Q node to the level of the first high-potential gate voltage GVDD1 based on the charging voltage of the M node in response to the input of the reset signal RESET. Additionally, the line selection unit 502 discharges or resets the Q node to the level of the third low-potential gate voltage GVSS3 in response to the input of the panel on signal POS.

The line selection unit 502 includes 11th to 17th transistors (T11 to T17) and a precharging capacitor (CA).

The 11th transistor T11 and the 12th transistor T12 are connected between the M node and the first high-potential gate voltage line transmitting the first high-potential gate voltage GVDD1. Additionally, the 11th transistor (T11) and the 12th transistor (T12) are connected to each other in series.

The eleventh transistor T11 outputs the front-end carry signal C(k-2) to the first connection node NC1 in response to the input of the line sensing signal LSP.

The twelfth transistor T12 electrically connects the first connection node NC1 to the M node in response to the input of the line sensing signal LSP. For example, when a high voltage line sensing signal (LSP) is input to the 11th transistor (T11) and the 12th transistor (T12), the 11th transistor (T11) and the 12th transistor (T12) are turned on simultaneously and the M node becomes the first It is charged to the high potential gate voltage (GVDD1) level.

The thirteenth transistor T13 is turned on when the voltage level of the M node is high level and supplies the first high potential gate voltage GVDD1 to the first connection node NC1. When the first high-potential gate voltage GVDD1 is supplied to the first connection node NC1, the voltage difference between the gate voltage of the 11th transistor T11 and the first connection node NC1 increases.

Therefore, when the low level line sensing signal (LSP) is input to the gate node of the 11th transistor (T11) and the 11th transistor (T11) is turned off, the gate voltage of the 11th transistor (T11) and the first connection node Due to the voltage difference between (NC1), the 11th transistor (T11) may be maintained in a completely turned-off state. Accordingly, current leakage of the 11th transistor T11 and the resulting voltage drop of the M node are prevented, and the voltage of the M node can be maintained stably.

The precharging capacitor (CA) is connected between the first high-potential gate voltage line delivering the first high-potential gate voltage (GVDD1) and the M node, and is connected between the first high-potential gate voltage (GVDD1) and the voltage charged at the M node. Save the difference.

When the 11th transistor (T11), the 12th transistor (T12), and the 13th transistor (T13) are turned on, the precharging capacitor (CA) stores the high voltage of the front-end carry signal (C(k-2)). When the 11th transistor (T11), the 12th transistor (T12), and the 13th transistor (T13) are turned off, the precharging capacitor (CA) maintains the voltage of the M node for a certain time with the stored voltage.

The 14th transistor T14 and the 15th transistor T15 are connected between the Q node and the first high-potential gate voltage line delivering the first high-potential gate voltage GVDD1. The fourteenth transistor T14 and the fifteenth transistor T15 are connected in series.

The fourteenth transistor T14 and the fifteenth transistor T15 charge the Q node with the first high potential gate voltage GVDD1 in response to the voltage of the M node and the input of the reset signal RESET.

The fourteenth transistor T14 is turned on when the voltage of the M node is at a high level and transfers the first high potential gate voltage GVDD1 to the shared node of the fourteenth transistor T14 and the fifteenth transistor T15.

The fifteenth transistor T15 is turned on by the high-level reset signal RESET and supplies the voltage of the shared node to the Q node. Therefore, when the 14th transistor T14 and the 15th transistor T15 are turned on at the same time, the Q node is charged with the first high potential gate voltage GVDD1.

The 16th transistor T16 and the 17th transistor T17 are connected between the Q node and the third low-potential gate voltage line that transmits the third low-potential gate voltage GVSS3. The 16th transistor (T16) and the 17th transistor (T17) are connected in series with each other.

The 16th transistor (T16) and the 17th transistor (T17) discharge the Q node to the third low-potential gate voltage (GVSS3) in response to the input of the panel on signal (POS). Discharging the Q node to the third low-potential gate voltage (GVSS3) can also be expressed as the Q node being reset.

The seventeenth transistor T17 is turned on by the input of the high-level panel on signal POS and supplies the third low-potential gate voltage GVSS3 to the QH node.

The sixteenth transistor T16 is turned on according to the input of the high level panel on signal (POS) and electrically connects the Q node and the QH node. Therefore, when the 16th transistor T16 and the 17th transistor T17 are turned on at the same time, the Q node is discharged or reset to the third low-potential gate voltage GVSS3.

The Q node control unit 504 charges the Q node to the level of the first high potential gate voltage (GVDD1) in response to the input of the front-end carry signal (C(k-2)) and charges the rear-end carry signal (C(k+2) In response to the input of )), the Q node is discharged to the level of the third low-potential gate voltage (GVSS3).

The Q node control unit 504 includes 21st to 28th transistors (T21 to T28).

The 21st transistor T21 and the 22nd transistor T22 are connected between the Q node and the first high potential gate voltage line delivering the first high potential gate voltage GVDD1. The 21st transistor (T21) and the 22nd transistor (T22) are connected to each other in series.

The 21st transistor T21 and the 22nd transistor T22 charge the Q node to the level of the first high potential gate voltage GVDD1 in response to the input of the front-end carry signal C(k-2).

The 21st transistor T21 is turned on according to the input of the previous carry signal C(k-2) and supplies the first high potential gate voltage GVDD1 to the second connection node NC2.

The 22nd transistor T22 is turned on according to the input of the previous carry signal C(k-2) and electrically connects the second connection node NC2 and the Q node. Accordingly, when the 21st transistor T21 and the 22nd transistor T22 are turned on simultaneously, the first high potential gate voltage GVDD1 is supplied to the Q node.

The 25th transistor T25 and the 26th transistor T26 are connected to a third high potential gate voltage line that transmits the third high potential gate voltage GVDD3. The 25th transistor T25 and the 26th transistor T26 supply the third high potential gate voltage GVDD3 to the second connection node NC2 in response to the third high potential gate voltage GVDD3.

The 25th transistor (T25) and the 26th transistor (T26) are simultaneously turned on by the third high-potential gate voltage (GVDD3) to constantly apply the third high-potential gate voltage (GVDD3) to the second connection node (NC2). By supplying , the voltage difference between the gate voltage of the 21st transistor (T21) and the second connection node (NC2) is increased. Therefore, when the low-level front-end carry signal (C(k-2)) is input to the gate node of the 21st transistor (T21) and the 21st transistor (T21) is turned off, the gate voltage of the 21st transistor (T21) Due to the voltage difference between and the second connection node NC2, the 21st transistor T21 may be maintained in a completely turned-off state.

Accordingly, current leakage of the 21st transistor T21 and the resulting voltage drop of the Q node can be prevented, and the voltage of the Q node can be maintained stably.

For example, when the threshold voltage of the 21st transistor (T21) is negative (-), the gate-source voltage (Vgs) of the 21st transistor (T21) is the third high potential gate voltage (GVDD3) supplied to the drain electrode. ) is maintained as negative polarity (-).

Therefore, when the low-level front-end carry signal C(k-2) is input to the gate node of the 21st transistor T21 and the 21st transistor T21 is turned off, the 21st transistor T21 is completely turned on. -It is maintained in the off state to prevent leakage current.

Here, the third high-potential gate voltage (GVDD3) is set to a voltage level lower than the first high-potential gate voltage (GVDD1).

The 23rd transistor T23 and the 24th transistor T24 are connected between the Q node and the third low-potential gate voltage line transmitting the third low-potential gate voltage GVSS3. The 23rd transistor (T23) and the 24th transistor (T24) are connected to each other in series.

The 23rd transistor T23 and the 24th transistor T24 discharge the Q node and QH node to the level of the third low-potential gate voltage GVSS3 in response to the input of the rear carry signal C(k+2).

The 24th transistor T24 is turned on according to the input of the rear carry signal C(k+2) to discharge the QH node to the level of the third low-potential gate voltage GVSS3. The 23rd transistor T23 is turned on according to the input of the rear carry signal C(k+2) and electrically connects the Q node and the QH node. Accordingly, when the 23rd transistor T23 and the 24th transistor T24 are turned on simultaneously, the Q node and QH node are discharged or reset to the level of the third low-potential gate voltage GVSS3, respectively.

The 27th transistor (T27) and the 28th transistor (T28) are between the first high-potential gate voltage line and the Q node, which transmits the first high-potential gate voltage (GVDD1), and transmit the first high-potential gate voltage (GVDD1). is connected between the first high potential gate voltage line and the QH node. The 27th transistor (T27) and the 28th transistor (T28) are connected to each other in series.

The 27th transistor T27 and the 28th transistor T28 supply the first high potential gate voltage GVDD1 to the QH node in response to the voltage of the Q node. The 27th transistor T27 is turned on when the voltage of the Q node is at a high level and supplies the first high potential gate voltage GVDD1 to the shared node of the 27th transistor T27 and the 28th transistor T28.

The 28th transistor T28 is turned on when the voltage of the Q node is at a high level and electrically connects the shared node and the QH node. Accordingly, the 27th transistor T27 and the 28th transistor T28 are simultaneously turned on when the voltage of the Q node is at a high level and supply the first high potential gate voltage GVDD1 to the QH node.

When the first high-potential gate voltage GVDD1 is supplied to the QH node, the voltage difference between the gate node of the 23rd transistor T23 and the QH node increases. Therefore, when the low-level rear carry signal (C(k+2)) is input to the gate node of the 23rd transistor (T23) and the 23rd transistor (T23) is turned off, the gate voltage of the 23rd transistor (T23) Due to the voltage difference between the and QH nodes, the 23rd transistor T23 may be maintained in a completely turned-off state. Accordingly, current leakage of the 23rd transistor T23 and the resulting voltage drop of the Q node are prevented, and the voltage of the Q node can be maintained stably.

The Q node stabilizing unit 506 discharges the Q node and QH node to the level of the third low-potential gate voltage GVSS3 in response to the voltage of the QB node. The Q node stabilization unit 506 includes a 31st transistor (T31) and a 32nd transistor (T32). The 31st transistor T31 and the 32nd transistor T32 are connected between the Q node and the third low-potential gate voltage line that transmits the third low-potential gate voltage GVSS3. The 31st transistor (T31) and the 32nd transistor (T32) are connected to each other in series.

The 31st transistor T31 and the 32nd transistor T32 discharge the Q node and QH node to the level of the third low-potential gate voltage GVSS3 in response to the voltage of the QB node. The 32nd transistor T32 is turned on when the voltage of the QB node is at a high level and supplies the third low-potential gate voltage GVSS3 to the shared node of the 31st transistor T31 and the 32nd transistor T32.

The 31st transistor T31 is turned on when the voltage of the QB node is at a high level and electrically connects the Q node and the QH node. Therefore, when the 31st transistor (T31) and the 32nd transistor (T32) are simultaneously turned on in response to the voltage of the QB node, the Q node and QH node are discharged or reset to the level of the third low-potential gate voltage (GVSS3), respectively. .

The inverter unit 508 changes the voltage level of the QB node according to the voltage level of the Q node. The inverter unit 508 includes 41st to 45th transistors (T41 to T45).

The 42nd transistor T42 and the 43rd transistor T43 are connected between the second high potential gate voltage line transmitting the second high potential gate voltage GVDD2 and the third connection node NC3. The 42nd transistor (T42) and the 43rd transistor (T43) are connected to each other in series.

The 42nd transistor T42 and the 43rd transistor T43 supply the second high potential gate voltage GVDD2 to the third connection node NC3 in response to the second high potential gate voltage GVDD2. The 42nd transistor T42 is turned on by the second high-potential gate voltage GVDD2 and supplies the second high-potential gate voltage GVDD2 to the shared node of the 42nd transistor T42 and the 43rd transistor T43. .

The 43rd transistor T43 is turned on by the second high potential gate voltage GVDD2 to electrically connect the shared node of the 42nd transistor T42 and the 43rd transistor T43 to the third connection node NC3. do. Therefore, when the 42nd transistor (T42) and the 43rd transistor (T43) are simultaneously turned on by the second high-potential gate voltage (GVDD2), the third connection node (NC3) is at the level of the second high-potential gate voltage (GVDD2). is charged with

The 44th transistor T44 is connected between the third connection node NC3 and the second low-potential gate voltage line that transmits the second low-potential gate voltage GVSS2.

The 44th transistor T44 supplies the second low-potential gate voltage GVSS2 to the third connection node NC3 in response to the voltage of the Q node. The 44th transistor T44 is turned on when the voltage of the Q node is at a high level to discharge or reset the third connection node NC3 to the second low-potential gate voltage GVSS2.

The 41st transistor T41 is connected between the QB node and the second high potential gate voltage line delivering the second high potential gate voltage GVDD2.

The 41st transistor T41 supplies the second high potential gate voltage GVDD2 to the QB node in response to the voltage of the third connection node NC3. The 41st transistor T41 is turned on when the voltage of the third connection node NC3 is at a high level and charges the QB node to the level of the second high potential gate voltage GVDD2.

The 45th transistor T45 is connected between the QB node and the third low-potential gate voltage line delivering the third low-potential gate voltage GVSS3.

The 45th transistor (T45) supplies a third low-potential voltage (GVSS3) to the QB node in response to the voltage of the Q node. The 45th transistor T45 is turned on when the voltage of the Q node is at a high level to discharge or reset the QB node to the third low-potential gate voltage GVSS3 level.

The QB node stabilizing unit 510 adjusts the QB node to the third low-potential gate voltage (GVSS3) in response to the input of the rear-end carry signal (C(k-2)), the input of the reset signal (RESET), and the charging voltage of the M node. Discharge to the level of The QB node stabilization unit 510 includes 51st to 53rd transistors (T51 to T53).

The 51st transistor T51 is connected between the QB node and the third low-potential gate voltage line delivering the third low-potential gate voltage GVSS3.

The 51st transistor T51 supplies the third low-potential gate voltage GVSS3 to the QB node in response to the input of the rear carry signal C(k-2).

The 52nd transistor T52 and the 53rd transistor T53 are connected between the QB node and the third low-potential gate voltage line transmitting the third low-potential gate voltage GVSS3. The 52nd transistor (T52) and the 53rd transistor (T53) are connected in series with each other.

The 52nd transistor T52 and the 53rd transistor T53 discharge the QB node to the level of the third low-potential gate voltage GVSS3 in response to the input of the reset signal RESET and the charging voltage of the M node.

The 53rd transistor T53 is turned on when the voltage of the M node is at a high level and supplies the third low-potential gate voltage GVSS3 to the shared node of the 52nd transistor T52 and the 53rd transistor T53.

The 52nd transistor T52 is turned on by the input of the reset signal RESET and electrically connects the shared node and the QB node of the 52nd transistor T52 and the 53rd transistor T53. Therefore, when the reset signal (RESET) is input while the voltage of the M node is at a high level, the 52nd transistor (T52) and the 53rd transistor (T53) are turned on simultaneously, so that the QB node is at the third low-potential gate voltage (GVSS2) level. is discharged or reset.

The carry signal output unit 512 outputs a carry signal (C) based on the voltage level of the carry clock (CRCLK(k)) or the level of the third low-potential gate voltage (GVSS3) according to the voltage level of the Q node or the voltage level of the QB node. (k)) is output.

The carry signal output unit 512 includes a 61st transistor (T61), a 62nd transistor (T62), and a boosting capacitor (CC).

The 61st transistor T61 is connected between the clock line transmitting the carry clock CRCLK(k) and the first output node NO1. A boosting capacitor (CC) is connected between the gate node and the source node of the 61st transistor (T61).

The 61st transistor T61 outputs a high-level carry signal C(k) through the first output node NO1 based on the carry clock CRCLK(k) in response to the voltage of the Q node. The 61st transistor T61 is turned on when the voltage of the Q node is at a high level and supplies the high level carry clock CRCLK(k) to the first output node NO1. Accordingly, a high-level carry signal (C(k)) is output.

When the carry signal (C(k)) is output, the boosting capacitor (CC) is synchronized with the high-level carry clock (CRCLK(k)) to lower the voltage of the Q node to the level of the first high-potential gate voltage (GVDD1). Bootstrap to a high boosting voltage level. When the voltage of the Q node is bootstrapped, the high-level carry clock (CRCLK(k)) can be output as the carry signal (C(k)) quickly and without distortion.

The 62nd transistor T62 is connected between the first output node NO1 and the third low-potential gate voltage line transmitting the third low-potential gate voltage GVSS3.

The 62nd transistor T62 outputs a low-level carry signal C(k) through the first output node NO1 based on the third low-potential gate voltage GVSS3 in response to the voltage of the QB node. The 62nd transistor T62 is turned on when the voltage of the QB node is at a high level and supplies the third low potential voltage GVSS3 to the first output node NO1. Accordingly, a low-level carry signal (C(k)) is output.

The scan signal output unit 514 generates a plurality of scan clocks (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3) according to the voltage level of the Q node or the voltage level of the QB node. A plurality of scan signals (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) based on the voltage level of )) or the level of the first low-potential gate voltage (GVSS1) outputs. (i is a positive integer)

Here, the multiple scan clocks (SCCLK(i), SCCLK(i+1), SCCLK(i+2), and SCCLK(i+3)) are signals corresponding to the gate clock (GCLK), and are used in the gate driving integrated circuit. It may vary depending on the number of scan signals (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) output from (GDIC).

The scan signal output unit 514 includes 71st to 78th transistors (T71 to T78) and boosting capacitors (CS1, CS2, CS3, and CS4).

The 71st transistor (T71), the 73rd transistor (T73), the 75th transistor (T75), and the 77th transistor (T77) respectively use scan clocks (SCCLK(i), SCCLK(i+1), and SCCLK(i+2). , is connected between a clock line delivering SCCLK(i+3)) and the second to fifth output nodes (NO2 to NO5).

Boosting capacitors CS1, CS2, CS3, and CS4 are connected between the gate node and source node of the 71st transistor (T71), 73rd transistor (T73), 75th transistor (T75), and 77th transistor (T77), respectively. .

The 71st transistor (T71), 73rd transistor (T73), 75th transistor (T75), and 77th transistor (T77) each generate scan clocks (SCCLK(i), SCCLK(i+1) in response to the voltage of the Q node. , SCCLK(i+2), SCCLK(i+3)), the second output node (NO2), the third output node (NO3), the fourth output node (NO4), and the fifth output node (NO5). Through it, high-level scan signals (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) are output.

The 71st transistor (T71), the 73rd transistor (T73), the 75th transistor (T75), and the 77th transistor (T77) are turned on when the voltage of the Q node is at a high level and generate a high-level scan clock (SCCLK(i). ), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) to the second output node (NO2), third output node (NO3), fourth output node (NO4), and fifth Each is supplied to the output node (NO5). Accordingly, high-level scan signals (SCAN(i), SCAN(i+1), SCAN(i+2), and SCAN(i+3)) are output, respectively.

The 71st transistor (T71), 73rd transistor (T73), 75th transistor (T75), and 77th transistor (T77) respectively correspond to pull-up transistors.

When scan signals (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) are output, the boosting capacitors (CS1, CS2, CS3, CS4) are set to high-level scan signals. Boosting the voltage of the Q node in synchronization with the clock (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) higher than the level of the first high-potential gate voltage (GVDD1) Bootstrap or increase the level. When the voltage of the Q node is bootstrapped, the high-level scan clocks (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) are generated quickly and without distortion. i), SCAN(i+1), SCAN(i+2), SCAN(i+3)).

The 72nd transistor (T72), the 74th transistor (T74), the 76th transistor (T76), and the 78th transistor (T78) respond to the voltage of the QB node and produce a second output based on the first low-potential gate voltage (GVSS1). Low-level scan signals (SCAN(i), SCAN(i+1), SCAN( i+2) and SCAN(i+3)) are output respectively.

The 72nd transistor (T72), 74th transistor (T74), 76th transistor (T76), and 78th transistor (T78) are turned on when the voltage of the QB node is at a high level to increase the first low-potential gate voltage (GVSS1). is supplied to the second output node (NO2), the third output node (NO3), the fourth output node (NO4), and the fifth output node (NO5), respectively. Accordingly, low-level scan signals (SCAN(i), SCAN(i+1), SCAN(i+2), and SCAN(i+3)) are output.

The 72nd transistor (T72), 74th transistor (T74), 76th transistor (T76), and 78th transistor (T78) respectively correspond to pull-down transistors.

Here, three high-potential gate voltages (GVDD1, GVDD2, GVDD3) set to different levels and three low-potential gate voltages (GVSS1, GVSS2, GVSS3) set to different levels are supplied to each stage circuit. Indicates a case. For example, the first high-potential gate voltage (GVDD1) may be set to 20V, the second high-potential gate voltage (GVDD2) may be set to 16V, the third high-potential gate voltage (GVDD3) may be set to 14V, and the first low-potential gate voltage may be set to 14V. (GVSS1) can be set to -6V, the second low-potential gate voltage (GVSS2) can be set to -10V, and the third low-potential gate voltage (GVSS3) can be set to -12V. This figure is just an example, and the levels of the high-potential gate voltage and the low-potential gate voltage may be set differently depending on the embodiment.

FIG. 8 is a diagram showing an example of a 16-phase scan clock line arranged in one gate driving integrated circuit, and FIG. 9 is a diagram showing an example of a signal waveform of a 16-phase scan clock applied through a 16-phase scan clock line. It is a drawing.

8 and 9, a plurality of gate driving integrated circuits (GDIC(1), GDIC(2), GDIC(3), GDIC(4),...) constituting the gate driving circuit 120 have phases. 16 different scan clocks (SCCLK(1)-SCCLK(16)) can be applied through 16 scan clock lines (SCL(1)-SCL(16)). At this time, 16 scan clocks (SCCLK(1)-SCCLK(16)) may each correspond to 16 scan signals (SCAN(1)-SCAN(16)).

Here, the case where 16 scan clock lines (SCL(1)-SCL(16)) are arranged sequentially is shown as an example, and can be changed to various structures such as 8-phase or 12-phase scan clock lines.

The 16 scan clocks (SCCLK(1)-SCCLK(16)) applied through the 16-phase scan clock lines (SCL(1)-SCL(16)) may be pulse signals with different phases. The phases of the 16-phase scan clocks (SCCLK(1)-SCCLK(16)) are predetermined according to the clock order, and the smaller the clock number, the faster the phase. Accordingly, among the 16-phase scan clocks (SCCLK(1)-SCCLK(16)), the phase of the first scan clock (SCCLK(1)) is the fastest, and the phase of the 16th scan clock (SCCLK(16)) is the latest.

All 16-phase scan clocks (SCCLK(1)-SCCLK(16)) have the same pulse width, and here, they have a pulse width of 4 horizontal periods (4H).

Additionally, the phase of the 16-phase scan clock (SCCLK(1)-SCCLK(16)) may be delayed at regular time intervals, for example, at an interval of 1 horizontal period (1H). Accordingly, the 16-phase scan clocks (SCCLK(1)-SCCLK(16)) may overlap with adjacent scan clocks by 3 horizontal periods (3H).

Meanwhile, the gate driving integrated circuits (GDIC(1), GDIC(2), GDIC(3), GDIC(4),...) can each output one or more scan signals, where one gate driving integrated circuit This shows a case where 4 scan signals are output.

The display panel 110 is designed to narrow the spacing between the 16-phase scan clock lines (SCL(1)-SCL(16)) in order to narrow the bezel. In this case, the scan clock lines (SCCLK(1)-SCCLK) (16)), the parasitic capacitance that occurs between them may become large.

At this time, depending on the signal overlap between adjacent scan clocks (SCCLK(1)-SCCLK(16)), the effect of parasitic capacitance occurring between scan clocks (SCCLK(1)-SCCLK(16)) may vary. . As a result, the pulse width of the scan signal (SCAN(1)-SCAN(16)) output from the gate driving integrated circuit (GDIC(1), GDIC(2), GDIC(3), GDIC(4),...) changes and image quality may deteriorate.

For example, when 16-phase scan clocks (SCCLK(1)-SCCLK(12)) overlap with adjacent scan clocks by 3 horizontal periods (3H), the first scan clock (SCCLK(1)) is the second scan clock. (SCCLK(2)) overlaps by 3 horizontal cycles (3H).

On the other hand, the second scan clock (SCCLK(2)) overlaps with the first scan clock (SCCLK(1)) by 3 horizontal cycles (3H) and also overlaps with the third scan clock (SCCLK(3)) by 3 horizontal cycles (3H). It overlaps by 3H). Likewise, the third scan clock (SCCLK(3)) overlaps with the second scan clock (SCCLK(2)) by 3 horizontal periods (3H) and overlaps with the fourth scan clock (SCCLK(4)) by 3 horizontal periods (3H). It overlaps by 3H). This overlap characteristic appears equally in the case of the second scan clock (SCCLK(2)) to the fifteenth scan clock (SCCLK(15)).

Additionally, the 16th scan clock (SCCLK(16)) overlaps with the 15th scan clock (SCCLK(15)) by 3 horizontal periods (3H).

Ultimately, in the case of a 16-phase scan clock (SCCLK(1)-SCCLK(16)), the first scan clock line (SCL(1)) and the 16th scan clock line (SCL(16)) placed on the outer edge are Although they have the same overlapping characteristics, the second to fifteenth scan clock lines (SCL(2)) to the fifteenth scan clock lines (SCL(15)) disposed between them have different overlapping characteristics.

FIG. 10 is a diagram illustrating the parasitic capacitance between scan clock lines and the resulting distortion of the scan signal in the structures of FIGS. 8 and 9 as an example.

Referring to FIG. 10, 16-phase scan clocks (SCCLK(1)-SCCLK(12)) may have a pulse width of 4 horizontal cycles (4H) and be transmitted at intervals of 1 horizontal cycle (1H). In this case, the first scan clock (SCCLK(1)) overlaps the second scan clock (SCCLK(2)) by 3 horizontal periods (3H), and the 16th scan clock (SCCLK(16)) overlaps with the 15th scan clock (SCCLK(16)). (SCCLK(15)) overlaps by 3 horizontal cycles (3H). Therefore, the first ripple (Ripple(1)) appearing in the first scan clock (SCCLK(1)) and the 16th ripple (Ripple(16)) appearing in the 16th scan clock (SCCLK(16)) may be the same. .

On the other hand, the ripples (Ripple(2)-Ripple(15)) that appear in the 2nd scan clock (SCCLK(2)) to the 15th scan clock (SCCLK(15)) are the first ripple by the scan clock lines placed on both sides. (Ripple(1)) and the 16th ripple (Ripple(16)).

As a result, the scan signal (SCAN(1)) output from the gate driving integrated circuit (GDIC(1), GDIC(2), GDIC(3), GIIC(4),...) due to the deviation of the ripple due to the parasitic capacitance. - Deviation may occur in the SCAN (16), and horizontal line defects may occur in the display panel (110).

Therefore, it is necessary to eliminate horizontal line defects caused by ripple deviation by making parasitic capacitances occurring between scan clock lines (SCL(1)-SCL(16)) the same.

FIG. 11 is a diagram showing an example of the arrangement of a scan clock line that can reduce parasitic capacitance in a display device according to embodiments of the present disclosure, and FIG. 12 is a signal waveform diagram according to the arrangement of the scan clock line of FIG. 11. This is a drawing shown as an example.

11 and 12, in the display device 100 according to embodiments of the present disclosure, a plurality of gate driving integrated circuits (GDIC(1), GDIC(2), 16 scan clocks (SCCLK(1)-SCCLK(16)) with different phases are applied to GDIC(3), GDIC(4), …) to correspond to scan signals (SCAN(1)-SCAN(16)). It can be.

All 16-phase scan clocks (SCCLK(1)-SCCLK(16)) have the same pulse width, and here, they have a pulse width of 4 horizontal periods (4H).

Additionally, the phase of the 16-phase scan clock (SCCLK(1)-SCCLK(16)) may be delayed at regular time intervals, for example, at an interval of 1 horizontal period (1H). Accordingly, the 16-phase scan clocks (SCCLK(1)-SCCLK(16)) may overlap with adjacent scan clocks by 3 horizontal periods (3H).

Gate driving integrated circuits (GDIC(1), GDIC(2), GDIC(3), GDIC(4),...) can each output four scan signals. Specifically, the first gate driving integrated circuit (GDIC(1)) outputs the first scan signal (SCAN(1)) to the fourth scan signal (SCAN(4)), and the second gate driving integrated circuit (GDIC(2) )) can output the fifth scan signal (SCAN(5)) to the eighth scan signal (SCAN(8)). In addition, the third gate driving integrated circuit (GDIC(3)) outputs the ninth scan signal (SCAN(9)) to the twelfth scan signal (SCAN(12)), and the fourth gate driving integrated circuit (GDIC(4) )) can output the 13th scan signal (SCAN(13)) to the 16th scan signal (SCAN(16)).

The display device 100 of the present disclosure provides a dummy scan clock line outside the outermost scan clock line to reduce the deviation of the parasitic capacitance caused between the scan clocks (SCCLK(1) - SCCLK(16)). (DSCL(1), DSCL(2)) can be placed.

For example, in the structure of the 16-phase scan clock (SCCLK(1)-SCCLK(16)), the first scan clock line (SCL(1)) disposed on the leftmost side corresponds to the first outermost scan clock line and , the 16th scan clock line (SCL(16)) disposed on the rightmost side will correspond to the second outermost scan clock line.

At this time, the first dummy scan clock line (DSCL(1)) is placed to the left of the first scan clock line (SCL(1)), and the second dummy scan clock line (DSCL(1)) is placed to the right of the 16th scan clock line (SCL(16)). Place the scan clock line (DSCL(2)).

Since the dummy scan clock lines (DSCL(1), DSCL(2)) are not electrically connected to the gate drive integrated circuit (GDIC(1), GDIC(2), GDIC(3), GDIC(4), …), It does not affect the output of the scan signal from the gate driving integrated circuit (GDIC(1), GDIC(2), GDIC(3), GDIC(4),...).

However, in order to reduce the deviation of the parasitic capacitance caused between the scan clocks (SCCLK(1) - SCCLK(16)), a first dummy scan clock (DSCCLK(1)) is provided on the first dummy scan clock line (DSCL(1)). 1)) is applied, and the second dummy scan clock (DSCCLK(2)) may be applied to the second dummy scan clock line (DSCL(2)).

More specifically, the first dummy scan clock (DSCCLK(1)) applied to the first dummy scan clock line (DSCL(1)) is a pulse having the same phase and amplitude as the 16th scan clock (SCCLK(16)). , the second dummy scan clock (DSCCLK(2)) applied to the second dummy scan clock line (DSCL(2)) may be a pulse having the same phase and amplitude as the first scan clock (SCCLK(1)).

To this end, the first dummy scan clock line (DSCL(1)) disposed adjacent to the first scan clock line (SCL(1)) may be electrically connected to the 16th scan clock line (SCL(16)).

At this time, the first dummy scan clock line (DSCL(1)) and the sixteenth scan clock line (SCL(16)) may be electrically connected to the source printed circuit board (SPCB) or the control printed circuit board (CPCB).

Accordingly, pulses having the same phase and amplitude can be applied to the first dummy scan clock line (DSCL(1)) and the 16th scan clock line (SCL(16)).

On the other hand, a separate pulse generation circuit is placed on the first dummy scan clock line (DSCL(1)), and a first dummy scan clock (DSCCLK(1)) having the same phase and amplitude as the 16th scan clock (SCCLK(16)) is used. )) may be created and approved.

Additionally, the second dummy scan clock line (DSCL(2)) disposed adjacent to the 16th scan clock line (SCL(16)) may be electrically connected to the first scan clock line (SCL(1)).

At this time, the second dummy scan clock line (DSCL(2)) and the first scan clock line (SCL(1)) may be electrically connected to the source printed circuit board (SPCB) or the control printed circuit board (CPCB).

Accordingly, pulses having the same phase and amplitude can be applied to the second dummy scan clock line (DSCL(2)) and the first scan clock line (SCL(1)).

On the other hand, a separate pulse generation circuit is placed on the second dummy scan clock line (DSCL(2)), and a second dummy scan clock (DSCCLK(2)) has the same phase and amplitude as the first scan clock (SCCLK(1)). )) may be created and approved.

In this way, when the first dummy scan clock (DSCCLK(1)) of the same pulse as the 16th scan clock (SCCLK(16)) is applied to the first dummy scan clock line (DSCL(1)), the first scan clock The clock (SCCLK(1)) overlaps with the first dummy scan clock (DSCCLK(1)) for 3 horizontal cycles (3H) and overlaps with the second scan clock (SCCLK(2)) for 3 horizontal cycles (3H). . Accordingly, the parasitic capacitance appearing in the first scan clock (SCCLK(1)) is at the same level as the parasitic capacitance appearing in the second scan clock (SCCLK(2)) to the fifteenth scan clock (SCCLK(15)). As a result, horizontal line defects caused by variations in parasitic capacitance are alleviated.

In addition, when the second dummy scan clock (DSCCLK(2)) of the same pulse as the first scan clock (SCCLK(1)) is applied to the second dummy scan clock line (DSCL(2)), the 16th scan clock (SCCLK(16)) overlaps with the 15th scan clock (SCCLK(15)) for 3 horizontal cycles (3H) and also overlaps with the second dummy scan clock (DSCCLK(2)) for 3 horizontal cycles (3H). Accordingly, the parasitic capacitance appearing in the 16th scan clock (SCCLK(16)) is at the same level as the parasitic capacitance appearing in the 2nd scan clock (SCCLK(2)) to the 15th scan clock (SCCLK(15)). As a result, horizontal line defects caused by variations in parasitic capacitance are alleviated.

FIG. 13 is a diagram showing an example of a case in which horizontal line defects are improved by a dummy scan clock applied through a dummy scan clock line in a display device according to embodiments of the present disclosure.

Referring to FIG. 13, in the display device 100 according to embodiments of the present disclosure, in order to reduce the deviation of parasitic capacitance caused between 16-phase scan clocks (SCCLK(1)-SCCLK(16)), the maximum A first dummy scan clock line (DSCL(1)) and a second dummy scan clock line outside the first scan clock line (SCL(1)) and the sixteenth scan clock line (SCL(16)) disposed on the outside, respectively. (DSCL(2)) can be placed.

To reduce the deviation of the parasitic capacitance caused between the scan clocks (SCCLK(1) - SCCLK(16)), a first dummy scan clock (DSCCLK(1)) is provided on the first dummy scan clock line (DSCL(1)). ) is applied, and the second dummy scan clock (DSCCLK(2)) may be applied to the second dummy scan clock line (DSCL(2)).

The first dummy scan clock (DSCCLK(1)) is a pulse having the same phase and amplitude as the 16th scan clock (SCCLK(16)), and the second dummy scan clock (DSCCLK(2)) is a pulse with the same phase and amplitude as the 16th scan clock (SCCLK(16)). It may be a pulse with the same phase and amplitude as (1)).

As a result, the parasitic capacitance appearing in the first scan clock (SCCLK(1)) is at the same level as the parasitic capacitance appearing in the second scan clock (SCCLK(2)) to the fifteenth scan clock (SCCLK(15)).

Additionally, the parasitic capacitance appearing in the 16th scan clock (SCCLK(16)) is at the same level as the parasitic capacitance appearing in the 2nd scan clock (SCCLK(2)) to the 15th scan clock (SCCLK(15)). As a result, horizontal line defects caused by variations in parasitic capacitance are alleviated.

Additionally, the display device 100 of the present disclosure can be applied to various structures with different numbers of scan clock lines. For example, it may be applied to the structure of a 12-phase scan clock line that drives the gate driving circuit 120 using 12 scan clocks.

FIG. 14 is a diagram showing an example of the arrangement of a 12-phase scan clock line that can reduce parasitic capacitance in a display device according to further embodiments of the present disclosure.

Referring to FIG. 14, in the display device 100 according to embodiments of the present disclosure, a plurality of gate driving integrated circuits (GDIC(1), GDIC(2), GDIC(3) constituting the gate driving circuit 120 ), GDIC(4), …) 12 scan clocks (SCCLK(1)-SCCLK(12)) with different phases can be applied to correspond to the scan signals (SCAN(1)-SCAN(16)). .

All 12-phase scan clocks (SCCLK(1)-SCCLK(12)) have the same pulse width, and here, the pulse width is 4 horizontal periods (4H).

Additionally, the phase of the 12-phase scan clock (SCCLK(1)-SCCLK(12)) may be delayed at regular time intervals, for example, at an interval of 1 horizontal period (1H). Accordingly, the 12-phase scan clocks (SCCLK(1)-SCCLK(12)) may overlap with adjacent scan clocks by 3 horizontal periods (3H).

Gate driving integrated circuits (GDIC(1), GDIC(2), GDIC(3), GDIC(4),...) can each output four scan signals. Specifically, the first gate driving integrated circuit (GDIC(1)) outputs the first scan signal (SCAN(1)) to the fourth scan signal (SCAN(4)), and the second gate driving integrated circuit (GDIC(2) )) can output the fifth scan signal (SCAN(5)) to the eighth scan signal (SCAN(8)). Additionally, the third gate driving integrated circuit (GDIC(3)) outputs the ninth scan signal (SCAN(9)) to the twelfth scan signal (SCAN(12)), and the fourth gate driving integrated circuit (GDIC(4) )) can output the 13th scan signal (SCAN(13)) to the 16th scan signal (SCAN(16)).

In the display device 100 of the present disclosure, in order to reduce the deviation of the parasitic capacitance caused between the 12-phase scan clocks (SCCLK(1) - SCCLK(12)), each device is provided outside the outermost scan clock line. A first dummy scan clock line (DSCL(1)) and a second dummy scan clock line (DSCL(2)) may be disposed.

For example, in the structure of the 12-phase scan clock (SCCLK(1)-SCCLK(12)), the first scan clock line (SCL(1)) disposed on the leftmost side corresponds to the first outermost scan clock line and , the 12th scan clock line (SCL(12)) disposed on the rightmost side will correspond to the second outermost scan clock line.

At this time, the first dummy scan clock line (DSCL(1)) is placed to the left of the first scan clock line (SCL(1)), and the second dummy scan clock line (DSCL(1)) is placed to the right of the twelfth scan clock line (SCL(12)). Place the scan clock line (DSCL(2)).

Since the dummy scan clock lines (DSCL(1), DSCL(2)) are not electrically connected to the gate drive integrated circuit (GDIC(1), GDIC(2), GDIC(3), GDIC(4), …), It does not affect the output of the scan signal from the gate driving integrated circuit (GDIC(1), GDIC(2), GDIC(3), GDIC(4),...).

However, in order to reduce the deviation of the parasitic capacitance caused between the scan clocks (SCCLK(1) - SCCLK(12)), a first dummy scan clock (DSCCLK(1)) is provided on the first dummy scan clock line (DSCL(1)). 1)) is applied, and the second dummy scan clock (DSCCLK(2)) may be applied to the second dummy scan clock line (DSCL(2)).

More specifically, the first dummy scan clock (DSCCLK(1)) applied to the first dummy scan clock line (DSCL(1)) is a pulse having the same phase and amplitude as the 12th scan clock (SCCLK(12)). , the second dummy scan clock (DSCCLK(2)) applied to the second dummy scan clock line (DSCL(2)) may be a pulse having the same phase and amplitude as the first scan clock (SCCLK(1)).

To this end, the first dummy scan clock line (DSCL(1)) disposed adjacent to the first scan clock line (SCL(1)) may be electrically connected to the 12th scan clock line (SCL(12)).

At this time, the first dummy scan clock line (DSCL(1)) and the twelfth scan clock line (SCL(12)) may be electrically connected to the source printed circuit board (SPCB) or the control printed circuit board (CPCB).

Accordingly, pulses having the same phase and amplitude can be applied to the first dummy scan clock line (DSCL(1)) and the twelfth scan clock line (SCL(12)).

On the other hand, a separate pulse generation circuit is placed on the first dummy scan clock line (DSCL(1)), and a first dummy scan clock (DSCCLK(1)) having the same phase and amplitude as the 12th scan clock (SCCLK(12)) is used. )) may be created and approved.

Additionally, the second dummy scan clock line (DSCL(2)) disposed adjacent to the twelfth scan clock line (SCL(12)) may be electrically connected to the first scan clock line (SCL(1)).

At this time, the second dummy scan clock line (DSCL(2)) and the first scan clock line (SCL(1)) may be electrically connected to the source printed circuit board (SPCB) or the control printed circuit board (CPCB).

Accordingly, pulses having the same phase and amplitude can be applied to the second dummy scan clock line (DSCL(2)) and the first scan clock line (SCL(1)).

On the other hand, a separate pulse generation circuit is placed on the second dummy scan clock line (DSCL(2)), and a second dummy scan clock (DSCCLK(2)) has the same phase and amplitude as the first scan clock (SCCLK(1)). )) may be created and approved.

In this way, when the first dummy scan clock (DSCCLK(1)) of the same pulse as the 12th scan clock (SCCLK(12)) is applied to the first dummy scan clock line (DSCL(1)), the first scan clock The clock (SCCLK(1)) overlaps with the first dummy scan clock (DSCCLK(1)) for 3 horizontal cycles (3H) and overlaps with the second scan clock (SCCLK(2)) for 3 horizontal cycles (3H). . Accordingly, the parasitic capacitance appearing in the first scan clock (SCCLK(1)) is at the same level as the parasitic capacitance appearing in the second scan clock (SCCLK(2)) to the eleventh scan clock (SCCLK(11)). As a result, horizontal line defects caused by variations in parasitic capacitance are alleviated.

Additionally, when the second dummy scan clock (DSCCLK(2)) of the same pulse as the first scan clock (SCCLK(1)) is applied to the second dummy scan clock line (DSCL(2)), the 12th scan clock (SCCLK(12)) overlaps with the 11th scan clock (SCCLK(11)) for 3 horizontal cycles (3H) and also overlaps with the second dummy scan clock (DSCCLK(2)) for 3 horizontal cycles (3H). Accordingly, the parasitic capacitance appearing in the 12th scan clock (SCCLK(12)) is at the same level as the parasitic capacitance appearing in the 2nd scan clock (SCCLK(2)) to the 11th scan clock (SCCLK(11)). As a result, horizontal line defects caused by variations in parasitic capacitance are alleviated.

The embodiments of the present disclosure described above are briefly described as follows.

The display panel 110 of the present disclosure includes a plurality of subpixels (SP) disposed in an area where a plurality of gate lines (GL) and a plurality of data lines (DL) intersect, and a plurality of subpixels (SP) arranged through the plurality of gate lines (GL). A plurality of gate in panel (GIP) circuits (GIPC) that supply a plurality of scan signals (SCAN) to the plurality of subpixels (SP), and a plurality of scan clocks (SCCLK) corresponding to the plurality of scan signals (SCAN) ) and a plurality of scan clock lines (SCL) that supply the plurality of gate in panel (GIP) circuits (GIPC), and disposed adjacent to a first outermost scan clock line among the plurality of scan clock lines (SCL). Includes a first dummy scan clock line (DSCL(1)) and a second dummy scan clock line (DSCL(2)) disposed adjacent to the second outermost scan clock line among the plurality of scan clock lines (SCL). can do.

The plurality of scan clock lines (SCL) are N-phase scan clock lines that transmit N (N is a natural number) scan clocks (SCCLK), and the first outermost scan clock line is a first scan clock line (SCL(1) )), and the second outermost scan clock line may be the Nth scan clock line.

The first dummy scan clock line (DSCL(1)) and the second dummy scan clock line (DSCL(2)) may be respectively disposed outside the plurality of scan clock lines (SCL).

The first dummy scan clock line (DSCL(1)) and the second dummy scan clock line (DSCL(2)) may be electrically insulated from the plurality of gate in panel (GIP) circuits (GIPC).

A first dummy scan clock (DSCCLK(1)) is applied to the first dummy scan clock line (DSCL(1)), and a second dummy scan clock (DSCCLK(1)) is applied to the second dummy scan clock line (DSCL(2)). (2)) may be approved.

The first dummy scan clock (DSCCLK(1)) has the same phase and amplitude as the scan clock applied to the second outermost scan clock line, and the second dummy scan clock (DSCCLK(2)) has the same phase and amplitude as the scan clock applied to the second outermost scan clock line. The phase and amplitude may be the same as the scan clock applied to the outermost scan clock line.

a first pulse generation circuit that supplies the first dummy scan clock (DSCCLK(1)) to the first dummy scan clock line (DSCL(1)); and a second pulse generation circuit that supplies the second dummy scan clock (DSCCLK(2)) to the second dummy scan clock line (DSCL(2)).

The first dummy scan clock line (DSCL(1)) is electrically connected to the second outermost scan clock line, and the second dummy scan clock line (DSCL(2)) is electrically connected to the first outermost scan clock line. can be electrically connected to.

In addition, the display device 100 of the present disclosure includes a display panel 110 on which a plurality of subpixels (SP) are arranged, and a plurality of scan signals (SCAN) transmitted to the display panel 110 through a plurality of gate lines (GL). ) and data configured to supply a plurality of data voltages to the display panel 110 through a plurality of data lines DL. A driving circuit 130, a timing controller 140 configured to control the gate driving circuit 120 and the data driving circuit 130, and a plurality of scan clocks (SCCLK) corresponding to the plurality of scan signals (SCAN) ) a plurality of scan clock lines (SCL) that supply the plurality of scan clock lines (SCL) to the plurality of gate driving integrated circuits (GDIC), and a first dummy disposed adjacent to the first outermost scan clock line among the plurality of scan clock lines (SCL) It may include a scan clock line (DSCL(1)) and a second dummy scan clock line (DSCL(2)) disposed adjacent to the second outermost scan clock line among the plurality of scan clock lines (SCL). .

The first dummy scan clock line (DSCL(1)) and the second dummy scan clock line (DSCL(2)) are connected to the first dummy scan clock line (DSCL(2)) in the source printed circuit board (SPCB) on which the data driving circuit 130 is disposed. It may be electrically connected to the outermost scan clock line and the second outermost scan clock line.

The first dummy scan clock line (DSCL(1)) and the second dummy scan clock line (DSCL(2)) are in the control printed circuit board (CPCB) on which the timing controller 140 is disposed. It may be electrically connected to the outermost scan clock line and the second outermost scan clock line.

The above description is merely an illustrative explanation of the technical idea of the present disclosure, and those skilled in the art will be able to make various modifications and variations without departing from the essential characteristics of the present disclosure. In addition, the embodiments disclosed in the present disclosure are not intended to limit the technical idea of the present disclosure, but rather are for explanation, and therefore the scope of the technical idea of the present disclosure is not limited by these embodiments.

100: display device
110: display panel
120: Gate driving circuit
130: data driving circuit
131: Gate driving voltage line
132: clock line
133: Line sensing signal line
134: reset signal line
140: Timing controller
150: power management circuit
160: main power management circuit
170: set board
502: Line selection unit
504: Q node control unit
506: Q node stabilization unit
508: Inverter unit
510: QB node stabilization unit
512: Carry signal output unit
514: scan signal output unit

Claims (18)

A plurality of subpixels disposed in an area where a plurality of gate lines and a plurality of data lines intersect;
a plurality of gate-in-panel (GIP) circuits that supply a plurality of scan signals to the plurality of subpixels through the plurality of gate lines;
a plurality of scan clock lines supplying a plurality of scan clocks corresponding to the plurality of scan signals to the plurality of gate-in-panel (GIP) circuits;
a first dummy scan clock line disposed adjacent to a first outermost scan clock line among the plurality of scan clock lines; and
A display panel including a second dummy scan clock line disposed adjacent to a second outermost scan clock line among the plurality of scan clock lines.
According to claim 1,
The plurality of scan clock lines are
It is an N-phase scan clock line that transmits N (N is a natural number) scan clocks,
The first outermost scan clock line is the first scan clock line,
The display panel wherein the second outermost scan clock line is the Nth scan clock line.
According to claim 1,
The first dummy scan clock line and the second dummy scan clock line are
A display panel disposed outside each of the plurality of scan clock lines.
According to claim 1,
The first dummy scan clock line and the second dummy scan clock line are
A display panel electrically insulated from the plurality of gate-in-panel (GIP) circuits.
According to claim 1,
A first dummy scan clock is applied to the first dummy scan clock line,
A display panel in which a second dummy scan clock is applied to the second dummy scan clock line.
According to claim 5,
The first dummy scan clock is
The phase and amplitude are the same as the scan clock applied to the second outermost scan clock line,
The second dummy scan clock is
A display panel having the same phase and amplitude as a scan clock applied to the first outermost scan clock line.
According to claim 5,
a first pulse generation circuit that supplies the first dummy scan clock to the first dummy scan clock line; and
The display panel further includes a second pulse generation circuit that supplies the second dummy scan clock to the second dummy scan clock line.
According to claim 1,
The first dummy scan clock line is
electrically connected to the second outermost scan clock line,
The second dummy scan clock line is
A display panel electrically connected to the first outermost scan clock line.
A display panel on which a plurality of subpixels are arranged;
a gate driving circuit including a plurality of gate driving integrated circuits configured to supply a plurality of scan signals to the display panel through a plurality of gate lines;
a data driving circuit configured to supply a plurality of data voltages to the display panel through a plurality of data lines;
a timing controller configured to control the gate driving circuit and the data driving circuit;
a plurality of scan clock lines supplying a plurality of scan clocks corresponding to the plurality of scan signals to the plurality of gate driving integrated circuits;
a first dummy scan clock line disposed adjacent to a first outermost scan clock line among the plurality of scan clock lines; and
A display device comprising a second dummy scan clock line disposed adjacent to a second outermost scan clock line among the plurality of scan clock lines.
According to clause 9,
The plurality of scan clock lines are
It is an N-phase scan clock line that transmits N (N is a natural number) scan clocks,
The first outermost scan clock line is the first scan clock line,
The display device wherein the second outermost scan clock line is the Nth scan clock line.
According to clause 9,
The first dummy scan clock line and the second dummy scan clock line are
A display device disposed outside each of the plurality of scan clock lines.
According to clause 9,
The first dummy scan clock line and the second dummy scan clock line are
A display device electrically insulated from the plurality of gate-in-panel (GIP) circuits.
According to clause 9,
A first dummy scan clock is applied to the first dummy scan clock line,
A display device in which a second dummy scan clock is applied to the second dummy scan clock line.
According to claim 13,
The first dummy scan clock is
The phase and amplitude are the same as the scan clock applied to the second outermost scan clock line,
The second dummy scan clock is
A display device having the same phase and amplitude as a scan clock applied to the first outermost scan clock line.
According to claim 13,
a first pulse generation circuit that supplies the first dummy scan clock to the first dummy scan clock line; and
The display device further includes a second pulse generation circuit that supplies the second dummy scan clock to the second dummy scan clock line.
According to clause 9,
The first dummy scan clock line is
electrically connected to the second outermost scan clock line,
The second dummy scan clock line is
A display device electrically connected to the first outermost scan clock line.
According to claim 16,
The first dummy scan clock line and the second dummy scan clock line are
A display device electrically connected to the first outermost scan clock line and the second outermost scan clock line on the source printed circuit board on which the data driving circuit is disposed.
According to claim 16,
The first dummy scan clock line and the second dummy scan clock line are
A display device electrically connected to the first outermost scan clock line and the second outermost scan clock line on a control printed circuit board on which the timing controller is disposed.

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