KR20240050999A - A semiconductor memory device and an electronic system including the same - Google Patents

Abstract

The semiconductor memory device of the present invention is stacked sequentially on a substrate including a cell array area, an extension area, and a boundary area between the cell array area and the extension area, on the substrate of the cell array area and the boundary area, and on the substrate of the extension area. A mold structure including a plurality of gate electrodes stacked in a pattern and a plurality of mold insulating films alternately stacked with the plurality of gate electrodes, and a plurality of gate electrodes penetrating the mold structure on a substrate in the cell array area. A plurality of intersecting channel structures, on the substrate in the border area, a plurality of dummy channel structures penetrating the mold structure, on the substrate in the extension area, a plurality of cell contacts connected to each of the plurality of gate electrodes, In the cell array area, a source layer disposed between the substrate and the mold structure and connected to the plurality of channel structures; in the extension area, a source sacrificial layer disposed between the mold structure of the substrate; and between the source layer and the source sacrificial layer. and a source support layer covering the source layer and the source sacrificial layer, wherein the top surface of the source support layer includes a first portion extending parallel to the top surface of the substrate, a second portion spaced apart from the first portion, and a second portion between the first portion and the second portion. and a third portion connecting the portions, wherein the first vertical distance from the top surface of the source layer to the first portion is less than the second vertical distance from the top surface of the substrate to the second portion.

Description

Semiconductor memory device and electronic system including same {A SEMICONDUCTOR MEMORY DEVICE AND AN ELECTRONIC SYSTEM INCLUDING THE SAME}

The present invention relates to a semiconductor memory device with improved reliability and an electronic system including the same.

There is a need to increase the integration of non-volatile memory devices to meet the excellent performance and low prices demanded by consumers. In the case of non-volatile memory devices, since the degree of integration is an important factor in determining the price of the product, increased integration is especially required.

Meanwhile, in the case of two-dimensional or two-dimensional non-volatile memory devices, the degree of integration is mainly determined by the area occupied by a unit memory cell, and is therefore greatly affected by the level of fine pattern formation technology. However, because ultra-expensive equipment is required to refine the pattern, the integration of two-dimensional non-volatile memory devices is increasing but is still limited. Accordingly, three-dimensional non-volatile memory devices having memory cells arranged three-dimensionally have been proposed.

The technical problem to be solved by the present invention is to provide a semiconductor memory device with improved reliability.

Another technical problem to be solved by the present invention is to provide an electronic system including a semiconductor memory device with improved reliability.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A semiconductor memory device according to some embodiments of the present invention for achieving the above technical problem includes a substrate including a cell array area, an extension area, and a boundary area between the cell array area and the extension area, the cell array area, and A mold structure including a plurality of gate electrodes sequentially stacked on the substrate in the boundary area and in a step shape on the substrate in the extension area, and a plurality of mold insulating films alternately stacked with the plurality of gate electrodes; On the substrate in the cell array area, a plurality of channel structures penetrate the mold structure and intersect the plurality of gate electrodes, and on the substrate in the boundary area, a plurality of dummy channel structures penetrate the mold structure. , on the substrate in the extended area, a plurality of cell contacts connected to each of the plurality of gate electrodes, disposed in the cell array area between the substrate and the mold structure, and the plurality of channel structures and a connected source layer, a source sacrificial layer disposed in the extension region between the mold structure of the substrate, and a source support layer filling between the source layer and the source sacrificial layer and covering the source layer and the source sacrificial layer. wherein the upper surface of the source support layer includes a first part extending parallel to the upper surface of the substrate, a second part spaced apart from the first part, and a third part connecting the first part and the second part. and a first vertical distance from the top surface of the source layer to the first portion is smaller than a second vertical distance from the top surface of the substrate to the second portion.

A semiconductor memory device according to some embodiments of the present invention for achieving the above technical problem includes a substrate including a cell array area, an extension area, and a boundary area between the cell array area and the extension area, the cell array area, and the A mold structure including a plurality of gate electrodes sequentially stacked on a substrate in a boundary area and stacked in a step shape on a substrate in the extension area, and a plurality of mold insulating films alternately stacked with the plurality of gate electrodes, the mold structure comprising: On the substrate in the cell array area, a plurality of channel structures penetrate the mold structure and intersect the plurality of gate electrodes, each of the plurality of channel structures is disposed in a channel hole penetrating the mold structure, An information storage film disposed along the sidewall and bottom of the channel hole, a plurality of channel structures including a semiconductor pattern on the information storage film, and a plurality of dummy channels penetrating the mold structure on the substrate in the boundary area. Structures, on the substrate in the extended area, a plurality of cell contacts connected to each of the plurality of gate electrodes, a word line extending in a first direction on the substrate and cutting the plurality of gate electrodes A cutting structure, a bit line connected to each of the plurality of channel structures on the mold structure and extending in a second direction, disposed in the cell array area between the substrate and the mold structure, and a sidewall of the information storage film A source layer passing through and connected to the semiconductor pattern, a source sacrificial layer disposed in the extension region between the mold structures of the substrate, and filling between the source layer and the source sacrificial layer, the source layer, and and a source support layer covering the source sacrificial layer, wherein a first vertical distance from the top surface of the source layer to the top of the top surface of the source support layer is less than a second vertical distance from the top surface of the substrate to the bottom of the top surface of the source support layer. , the third vertical distance from the top surface of the source sacrificial layer to the top surface of the source support layer is smaller than the second vertical distance, and the level of the bottom surface of the word line cut structure on the cell array area with respect to the top surface of the substrate The level of the bottom surface of the word line cut structure on the extended area is different.

An electronic system according to some embodiments of the present invention for achieving the above technical problem includes a main board, a semiconductor memory device on the main board, and a controller electrically connected to the semiconductor memory device on the main board, The semiconductor memory device is sequentially stacked on a substrate including a cell array area, an extension area, and a boundary area between the cell array area and the extension area, on a substrate of the cell array area and the boundary area, and the extension area. A mold structure including a plurality of gate electrodes stacked in a step shape on a substrate and a plurality of mold insulating films alternately stacked with the plurality of gate electrodes, and penetrating the mold structure on the substrate in the cell array area. A plurality of channel structures intersecting the plurality of gate electrodes, a plurality of dummy channel structures penetrating the mold structure, on the substrate in the boundary area, and a plurality of dummy channel structures on the substrate in the extension area, each of the plurality of channel structures A plurality of cell contacts connected to the gate electrodes, in the cell array region, a source layer disposed between the substrate and the mold structure, and connected to the plurality of channel structures, in the extension region, the A source sacrificial layer disposed between the mold structures, and a source support layer that fills between the source layer and the source sacrificial layer and covers the source layer and the source sacrificial layer, wherein the top surface of the source support layer is the top surface of the substrate. A first part extending in parallel, a second part spaced apart from the first part, and a third part connecting the first part and the second part, from the top surface of the source layer to the first part. The first vertical distance is smaller than the second vertical distance from the top surface of the substrate to the second portion.

Specific details of other embodiments are included in the description and drawings.

1 is an example block diagram for explaining a semiconductor memory device according to some embodiments.
FIG. 2 is an example circuit diagram illustrating a semiconductor memory device according to some embodiments.
3 is an exemplary plan view of a semiconductor memory device according to some embodiments.
FIG. 4 is an exemplary cross-sectional view taken along line AA of FIG. 3.
Figure 5 is an enlarged view of area P in Figure 4.
FIG. 6 is an exemplary cross-sectional view taken along line BB in FIG. 3.
Figure 7 is an enlarged view of area Q in Figure 6.
FIG. 8 is an exemplary cross-sectional view taken along line CC of FIG. 3.
FIG. 9 is an exemplary cross-sectional view taken along line DD in FIG. 3.
Figure 10 is an enlarged view of area R in Figure 9.
11 to 15 are exemplary diagrams for explaining semiconductor memory devices according to some other embodiments.
FIG. 16 is an example diagram for explaining a semiconductor memory device according to some other embodiments.
FIG. 17 is an example diagram for explaining a semiconductor memory device according to some other embodiments.
FIGS. 18 to 26 are diagrams sequentially showing the process of manufacturing a semiconductor memory device having the cross-section of FIGS. 4 and 5.
Figure 27 is an example block diagram for explaining an electronic system according to some embodiments.
Figure 28 is an example perspective view for explaining an electronic system according to some embodiments.
FIG. 29 is a schematic cross-sectional view taken along line II of FIG. 28.

In this specification, although first, second, upper, and lower are used to describe various elements or components, these elements or components are of course not limited by these terms. These terms are merely used to distinguish one device or component from another device or component. Therefore, of course, the first element or component mentioned below may also be a second element or component within the technical spirit of the present invention. In addition, of course, the lower elements or components mentioned below may also be upper elements or components within the technical spirit of the present invention.

Hereinafter, embodiments according to the technical idea of the present invention will be described with reference to the attached drawings. First, a semiconductor memory device according to some embodiments will be described with reference to FIGS. 1 to 10 .

1 is an example block diagram for explaining a semiconductor memory device according to some embodiments.

Referring to FIG. 1 , a semiconductor memory device 10 according to some embodiments includes a memory cell array 20 and a peripheral circuit 30.

The memory cell array 20 may include a plurality of memory cell blocks BLK1 to BLKn. Each memory cell block (BLK1 to BLKn) may include a plurality of memory cells. The memory cell array 20 may be connected to the peripheral circuit 30 through a bit line (BL), a word line (WL), at least one string select line (SSL), and at least one ground select line (GSL). Specifically, the memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 through a word line (WL), a string select line (SSL), and a ground select line (GSL). Additionally, the memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 through the bit line BL.

The peripheral circuit 30 can receive an address (ADDR), a command (CMD), and a control signal (CTRL) from outside the semiconductor memory device 10, and can receive data (DATA) from devices outside the semiconductor memory device 10. ) can be transmitted and received. The peripheral circuit 30 may include a control logic 37, a row decoder 33, and a page buffer 35. Although not shown, the peripheral circuit 30 includes an input/output circuit, a voltage generation circuit that generates various voltages necessary for the operation of the semiconductor memory device 10, and a correction for errors in data (DATA) read from the memory cell array 20. It may further include various sub-circuits such as an error correction circuit.

Control logic 37 may be connected to the row decoder 33, the input/output circuit, and the voltage generation circuit. The control logic 37 may control the overall operation of the semiconductor memory device 10. The control logic 37 may generate various internal control signals used within the semiconductor memory device 10 in response to the control signal CTRL. For example, the control logic 37 may adjust the voltage level provided to the word line (WL) and the bit line (BL) when performing a memory operation such as a program operation or an erase operation.

The row decoder 33 may select at least one of the plurality of memory cell blocks BLK1 to BLKn in response to the address ADDR, and selects at least one word line WL of the selected memory cell blocks BLK1 to BLKn. ), at least one string select line (SSL) and at least one ground select line (GSL) can be selected. Additionally, the row decoder 33 may transmit a voltage for performing a memory operation to the word line WL of the selected memory cell blocks BLK1 to BLKn.

The page buffer 35 may be connected to the memory cell array 20 through a bit line BL. The page buffer 35 may operate as a writer driver or a sense amplifier. Specifically, when performing a program operation, the page buffer 35 may operate as a write driver and apply a voltage according to the data (DATA) to be stored in the memory cell array 20 to the bit line (BL). Meanwhile, when performing a read operation, the page buffer 35 operates as a sense amplifier and can sense data (DATA) stored in the memory cell array 20.

FIG. 2 is an example circuit diagram illustrating a semiconductor memory device according to some embodiments.

Referring to FIG. 2, a memory cell array (e.g., 20 in FIG. 1) of a semiconductor memory device according to some embodiments includes a common source line (CSL), a plurality of bit lines (BL), and a plurality of cell strings (CSTR). includes them.

The common source line (CSL) may extend in the first direction (X). In some embodiments, a plurality of common source lines (CSLs) may be arranged two-dimensionally. For example, the plurality of common source lines (CSL) may be spaced apart from each other and each extend in the first direction (X). The same electrical voltage may be applied to the common source lines (CSL), or different voltages may be applied and controlled separately.

A plurality of bit lines BL may be arranged two-dimensionally. For example, the bit lines BL may be spaced apart from each other and extend in the second direction Y that intersects the first direction X. A plurality of cell strings (CSTR) may be connected in parallel to each bit line (BL). Cell strings (CSTR) may be commonly connected to a common source line (CSL). That is, a plurality of cell strings (CSTR) may be disposed between the bit lines (BL) and the common source line (CSL).

Each cell string (CSTR) includes a ground select transistor (GST) connected to the common source line (CSL), a string select transistor (SST) connected to the bit line (BL), a ground select transistor (GST), and a string select transistor ( It may include a plurality of memory cell transistors (MCT) disposed between (SST). Each memory cell transistor (MCT) may include a data storage element. The ground select transistor (GST), string select transistor (SST), and memory cell transistors (MCT) may be connected in series in the third direction (Z). In this specification, the first direction (X), the second direction (Y), and the third direction (Z) may be substantially perpendicular to each other.

The common source line (CSL) may be commonly connected to the sources of the ground select transistors (GST). Additionally, a ground select line (GSL), a plurality of word lines (WL1 to WLn), and a string select line (SSL) may be disposed between the common source line (CSL) and the bit line (BL). The ground select line (GSL) can be used as the gate electrode of the ground select transistor (GST), the word lines (WL1 to WLn) can be used as the gate electrode of the memory cell transistors (MCT), and the string select line (SSL) ) can be used as the gate electrode of a string select transistor (SST).

In some embodiments, an erase control transistor (ECT) may be disposed between the common source line (CSL) and the ground select transistor (GST). The common source line (CSL) may be commonly connected to the sources of the erase control transistors (ECT). Additionally, an erase control line (ECL) may be disposed between the common source line (CSL) and the ground select line (GSL). The erase control line (ECL) can be used as the gate electrode of the erase control transistor (ECT). Erase control transistors (ECT) may generate gate induced drain leakage (GIDL) to perform an erase operation of the memory cell array.

3 is an exemplary plan view of a semiconductor memory device according to some embodiments. FIG. 4 is an exemplary cross-sectional view taken along line A-A of FIG. 3. Figure 5 is an enlarged view of area P in Figure 4. FIG. 6 is an exemplary cross-sectional view taken along line B-B of FIG. 3. Figure 7 is an enlarged view of area Q in Figure 6. FIG. 8 is an exemplary cross-sectional view taken along line C-C of FIG. 3. FIG. 9 is an exemplary cross-sectional view taken along line D-D of FIG. 3. Figure 10 is an enlarged view of area R in Figure 9.

3 to 10 , a semiconductor memory device according to some embodiments includes a cell structure (CELL) and a peripheral circuit structure (PERI).

In some embodiments, the cell structure (CELL) includes a substrate 100, a mold structure (MS), a first interlayer insulating film 120, a second interlayer insulating film 140, a channel structure (CH), and a dummy channel structure (DCH). , a word line cutting structure (WLC), a source layer 102, a source support layer 104, a source sacrificial layer 106, a bit line (BL), and a plurality of cell contacts (CCT).

A semiconductor memory device according to some embodiments may include a cell array area (CAR), a border area (BR), and an extension area (EXT). The border area (BR) may be provided between the cell array area (CAR) and the extension area (EXT). The cell array area (CAR), border area (BR), and extension area (EXT) may be connected to each other.

A memory cell array (eg, 20 in FIG. 1 ) including a plurality of memory cells may be formed in the cell array area CAR. For example, a channel structure (CH), a bit line (BL), and gate electrodes (ECL, GSL, WL1 to WLn, SSL), which will be described later, may be disposed in the cell array area (CAR).

A plurality of dummy channel structures (DCH) may be disposed in the border area (BR). A plurality of dummy channel structures (DCH) may be channel structures that are not in operation. For example, a plurality of dummy channel structures (DCH) may not be connected to the bit line (BL).

The extension area (EXT) may be arranged around the cell array area (CAR). The extension area (EXT) may be arranged around the border area (BR). In the extension area EXT, gate electrodes ECL, GSL, WL1 to WLn, and SSL, which will be described later, may be stacked in a stepped shape. Additionally, a plurality of cell contacts (CCT), which will be described later, may be disposed in the extension area (EXT).

The substrate 100 may include a cell array area (CAR), a border area (BR), and an extension area (EXT). The substrate 100 may include, for example, a semiconductor substrate such as a silicon substrate, germanium substrate, or silicon-germanium substrate. Alternatively, the substrate 100 may include a Silicon-On-Insulator (SOI) substrate or a Germanium-On-Insulator (GOI) substrate. In some embodiments, the substrate 100 may contain impurities. For example, the substrate 100 may include n-type impurities (eg, phosphorus (P), arsenic (As), etc.).

The mold structure MS may be provided on the front surface (eg, top surface 100US) of the substrate 100. The mold structure MS may include a plurality of gate electrodes (ECL, GSL, WL1 to WLn, SSL) and a plurality of mold insulating films 110 alternately stacked on the substrate 100. Each of the gate electrodes (ECL, GSL, WL1 to WLn, SSL) and each mold insulating film 110 may have a layered structure extending parallel to the top surface 100US of the substrate 100. The gate electrodes (ECL, GSL, WL1 to WLn, SSL) may be sequentially stacked on the substrate 100 while being spaced apart from each other by the mold insulating films 110.

The gate electrodes (ECL, GSL, WL1 to WLn, SSL) may be stacked in a stepped shape in the extension area (EXT). For example, the gate electrodes (ECL, GSL, WL1 to WLn, SSL) may extend to different lengths in the first direction (X) and have a step difference. In some embodiments, the gate electrodes (ECL, GSL, WL1 to WLn, and SSL) may have a step in the second direction (Y). Accordingly, each of the gate electrodes (ECL, GSL, WL1 to WLn, and SSL) may be exposed from other gate electrodes. The exposed area may refer to an area where each of the plurality of cell contacts (CCT) and the gate electrode are in contact.

In some embodiments, the gate electrodes (ECL, GSL, WL1 to WLn, SSL) include an erase control line (ECL), a ground select line (GSL), and a plurality of word lines (WL1) sequentially stacked on the substrate 100. ~WLn) may be included. In some other embodiments, the erase control line (ECL) may be omitted.

The mold insulating films 110 may be stacked in a stepped shape in the extended area EXT. For example, the mold insulating films 110 may extend to different lengths in the first direction (X) and have a step difference. In some embodiments, the mold insulating films 110 may have a step in the second direction (Y).

The gate electrodes (ECL, GSL, WL1 to WLn, SSL) may each contain a conductive material, for example, a metal such as tungsten (W), cobalt (Co), nickel (Ni), or a semiconductor material such as silicon. However, it is not limited to this. For example, the gate electrodes (ECL, GSL, WL1 to WLn, and SSL) may each include tungsten (W). Unlike what is shown, the gate electrodes (ECL, GSL, WL1 to WLn, SSL) may be multilayer. For example, if the gate electrodes (ECL, GSL, WL1 to WLn, SSL) are multilayers, the gate electrodes (ECL, GSL, WL1 to WLn, SSL) may include a gate electrode barrier film and a gate electrode filling film. You can. For example, the gate electrode barrier layer may include titanium nitride (TiN), and the gate electrode filling layer may include tungsten (W), but are not limited thereto.

The mold insulating film 110 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto. For example, the mold insulating film 110 may include silicon oxide.

The channel structure (CH) may be provided in the mold structure (MS) of the cell array area (CAR). The channel structure CH may extend in a vertical direction (hereinafter referred to as the third direction Z) intersecting the upper surface 100US of the substrate 100 and penetrate the mold structure MS. For example, the channel structure CH may have a pillar shape (eg, a cylinder shape) extending in the third direction (Z). Accordingly, the channel structure CH may intersect each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL. The channel structure (CH) may be disposed in a channel hole penetrating the mold structure (MS).

The channel structure (CH) may include a semiconductor pattern 130 and an information storage layer 132.

The semiconductor pattern 130 may extend in the third direction (Z) and penetrate the mold structure (MS). The semiconductor pattern 130 is shown as having a cup shape, but this is only an example. For example, the semiconductor pattern 130 may have various shapes, such as a cylindrical shape, a rectangular cylinder shape, or a solid pillar shape. The semiconductor pattern 130 may include, but is not limited to, semiconductor materials such as single crystal silicon, polycrystalline silicon, organic semiconductor materials, and carbon nanostructures.

The information storage layer 132 may be interposed between the semiconductor pattern 130 and each of the gate electrodes (ECL, GSL, WL1 to WLn, and SSL). For example, the information storage layer 132 may extend along the outer surface of the semiconductor pattern 130 . The information storage film 132 may extend along the sidewall and bottom surface of the channel hole. The information storage layer 132 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material having a higher dielectric constant than silicon oxide. The high dielectric constant material is, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium. oxide), lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

In some embodiments, a plurality of channel structures (CH) may be arranged in a zigzag shape. For example, as shown in FIG. 3, a plurality of channel structures (CH) may be arranged to alternate with each other in the first direction (X) and the second direction (Y). A plurality of channel structures (CH) arranged in a zigzag shape can further improve the integration of a semiconductor memory device. In some embodiments, a plurality of channel structures (CH) may be arranged in a honeycomb shape.

In some embodiments, a dummy channel structure (DCH) may be formed within the mold structure (MS) in the boundary region (BR). The dummy channel structure (DCH) is formed in a similar shape to the channel structure (CH) and can reduce the stress applied to the mold structure (MS) in the boundary region (BR).

In some embodiments, a supporter structure (SS) may be formed within the mold structure (MS) of the extended area (EXT). The supporter structure (SS) may surround the cell contact (CCT) from a plan view perspective. The supporter structure (SS) is formed in a similar shape to the channel structure (CH) and can reduce the stress applied to the mold structure (MS) in the extended area (EXT).

In some embodiments, the information storage layer 132 may be formed as a multilayer. For example, as shown in FIG. 7, the information storage layer 132 includes a tunnel insulating layer 132a, a charge storage layer 132b, and a blocking insulating layer 132c that are sequentially stacked on the outer surface of the semiconductor pattern 130. It can be included.

The tunnel insulating film 132a may include, for example, silicon oxide or a high dielectric constant material (eg, aluminum oxide (Al ₂ O ₃ ) or hafnium oxide (HfO ₂ )) having a higher dielectric constant than silicon oxide. The charge storage layer 132b may include, for example, silicon nitride. The blocking insulating film 132c may include, for example, silicon oxide or a high dielectric constant material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al ₂ O ₃ ) or hafnium oxide (HfO ₂ )).

In some embodiments, the channel structure (CH) may further include a filling pattern (134). The filling pattern 134 may be formed to fill the interior of the cup-shaped semiconductor pattern 130. The filling pattern 134 may include an insulating material, for example, silicon oxide, but is not limited thereto.

In some embodiments, the channel structure (CH) may further include a channel pad 136. The channel pad 136 may be formed to be connected to the semiconductor pattern 130 . For example, the channel pad 136 may be formed in the first interlayer insulating film 120, which will be described later, and connected to the top of the semiconductor pattern 130. The channel pad 136 may include, for example, polysilicon doped with impurities, but is not limited thereto.

In some embodiments, a source layer 102, a source support layer 104, and a source sacrificial layer 106 may be disposed on the substrate 100. The source layer 102 and the source sacrificial layer 106 may be interposed between the substrate 100 and the mold structure MS. For example, the source layer 102 and the source sacrificial layer 106 may extend along the top surface 100US of the substrate 100.

Specifically, the source layer 102 is disposed on the substrate 100 in the cell array area (CAR). A portion of the source layer 102 may be disposed on the substrate 100 in the boundary region BR, but is not limited thereto. In some embodiments, the source layer 102 may be formed to be connected to the semiconductor pattern 130 of the channel structure (CH). For example, as shown in FIG. 7 , the source layer 102 may penetrate the information storage layer 132 and contact the semiconductor pattern 130 . For example, the source layer 102 may penetrate the sidewall of the information storage layer 132 and be connected to the semiconductor pattern 130.

This source layer 102 may be provided as a common source line (eg, CSL in FIG. 2) of a semiconductor memory device. The source layer 102 may be formed of, for example, a polysilicon film doped with impurities or a conductive film, but is not limited thereto.

In some embodiments, the channel structure (CH) and the dummy channel structure (DCH) may penetrate the source layer 102 and the source support layer 104, respectively. For example, the lower portion of the channel structure CH and the lower portion of the dummy channel structure DCH may penetrate the source layer 102 and the source support layer 104 and be buried in the substrate 100 .

The source sacrificial layer 106 is disposed on the substrate 100 in the extended area EXT. A portion of the source sacrificial layer 106 is shown as not being disposed on the substrate 100 in the boundary region BR, but this is only for convenience of explanation and is not limited thereto. Of course, unlike what is shown, the source sacrificial layer 106 may be disposed in the boundary region BR.

5 and 10 , the source sacrificial layer 106 may include a first layer 106a, a second layer 106b, and a third layer 106c that are sequentially stacked. The first layer 106a may contact the top surface 100US of the substrate 100. The third layer 106c may be in contact with the source support layer 104. The second layer 106b may be disposed between the first layer 106a and the third layer 106c.

In some embodiments, the source layer 102 may be formed at a location where the source sacrificial layer 106 disposed on the substrate 100 in the cell array region CAR is removed. That is, when the source layer 102 is formed, the source sacrificial layer 106 on the substrate 100 in the cell array region (CAR) is removed, and the source sacrificial layer 106 on the substrate 100 in the extension region (EXT) is removed. ) may not be removed.

The source sacrificial layer 106 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the first layer 106a and the third layer 106c may each be formed of a silicon oxide film, and the second layer 106c may be formed of a silicon nitride film, but are not limited thereto.

The source support layer 104 may fill between the source layer 102 and the source sacrificial layer 106. Additionally, the source support layer 104 may cover the source layer 102 and the source sacrificial layer 106. In some embodiments, the source support layer 104 may be used as a support layer to prevent the mold stack from collapsing or collapsing during a replacement process to form the source layer 102.

5 and 10 , the top surface 104US of the source support layer 104 may include a first portion 104US1, a second portion 104US2, and a third portion 104US3.

The first portion 104US1 may extend in the first direction (X) and/or the second direction (Y). The first portion 104US1 may be parallel to the top surface 100US of the substrate 100. The first portion 104US1 may extend parallel to the upper surface 100US of the substrate 100.

The second part 104US2 may be spaced apart from the first part 104US1. The second part 104US2 may be spaced apart from the first part 104US1 in the first direction (X) and/or the second direction (Y). The second portion 104US2 may extend in the first direction (X) and/or the second direction (Y). The second portion 104US2 may be parallel to the top surface 100US and the first portion 104US1 of the substrate 100. The second part 104US2 may extend parallel to the upper surface 100US and the first part 104US1 of the substrate 100.

The third part 104US3 may connect the first part 104US1 and the second part 104US2. The third portion 104US3 may extend in directions different from the first direction (X), the second direction (Y), and the third direction (Z). That is, the third portion 104US3 may not be parallel to the top surface 100US of the substrate 100.

In some embodiments, the first portion 104US1 may be the top of the top surface 104US of the source support layer 104. The second portion 104US2 may be the lowermost portion of the top surface 104US of the source support layer 104. In this specification, “top” may mean a portion disposed at the highest vertical level based on the top surface 100US of the substrate 100. In this specification, “lowest part” may mean a portion disposed at the lowest vertical level based on the top surface 100US of the substrate 100.

In some embodiments, the top surface 104US of the source support layer 104 may have a step. For example, the vertical level of the first portion 104US1 of the top surface 104US of the source support layer 104 may be different from the vertical level of the second portion 104US2 of the top surface 104US of the source support layer 104. . For example, the vertical level of the first part 104US1 may be higher than the vertical level of the second part 104US2.

In other words, the vertical distance from the top surface 100US of the substrate 100 to the first portion 104US1 is greater than the second vertical distance d2 from the top surface 100US of the substrate 100 to the second portion 104US2. You can. Additionally, the fourth vertical distance d4 from the first part 104US1 to the second part 104US2 may be greater than 0. For example, the fourth vertical distance d4 from the first part 104US1 to the second part 104US2 may be greater than 0 and less than or equal to 50 Å. However, the present invention is not limited to this. In the semiconductor memory device according to some embodiments, since the fourth vertical distance d4 is 50 Å or less, process margin may be improved in the process of forming the word line truncation structure (WLC), which will be described later.

In some embodiments, the first vertical distance d1 from the top surface 102US of the source layer 102 to the first portion 104US1 is equal to the distance d1 from the top surface 100US of the substrate 100 to the second portion 104US2. It is smaller than the second vertical distance (d2). That is, the thickness of the source layer 102 in the third direction (Z) may be greater than the fourth vertical distance (d4). In addition, the third vertical distance d3 from the top surface 106US of the source sacrificial layer 106 to the first portion 104US1 is the second vertical distance d3 from the top surface 100US of the substrate 100 to the second portion 104US2. It is smaller than the vertical distance (d2). That is, the thickness of the source sacrificial layer 106 in the third direction (Z) may be greater than the fourth vertical distance (d4).

In some embodiments, the minimum distance d5 from the top surface 102US of the source layer 102 to the third portion 104US3 may be equal to the second vertical distance d2. In this specification, “minimum distance from A to B” may mean the shortest distance among the distances from A to the plane including B.

Likewise, the minimum distance d6 from the top surface 106US of the source sacrificial layer 106 to the third portion 104US3 may be equal to the second vertical distance d2. That is, the minimum distance d5 from the top surface 102US of the source layer 102 to the third part 104US3 and the minimum distance from the top surface 106US of the source sacrificial layer 106 to the third part 104US3 ( d6) may be identical to each other. However, the technical idea of the present invention is not limited thereto.

As the semiconductor memory device according to some embodiments has the above-described structure, the process margin may be improved in the process of forming the word line cut structure (WLC), which will be described later. Accordingly, a semiconductor memory device with improved reliability can be manufactured.

The source support layer 104 may be formed of a polysilicon film not doped with impurities, but is not limited thereto. Although not shown, a base insulating film may be interposed between the substrate 100 and the source layer 102. For example, the base insulating layer may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

The word line cutting structure (WLC) can cut the mold structure (MS). The word line cutting structure (WLC) can cut the gate electrodes (ECL, GSL, WL1 to WLn, and SSL). The mold structure MS may be cut by the word line cut structure WLC to form a plurality of memory cell blocks (eg, BLK1 to BLKn in FIG. 1). For example, although not shown, two adjacent word line truncation structures (WLCs) may define a block of memory cells between them. A plurality of channel structures (CH) may be disposed within each memory cell block defined by word line truncation structures (WLC).

In some embodiments, the word line cutting structure (WLC) can cut the source layer 102 and the source support layer 104. In the cell array area (CAR), the bottom surface (WLC_BS) of the word line cut structure (WLC) is shown to be disposed only between the bottom surface of the source layer 102 and the top surface 102US of the source layer 102. It is just an example. As another example, the bottom surface (WLC_BS) of the word line cut structure (WLC) may be disposed at a vertical level lower than the bottom surface of the source layer 102.

In FIG. 8, the vertical level and extension area (EXT) of the bottom surface (WLC_BS) of the word line cut structure (WLC) on the substrate 100 in the cell array area (CAR) based on the top surface (100US) of the substrate 100 The vertical level of the bottom surface (WLC_BS) of the word line cut structure (WLC) on the substrate 100 may be different.

Specifically, the vertical level of the bottom surface (WLC_BS) of the word line cutting structure (WLC) on the substrate 100 in the cell array area (CAR) is the vertical level of the word line cutting structure (WLC) on the substrate 100 in the extension region (EXT). It may be lower than the vertical level of the floor surface (WLC_BS). This may be because an etching process is additionally performed when forming the word line cut structure (WLC) on the substrate 100 in the cell array area (CAR). Accordingly, at least a portion of the word line cut structure (WLC) on the substrate 100 in the cell array area (CAR) may be disposed in the source layer 102.

In addition, the bottom surface (WLC_BS) of the word line cut structure (WLC) on the substrate 100 in the cell array area (CAR) is in contact with the source layer 102, and the word line on the substrate 100 in the extension area (EXT) The bottom surface (WLC_BS) of the cutting structure (WLC) may be in contact with the source support layer 104, but is not limited thereto.

9 and 10 , the word line cut structure (WLC) on the substrate 100 in the extended area (EXT) may not contact the source sacrificial layer 106. The word line cut structure (WLC) on the substrate 100 in the extended area (EXT) does not overlap the source sacrificial layer 106 in the third direction (Z). In addition, the word line cut structure (WLC) on the substrate 100 in the extension area (EXT) is shown as not overlapping the source sacrificial layer 106 in the second direction (Y), but the technical idea of the present invention is limited to this. It doesn't work.

At this time, the vertical level of the bottom surface (WLC_BS) of the word line cut structure (WLC) on the substrate 100 in the extension area (EXT) may be higher than the vertical level of the top surface (106US) of the source sacrificial layer 106. That is, the vertical distance in the third direction (Z) from the top surface of the substrate 100 to the bottom surface (WLC_BS) of the word line cut structure (WLC) on the substrate 100 in the extension area (EXT) is the length of the substrate 100. It may be greater than the vertical distance in the third direction (Z) from the top surface to the top surface 106US of the source sacrificial layer 106. However, the technical idea of the present invention is not limited thereto.

In some embodiments, the wordline truncation structure (WLC) may include an insulating material. For example, the insulating material may fill a wordline truncation structure (WLC). The insulating material may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

In some embodiments, in the cross section of FIG. 9, the word line WLk disposed at the uppermost level may be the kth word line. However, the technical idea of the present invention is not limited thereto.

3 and 6, a string separation structure (SC) may be provided within the mold structure (MS). The string separation structure (SC) can cut the string selection line (SSL). Each memory cell block defined by word line truncation structures (WLC) may be divided by the string separation structure (SC) to form a plurality of string regions. For example, the string separation structure SC may define two string areas within one memory cell block. The string separation structure (SC) may include an insulating material. For example, the string separation structure SC may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto.

The first interlayer insulating film 120 may be disposed on the mold structure MS. The first interlayer insulating film 120 may cover a plurality of channel structures (CH), a plurality of dummy channel structures (DCH), and a plurality of cell contacts (CCT). The first interlayer insulating film 120 may include an oxide-based insulating material. The first interlayer insulating film 120 may include, but is not limited to, at least one of, for example, silicon oxide, silicon oxynitride, and a low-k material with a lower dielectric constant than silicon oxide.

A second interlayer insulating film 140 may be disposed on the first interlayer insulating film 120 . The second interlayer insulating film 140 may cover the bit line BL and the plurality of metal patterns 170 . The second interlayer insulating film 140 may include an oxide-based insulating material. The second interlayer insulating film 140 may include, but is not limited to, at least one of, for example, silicon oxide, silicon oxynitride, and a low-k material with a lower dielectric constant than silicon oxide.

The bit line BL may be disposed on the substrate 100 in the cell array area CAR. The bit line BL may be formed on the mold structure MS. The bit line BL may be a bit line (BL in FIG. 2) of a semiconductor memory device. The bit line BL may be disposed within the second interlayer insulating film 140 . The bit line BL may extend in the second direction (Y).

Additionally, the bit line (BL) may be connected to a plurality of channel structures (CH). For example, first and second bit line contacts 150 and 161 connected to the top of each channel structure CH may be formed in the first interlayer insulating film 120. The first bit line contact 150 is disposed on the channel structure (CH). The first bit line contact 150 may be connected to the channel pad 136. The second bit line contact 161 is disposed on the first bit line contact 150. The second bit line contact 161 may be connected to the bit line BL. The second bit line contact 161 may be provided between the bit line BL and the first bit line contact 150. The bit line BL may be electrically connected to the channel structures CH through the first and second bit line contacts 150 and 161.

The bit line BL may not be disposed on the mold structure MS in the boundary area BR. The bit line (BL) may not be connected to the dummy channel structure (DCH).

The bit line BL may include a conductive material. For example, the bit line BL may include, but is not limited to, tungsten (W) or copper (Cu).

A plurality of cell contacts (CCT) may be provided on the substrate in the extended area (EXT). The plurality of cell contacts CCT may extend in the third direction Z in the extension area EXT and penetrate the first interlayer insulating layer 120 . Each of the plurality of cell contacts (CCT) may be connected to one of the plurality of gate electrodes. For example, each of the plurality of cell contacts (CCT) may land on a gate electrode disposed at the highest level among the plurality of gate electrodes. That is, each of the plurality of cell contacts (CCT) may be electrically connected to the gate electrode disposed at the highest level among the plurality of gate electrodes.

The upper surfaces of each of the plurality of cell contacts (CCTs) may be arranged on a coplanar surface. Additionally, the bottom surfaces of each of the plurality of cell contacts (CCTs) may be arranged on a coplanar surface. However, the technical idea of the present invention is not limited thereto.

A plurality of metal patterns 170 may be disposed on the substrate 100 in the extended area EXT. A plurality of metal patterns 170 may be disposed on the mold structure MS in the extended area EXT. The top surface of the plurality of metal patterns 170 may be placed on the same plane as the top surface of the bit line BL. The plurality of metal patterns 170 may be connected to each of the plurality of cell contacts (CCT). For example, a via contact 163 may be formed between the plurality of metal patterns 170 and each cell contact (CCT). The plurality of metal patterns 170 and each cell contact (CCT) may be electrically connected through the via contact 163.

The plurality of metal patterns 170 may include a conductive material. For example, the plurality of metal patterns 170 may include tungsten (W) or copper (Cu), but is not limited thereto.

In some embodiments, the peripheral circuit structure PERI may include a peripheral circuit board 200 and a peripheral circuit element PT.

The peripheral circuit board 200 may be disposed below the substrate 100. For example, the upper surface of the peripheral circuit board 200 may face the lower surface of the substrate 100. The peripheral circuit board 200 may include, for example, a semiconductor substrate such as a silicon substrate, germanium substrate, or silicon-germanium substrate. Alternatively, the peripheral circuit board 200 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

Peripheral circuit elements PT may be formed on the peripheral circuit board 200 . The peripheral circuit element PT may constitute a peripheral circuit (eg, 30 in FIG. 1 ) that controls the operation of the semiconductor memory device. For example, the peripheral circuit element PT may include control logic (e.g., 37 in FIG. 1), a row decoder (e.g., 33 in FIG. 1), and a page buffer (e.g., 35 in FIG. 1). In the following description, the surface of the peripheral circuit board 200 on which the peripheral circuit element PT is disposed may be referred to as the front side of the peripheral circuit board 200. Conversely, the surface of the peripheral circuit board 200 opposite to the front surface of the peripheral circuit board 200 may be referred to as the back side of the peripheral circuit board 200.

The peripheral circuit element PT may include, for example, a transistor, but is not limited thereto. For example, peripheral circuit elements (PT) may include various active elements such as transistors, as well as various passive elements such as capacitors, resistors, and inductors. It may be possible.

In some embodiments, the rear surface of the substrate 100 may face the front surface of the peripheral circuit board 200. For example, an inter-wiring insulating film 220 may be formed on the front surface of the peripheral circuit board 200 to cover the peripheral circuit elements PT. The substrate 100 may be stacked on the upper surface of the inter-wiring insulating film 220 .

Peripheral circuit elements PT may be separated by a peripheral element isolation film 205. For example, a peripheral device isolation layer 205 may be provided within the peripheral circuit board 200. The peripheral isolation film 205 may be a shallow trench isolation (STI) film. The peripheral device isolation layer 205 may define an active area of the peripheral circuit devices PT. The peripheral device isolation layer 205 may include an insulating material. For example, the peripheral device isolation layer 205 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

The peripheral circuit structure PERI may further include a plurality of wiring patterns 232 and a plurality of wiring contacts 231. The plurality of wiring patterns 232 and the plurality of wiring contacts 231 may be electrically connected to each other. The plurality of wiring patterns 232 and the plurality of wiring contacts 231 may electrically connect the peripheral circuit element PT and other components in the cell structure CELL. Each of the plurality of wiring patterns 232 and the plurality of wiring contacts 231 may include a conductive material. For example, each of the plurality of wiring patterns 232 and the plurality of wiring contacts 231 may include tungsten (W) or copper (Cu), but is not limited thereto.

Hereinafter, several other embodiments of the semiconductor memory device of the present invention will be described with reference to FIGS. 11 to 17. For convenience of explanation, the description will focus on differences from those described using FIGS. 3 to 10.

11 to 15 are exemplary diagrams for explaining semiconductor memory devices according to some other embodiments. For reference, FIG. 11 may be an exemplary enlarged view of the R region of FIG. 9. FIG. 12 may be an exemplary cross-sectional view taken along line A-A of FIG. 3, and FIG. 13 may be an enlarged view of area P' of FIG. 12. FIG. 14 may be an exemplary cross-sectional view taken along line D-D of FIG. 3, and FIG. 15 may be an enlarged view of region R' of FIG. 14.

First, referring to FIG. 11, the vertical level of the bottom surface (WLC_BS) of the word line cut structure (WLC) on the substrate 100 in the extension region (EXT) is the vertical level of the top surface (106US) of the source sacrificial layer 106. It can be lower.

That is, the vertical distance in the third direction (Z) from the top surface of the substrate 100 to the bottom surface (WLC_BS) of the word line cut structure (WLC) on the substrate 100 in the extension area (EXT) is the length of the substrate 100. It may be smaller than the vertical distance in the third direction (Z) from the top surface to the top surface 106US of the source sacrificial layer 106. However, the technical idea of the present invention is not limited thereto.

A portion of the word line cut structure (WLC) on the substrate 100 in the extended area (EXT) may overlap the source sacrificial layer 106 in the second direction (Y). However, the technical idea of the present invention is not limited thereto.

Referring to FIGS. 12 to 15 , the top surface 104US of the source support layer 104 may not have a step. The vertical level of the top surface 104US of the source support layer 104 may be constant from the cell array area CAR toward the extension area EXT. That is, the first to third parts (104US1, 104US2, and 104US3 in FIG. 5) of the top surface 104US of the source support layer 104 may all lie on the same plane.

In some embodiments, a free source support layer (104_p in FIG. 23) is formed, and the free source support layer may be removed through a chemical mechanical polishing (CMP) process. The free source support layer may be removed to form the source support layer 104. At this time, if the pre-source support layer is over-etched, the upper surface 104US of the source support layer 104 may not have a step.

FIG. 16 is an example diagram for explaining a semiconductor memory device according to some other embodiments. For reference, FIG. 16 may be an exemplary cross-sectional view taken along line B-B of FIG. 3.

Referring to FIG. 16, a semiconductor memory device according to some embodiments may be a 2 stack semiconductor memory device. For example, the mold structure MS may include a lower mold structure MS1 and an upper mold structure MS2. The upper mold structure MS2 may be disposed on the lower mold structure MS1.

The lower mold structure MS1 may include a plurality of lower gate electrodes (ECL, GSL, WL11 to WL1n) and a plurality of lower mold insulating films 110a that are alternately stacked on the substrate 100. The plurality of lower gate electrodes (ECL, GSL, WL11 to WL1n) and the plurality of lower mold insulating films 110a may have a layered structure extending parallel to the upper surface of the substrate 100. The lower gate electrodes (ECL, GSL, WL11 to WL1n) may be stacked in a stepped shape in the extension area (EXT). For example, the lower gate electrodes (ECL, GSL, WL11 to WL1n) may extend to different lengths in the first direction (X) and have a step difference. In some embodiments, the lower gate electrodes (ECL, GSL, WL11 to WL1n) may have a step in the second direction (Y).

The upper mold structure MS2 may include a plurality of upper gate electrodes (WL21 to WL2n, SSL) and a plurality of upper mold insulating films 110b that are alternately stacked on the lower mold structure MS1. The plurality of upper gate electrodes (WL21 to WL2n, SSL) and the plurality of upper mold insulating films 110b may have a layered structure extending parallel to the upper surface of the substrate 100. The upper gate electrodes (WL21 to WL2n, SSL) may be stacked in a stepped shape in the extension area (EXT). For example, the upper gate electrodes (WL21 to WL2n, SSL) may extend to different lengths in the first direction (X) and have a step difference. In some embodiments, the upper gate electrodes (WL21 to WL2n, SSL) may have a step in the second direction (Y).

In some embodiments, the first interlayer insulating film 120 may include a lower interlayer insulating film 120a and an upper interlayer insulating film 120b. The upper interlayer insulating film 120b may be disposed on the lower interlayer insulating film 120a. Each of the lower interlayer insulating film 120a and the upper interlayer insulating film 120b may include, for example, at least one of silicon oxide, silicon oxynitride, and a low-k material with a dielectric constant smaller than silicon oxide. It is not limited.

FIG. 17 is an example diagram for explaining a semiconductor memory device according to some other embodiments. For reference, FIG. 17 may be an exemplary cross-sectional view taken along line A-A of FIG. 3.

Referring to FIG. 17 , in a semiconductor memory device according to some embodiments, the front surface of the substrate 100 faces the front surface of the peripheral circuit board 200.

For example, a semiconductor memory device according to some embodiments may have a C2C (chip to chip) structure. The C2C structure manufactures an upper chip including a cell structure (CELL) on a first wafer (e.g., substrate 100), and manufactures an upper chip including a cell structure (CELL) on a second wafer (e.g., peripheral circuit board 200) that is different from the first wafer. This means manufacturing a lower chip including a peripheral circuit structure (PERI) and then connecting the upper chip and the lower chip to each other by a bonding method.

For example, the bonding method electrically connects the bit line BL and a plurality of metal patterns 170 formed on the uppermost metal layer of the upper chip and the bonding metal 270 formed on the uppermost metal layer of the lower chip. It can mean a method. For example, when the bit line BL, the plurality of metal patterns 170, and the bonding metal 270 are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. However, this is only an example, and the bit line BL, the plurality of metal patterns 170, and the bonding metal 270 may each be formed of various other metals such as aluminum (Al) or tungsten (W). Of course.

As the bit line BL and the bonding metal 270 are connected, and the plurality of metal patterns 170 and the bonding metal 270 are connected, the cell structure CELL and the peripheral circuit structure PERI are electrically connected. You can. For example, the bit line BL and the wiring pattern 232, and the plurality of metal patterns 170 and the wiring pattern 232 may be connected to each other through the bonding metal 270 and the bonding contact 260, respectively. . Through this, each of the gate electrodes (ECL, GSL, WL1 to WLn, SSL) and/or the source layer 102 may be electrically connected to the peripheral circuit element PT.

Hereinafter, a method of manufacturing a semiconductor memory device according to some embodiments will be described with reference to FIGS. 18 to 26. FIGS. 18 to 26 are diagrams sequentially showing the process of manufacturing a semiconductor memory device having the cross-section of FIGS. 4 and 5. For reference, FIGS. 19 to 26 may be enlarged views of area P in FIG. 18.

First, referring to FIGS. 18 and 19, a peripheral circuit board 200 is provided. A peripheral device isolation layer 205 is formed within the peripheral circuit board 200. The peripheral device isolation layer 205 may define a source/drain region within the peripheral circuit board 200.

Subsequently, a peripheral circuit element PT, a plurality of wiring contacts 231, and a plurality of wiring patterns 232 may be formed on the peripheral circuit board 200. Subsequently, an insulating film 220 between interconnections may be formed covering the peripheral circuit element PT, the plurality of interconnection contacts 231, and the plurality of interconnection patterns 232.

The substrate 100 may be provided on the inter-wiring insulating film 220 . A free source sacrificial layer 106_p may be formed on the upper surface 100US of the substrate 100. The free source sacrificial layer 106_p may be a multilayer. For example, the free source sacrificial layer 106_p may include a free first layer 106a_p, a free second layer 106b_p, and a free third layer 106c_p. The free first layer 106a_p may contact the top surface 100US of the substrate 100. The free second layer 106b_p may be formed on the free first layer 106a_p. And the free third layer 106c_p may be formed on the free second layer 106b_p.

In some embodiments, the free first layer 106a_p and the free third layer 106c_p may be formed of the same material. For example, the free first layer 106a_p and the free third layer 106c_p may each be formed of a silicon oxide film. The free second layer 106b_p may be formed of a material different from the free first layer 106a_p and the free third layer 106c_p. For example, the free second layer 106b_p may be formed of a silicon oxide film. However, the technical idea of the present invention is not limited thereto. The free second layer 106b_p may have an etch selectivity with the free first layer 106a_p and the free third layer 106c_p.

Referring to FIG. 20 , a first recess RC1 may be formed by etching a portion of the pre-source sacrificial layer 106_p. The free source sacrificial layer 106_p may be etched to expose the upper surface 100US of the substrate 100. The first recess RC1 may be a landing portion of the word line cut structure WLC to be formed later.

Referring to FIG. 21 , the second recess RC2 may be formed by etching a portion of the free second layer 106b_p of the free source sacrificial layer 106_p. The free second layer 106b_p of the free source sacrificial layer 106_p may be removed through a wet etching process. The free second layer 106b_p may have an etch selectivity with the free first layer 106a_p and the free third layer 106c_p. Accordingly, while the free second layer 106b_p is removed, the free first layer 106a_p and the free third layer 106c_p may not be removed. The free second layer 106b_p may be selectively removed.

Referring to FIG. 22, a sacrificial insulating layer 108 may be formed. The sacrificial insulating layer 108 may fill the second recess RC2. The sacrificial insulating layer 108 may include an oxide-based insulating material. The sacrificial insulating film 108 may be formed of, for example, a silicon oxide film, but is not limited thereto.

Referring to FIG. 23, a free source support layer 104_p may be formed on the substrate 100. The free source support layer 104_p may cover the top surface of the free source sacrificial layer 106_p. A portion of the free source support layer 104_p may contact the top surface 100US of the substrate 100.

The free source support layer 104_p may be formed conformally. The free source support layer 104_p may have a constant thickness. For example, the thickness of the free source support layer 104_p may be about 1000Å, but is not limited thereto.

The free source support layer 104_p may be formed of a silicon film. For example, the free source support layer 104_p may be formed of a polysilicon film not doped with impurities, but is not limited thereto.

Referring to FIG. 24, a capping insulating layer 105 may be formed on the free source support layer 104_p. The capping insulating layer 105 may completely cover the free source support layer 104_p. The capping insulating film 105 may include an oxide-based insulating material. The capping insulating layer 105 may include the same material as the first interlayer insulating layer 120 in FIG. 4 . For example, the capping insulating film 105 may include at least one of silicon oxide, silicon oxynitride, and a low-k material with a dielectric constant smaller than that of silicon oxide, but is not limited thereto.

Referring to FIG. 25 , a portion of the capping insulating film 105 may be removed to expose the free source support layer 104_p. The capping insulating film 105 may be removed through a chemical mechanical polishing (CMP) process. If the free source support layer 104_p is exposed while removing the capping insulating film 105 by performing a chemical mechanical polishing process, the chemical mechanical polishing process may be stopped.

Referring to FIG. 26 , the source support layer 104 may be formed by removing a portion of the free source support layer 104_p. The free source support layer 104_p may be removed through a chemical mechanical polishing (CMP) process. As the free source support layer 104_p is removed, a portion of the capping insulating layer 105 may also be removed. That is, the top of the top surface 104US of the source support layer 104 may lie on the same plane as the top surface of the capping insulating layer 105. The lowermost portion of the upper surface 104US of the source support layer 104 may lie on the same plane as the lower surface of the capping insulating layer 105.

The top surface 104US of the source support layer 104 may include a first portion 104US1, a second portion 104US2, and a third portion 104US3. The first portion 104US1 may be the top of the top surface 104US of the source support layer 104. The second portion 104US2 may be the lowermost portion of the top surface 104US of the source support layer 104. The third part 104US3 may connect the first part 104US1 and the second part 104US2.

The first portion 104US1 may be placed on the same plane as the top surface of the capping insulating layer 105. The second portion 104US2 may be placed on the same plane as the lower surface of the capping insulating layer 105. The third portion 104US3 may contact the sidewall of the capping insulating film 105.

Since the free source support layer 104_p is removed through a chemical mechanical polishing process, the fourth vertical distance d4 between the first part 104US1 and the second part 104US2 may be 50 Å or less. Since the fourth vertical distance d4 is 50 Å or less, the process margin of the subsequent process of forming the word line cut structure (WLC) can be improved.

Referring to FIGS. 4 and 5 , the free source sacrificial layer 106_p disposed on a portion of the cell array area CAR and the boundary area BR may be removed. A source layer 102 may be formed in an area where the free source sacrificial layer 106_p has been removed.

Hereinafter, an electronic system including a semiconductor memory device according to example embodiments will be described with reference to FIGS. 1 to 10 and FIGS. 27 to 29 .

Figure 27 is an example block diagram for explaining an electronic system according to some embodiments. Figure 28 is an example perspective view for explaining an electronic system according to some embodiments. FIG. 29 is a schematic cross-sectional view taken along line II of FIG. 28.

Referring to FIG. 27 , the electronic system 1000 according to some embodiments may include a semiconductor memory device 1100 and a controller 1200 electrically connected to the semiconductor memory device 1100. The electronic system 1000 may be a storage device including one or a plurality of semiconductor memory devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including one or a plurality of semiconductor memory devices 1100. .

The semiconductor memory device 1100 may be, for example, a NAND flash memory device, for example, the semiconductor memory device described above using FIGS. 1 to 10 . The semiconductor memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

The first structure 1100F includes a decoder circuit 1110 (e.g., row decoder 33 in FIG. 1), a page buffer 1120 (e.g., page buffer 35 in FIG. 1), and a logic circuit 1130 (e.g., FIG. 1). It may be a peripheral circuit structure including control logic 37).

The second structure 1100S may include a common source line (CSL), a plurality of bit lines (BL), and a plurality of cell strings (CSTR) described above with reference to FIG. 2 . The cell strings (CSTR) may be connected to the decoder circuit 1110 through a word line (WL), at least one string select line (SSL), and at least one ground select line (GSL). Additionally, cell strings (CSTR) may be connected to the page buffer 1120 through bit lines (BL).

In some embodiments, the common source line (CSL) and cell string (CSTR) are connected to the decoder circuit 1110 through first connection wires 1115 extending from the first structure 1100F to the second structure 1100S. Can be electrically connected.

In some embodiments, the bit lines BL may be electrically connected to the page buffer 1120 through second connection wires 1125 extending from the first structure 1100F to the second structure 1100S.

The semiconductor memory device 1100 may communicate with the controller 1200 through an input/output pad 1101 that is electrically connected to the logic circuit 1130 (e.g., control logic 37 of FIG. 1). The input/output pad 1101 may be electrically connected to the logic circuit 1130 through an input/output connection wire 1135 extending from the first structure 1100F to the second structure 1100S.

The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the electronic system 1000 may include a plurality of semiconductor memory devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor memory devices 1100.

The processor 1210 may control the overall operation of the electronic system 1000, including the controller 1200. The processor 1210 may operate according to predetermined firmware and may control the NAND controller 1220 to access the semiconductor memory device 1100. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor memory device 1100. Through the NAND interface 1221, control commands for controlling the semiconductor memory device 1100, data to be written to the memory cell transistors (MCT) of the semiconductor memory device 1100, and memory cells of the semiconductor memory device 1100. Data to be read from the transistors (MCT) may be transmitted. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When receiving a control command from an external host through the host interface 1230, the processor 1210 may control the semiconductor memory device 1100 in response to the control command.

27 to 29, an electronic system according to some embodiments includes a main board 2001, a main controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and DRAM 2004. may include. The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 through wiring patterns 2005 formed on the main substrate 2001.

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may include interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). You can communicate with an external host according to any one of the following. In some embodiments, the electronic system 2000 may operate with power supplied from an external host through the connector 2006. The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the main controller 2002 and the semiconductor package 2003.

The main controller 2002 can write data to the semiconductor package 2003 or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

DRAM (2004) may be a buffer memory to alleviate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 may operate as a type of cache memory and may provide space for temporarily storing data during control operations for the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the main controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b that are spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may each be a semiconductor package including a plurality of semiconductor chips 2200. The first semiconductor package 2003a and the second semiconductor package 2003b include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, and adhesive layers disposed on the lower surfaces of each of the semiconductor chips 2200. (2300), a connection structure 2400 that electrically connects the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100. ) may include.

The package substrate 2100 may be a printed circuit board including upper package pads 2130. Each semiconductor chip 2200 may include an input/output pad 2210. The input/output pad 2210 may correspond to the input/output pad 1101 of FIG. 27.

In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input/output pad 2210 and the top pads 2130 of the package. Accordingly, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire, and the package upper pads 2130 of the package substrate 2100 may be electrically connected to each other. ) can be electrically connected to. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 have a through electrode (Through Silicon Via, TSV) instead of the bonding wire-type connection structure 2400. ) may be electrically connected to each other by a connection structure including.

In some embodiments, the main controller 2002 and the semiconductor chips 2200 may be included in one package. In some embodiments, the main controller 2002 and the semiconductor chips 2200 are mounted on a separate interposer board different from the main board 2001, and the main controller 2002 and the semiconductor chips are connected by wiring formed on the interposer board. Chips 2200 may be connected to each other.

In some embodiments, package substrate 2100 may be a printed circuit board. The package substrate 2100 includes a package substrate body 2120, package upper pads 2130 disposed on the upper surface of the package substrate body 2120, and disposed on or exposed through the lower surface of the package substrate body 2120. may include lower pads 2125 and internal wires 2135 that electrically connect the upper pads 2130 and the lower pads 2125 inside the package substrate body 2120. The upper pads 2130 may be electrically connected to the connection structures 2400. The lower pads 2125 may be connected to the wiring patterns 2005 of the main board 2001 of the electronic system 2000 as shown in FIG. 27 through conductive connectors 2800.

Referring to FIGS. 28 and 29 , in an electronic system according to some embodiments, each of the semiconductor chips 2200 may include the semiconductor memory device described above using FIGS. 1 to 10 . For example, each of the semiconductor chips 2200 may include a peripheral circuit structure (PERI) and a cell structure (CELL) stacked on the peripheral circuit structure (PERI). Illustratively, the peripheral circuit structure PERI may include the peripheral circuit board 200 and the peripheral circuit elements PT described above using FIGS. 3 to 10 . In addition, by way of example, the cell structure (CELL) includes the substrate 100, mold structure (MS), channel structure (CH), word line cutting structure (WLC), and source layer ( 102), a source support layer 104, and a source sacrificial layer 106.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and can be manufactured in various different forms by those skilled in the art. It will be understood by those who understand that the present invention can be implemented in other specific forms without changing its technical spirit or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

100: substrate 102: source layer
104: Source support layer 106: Source victim layer
110: mold insulating film 120: first interlayer insulating film
CH: channel structure 136: channel pad
CCT: Cell Contact DCH: Dummy Channel Structure
CAR: Cell array area BR: Border area
EXT: Extension area BL: Bit line
WLC: Wordline truncation structure
200: Peripheral circuit board PT: Peripheral circuit element

Claims (10)

A substrate comprising a cell array area, an extension area, and a boundary area between the cell array area and the extension area;
A plurality of gate electrodes are sequentially stacked on the substrate in the cell array region and the boundary region, and are stacked in a step shape on the substrate in the extended region, and a plurality of mold insulating films are alternately stacked with the plurality of gate electrodes. A mold structure comprising;
On the substrate in the cell array area, a plurality of channel structures passing through the mold structure and intersecting the plurality of gate electrodes;
On the substrate in the boundary area, a plurality of dummy channel structures penetrating the mold structure;
A plurality of cell contacts connected to each of the plurality of gate electrodes on the substrate of the extended area;
a source layer disposed in the cell array area between the substrate and the mold structure and connected to the plurality of channel structures;
a source sacrificial layer disposed in the extended area between the mold structures of the substrate; and
a source support layer that fills between the source layer and the source sacrificial layer and covers the source layer and the source sacrificial layer;
The top surface of the source support layer includes a first part extending parallel to the top surface of the substrate, a second part spaced apart from the first part, and a third part connecting the first part and the second part,
A first vertical distance from the top surface of the source layer to the first portion is smaller than a second vertical distance from the top surface of the substrate to the second portion. According to clause 1,
Each of the plurality of channel structures is disposed within a channel hole,
Each of the plurality of channel structures includes an information storage film disposed along sidewalls and a bottom surface of the channel hole, and a semiconductor pattern on the information storage film,
The source layer penetrates the information storage film and is connected to the semiconductor pattern. According to clause 1,
A semiconductor memory device, wherein the first part is disposed at a higher level than the second part based on the top surface of the substrate. According to clause 3,
A semiconductor memory device wherein the vertical distance from the first portion to the second portion is 50 Å or less. According to clause 1,
The semiconductor memory device, wherein the first portion lies on the same plane as the second portion. According to clause 1,
A third vertical distance from the top surface of the source sacrificial layer to the first portion is smaller than the second vertical distance. According to clause 6,
The first vertical distance and the third vertical distance are equal to each other. According to clause 1,
A minimum distance from the top surface of the source layer to the third portion is equal to the second vertical distance. A substrate comprising a cell array area, an extension area, and a boundary area between the cell array area and the extension area;
A plurality of gate electrodes are sequentially stacked on the substrate in the cell array region and the boundary region, and are stacked in a step shape on the substrate in the extended region, and a plurality of mold insulating films are alternately stacked with the plurality of gate electrodes. A mold structure comprising;
On the substrate of the cell array area, a plurality of channel structures penetrate the mold structure and intersect the plurality of gate electrodes, each of the plurality of channel structures is disposed in a channel hole penetrating the mold structure, , a plurality of channel structures including an information storage film disposed along side walls and a bottom surface of the channel hole, and a semiconductor pattern on the information storage film;
On the substrate in the boundary area, a plurality of dummy channel structures penetrating the mold structure;
A plurality of cell contacts connected to each of the plurality of gate electrodes on the substrate of the extended area;
a word line cutting structure extending in a first direction on the substrate and cutting the plurality of gate electrodes;
a bit line connected to each of the plurality of channel structures on the mold structure and extending in a second direction;
a source layer disposed in the cell array region between the substrate and the mold structure and connected to the semiconductor pattern through a sidewall of the information storage layer;
a source sacrificial layer disposed in the extended area between the mold structures of the substrate; and
a source support layer that fills between the source layer and the source sacrificial layer and covers the source layer and the source sacrificial layer;
A first vertical distance from the top surface of the source layer to the top of the top surface of the source support layer is less than a second vertical distance from the top surface of the substrate to the bottom of the top surface of the source support layer,
A third vertical distance from the top surface of the source sacrificial layer to the top of the source support layer is smaller than the second vertical distance,
A semiconductor memory device wherein, with respect to the top surface of the substrate, the level of the bottom surface of the word line cut structure on the cell array area is different from the level of the bottom surface of the word line cut structure on the extension area. main board;
a semiconductor memory device on the main substrate; and
On the main board, it includes a controller electrically connected to the semiconductor memory device,
The semiconductor memory device,
A substrate comprising a cell array area, an extension area, and a boundary area between the cell array area and the extension area;
A plurality of gate electrodes are sequentially stacked on the substrate in the cell array region and the boundary region, and are stacked in a step shape on the substrate in the extended region, and a plurality of mold insulating films are alternately stacked with the plurality of gate electrodes. A mold structure comprising;
On the substrate in the cell array area, a plurality of channel structures passing through the mold structure and intersecting the plurality of gate electrodes;
On the substrate in the boundary area, a plurality of dummy channel structures penetrating the mold structure;
A plurality of cell contacts connected to each of the plurality of gate electrodes on the substrate of the extended area;
a source layer disposed in the cell array area between the substrate and the mold structure and connected to the plurality of channel structures;
a source sacrificial layer disposed in the extended area between the mold structures of the substrate; and
a source support layer that fills between the source layer and the source sacrificial layer and covers the source layer and the source sacrificial layer;
The top surface of the source support layer includes a first part extending parallel to the top surface of the substrate, a second part spaced apart from the first part, and a third part connecting the first part and the second part,
wherein a first vertical distance from the top surface of the source layer to the first portion is less than a second vertical distance from the top surface of the substrate to the second portion.

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