KR20230008542A - Method for fabricating semiconductor package - Google Patents

Abstract

According to a technical idea of the present invention, a method for manufacturing a semiconductor package comprises the steps of: forming a plurality of conductive vias in a first substrate; forming a first redistribution layer on an upper surface of the first substrate in which the plurality of conductive vias are exposed; attaching a second substrate on the first redistribution layer to face the first substrate with the first redistribution layer interposed therebetween; etching and removing the first substrate; mounting a semiconductor chip between the plurality of conductive vias on the first redistribution layer; forming a molding member to cover the plurality of conductive vias and the semiconductor chip; grinding the molding member to expose the plurality of conductive vias; and forming a second redistribution layer on the molding member. Accordingly, the plurality of conductive vias can be designed with a fine pitch.

Description

Manufacturing method of semiconductor package {METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE}

The technical field of the present invention relates to a method for manufacturing a semiconductor package, and more particularly, to a method for manufacturing a wafer level package including a redistribution layer.

Recently, the demand for portable electronic devices is rapidly increasing in the electronic product market, and as a result, miniaturization and light weight of electronic components mounted on portable electronic devices are continuously required. In order to reduce the size and weight of electronic components, the overall thickness of a semiconductor package is decreasing, but the demand for an increase in memory capacity continues to increase. Therefore, in order to efficiently arrange semiconductor chips within a structure of a limited semiconductor package, a wafer level package is being applied.

A problem to be solved by the technical idea of the present invention is a plurality of conductive vias electrically connecting the first redistribution layer and the second redistribution layer in a fan-out wafer level package (FO-WLP) An object of the present invention is to provide a method of manufacturing a semiconductor package capable of designing a plurality of conductive vias with a fine pitch by pre-forming them on a semiconductor substrate by using a method of forming a TSV (Through Silicon Via).

The problem to be solved by the technical idea of the present invention is not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A method of manufacturing a semiconductor package according to the technical idea of the present invention includes forming a plurality of conductive vias in a first substrate; forming a first redistribution layer on an upper surface of the first substrate where the plurality of conductive vias are exposed; attaching a second substrate on the first redistribution layer to face the first substrate with the first redistribution layer interposed therebetween; etching and removing the first substrate; mounting a semiconductor chip between the plurality of conductive vias on the first redistribution layer; forming a molding member to cover the plurality of conductive vias and the semiconductor chip; polishing the molding member to expose the plurality of conductive vias; and forming a second redistribution layer on the molding member.

A method of manufacturing a semiconductor package according to the technical idea of the present invention, in a fan-out wafer level package, uses a method of forming a plurality of conductive vias electrically connecting a first redistribution layer and a second redistribution layer to a semiconductor substrate using a method of forming TSVs. By forming the vias in advance, there is an effect of designing a plurality of conductive vias with a fine pitch.

1 is a block diagram illustrating a method of manufacturing a semiconductor package according to an embodiment of the inventive concept.
2 to 11 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept according to a process sequence.
12 is a plan view illustrating a semiconductor module including a semiconductor package according to an embodiment of the inventive concept.
13 is a configuration diagram illustrating a system of a semiconductor package according to an embodiment of the inventive concept.

Hereinafter, embodiments of the technical idea of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a method of manufacturing a semiconductor package according to an embodiment of the inventive concept.

Referring to FIG. 1 , a method of manufacturing a semiconductor package ( S10 ) may include a process sequence of first to eighth steps ( S110 to S180 ).

Recent semiconductor packages have limitations in accommodating all of the input/output terminals within the main surface of the semiconductor chip when the size of the semiconductor chip is reduced or the number of input/output terminals increases. Therefore, a fan-out wafer level package (FO-WLP) including the input/output terminals is obtained by extending a redistribution layer in the semiconductor package to a molding member forming an outer circumferential surface of the semiconductor chip. ) structure is being applied.

In the method (S10) of manufacturing a semiconductor package according to the technical idea of the present invention, among fan-out wafer level packages, in particular, redistribution is first formed on a substrate, and a semiconductor chip is later mounted on the formed redistribution. (Chip-Last) manufacturing method.

Specifically, the manufacturing method (S10) of a semiconductor package according to the technical idea of the present invention includes a first step (S110) of forming a plurality of conductive vias on a first substrate, and a first redistribution layer on the top surface of the first substrate. A second step of forming (S120), a third step of attaching a second substrate on the first redistribution layer to face the first substrate (S130), a fourth step of etching and removing the first substrate (S140), A fifth step of mounting a semiconductor chip between a plurality of conductive vias on one redistribution layer (S150), a sixth step of forming a molding member to cover the plurality of conductive vias and the semiconductor chip (S160), the plurality of conductive vias It may include a seventh step of polishing the molding member to be exposed ( S170 ), and an eighth step of forming a second redistribution layer on the molding member ( S180 ).

Here, when an embodiment can be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order reverse to the order described. The technical characteristics of each of the first to eighth steps (S110 to S180) will be described in detail with reference to FIGS. 2 to 11 to be described later.

2 to 11 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept according to a process sequence.

Referring to FIG. 2 , a step of forming a plurality of holes 101H to a predetermined depth from the upper surface 101T of the first substrate 101 is shown.

The first substrate 101 may have an upper surface 101T and a lower surface 101B. The first substrate 101 may include a semiconductor substrate such as silicon (Si), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). can

A mask pattern (not shown) is formed on the upper surface 101T of the first substrate 101, and the first substrate 101 is etched using the mask pattern as an etching mask to form a plurality of holes 101H. can form The plurality of holes 101H may be formed to a predetermined depth from the top surface 101T of the first substrate 101 .

The plurality of holes 101H may be formed in substantially the same manner as a process for forming through silicon vias (TSVs). Accordingly, the plurality of holes 101H may be designed to have a fine pitch.

In some embodiments, the plurality of holes 101H may be formed by an anisotropic etching process or a laser drilling process. The plurality of holes 101H may be formed to have various widths, depths, and shapes according to the type of semiconductor package. In some embodiments, as shown in the drawing, the plurality of holes 101H may be formed to have sidewalls perpendicular to the top surface 101T of the first substrate 101 .

In other embodiments, in the process of forming the plurality of holes 101H, sidewalls of the plurality of holes 101H are etched to have a predetermined inclination so that the upper width of the plurality of holes 101H is greater than the lower width. may be formed.

After forming the plurality of holes 101H in the first substrate 101, the mask pattern may be removed through an ashing and stripping process.

Referring to FIG. 3 , a barrier layer 111 conformally covering sidewalls and a bottom surface of a plurality of holes 101H (see FIG. 2 ) of a first substrate 101 is formed, and the plurality of holes 101H (see FIG. 2 ) are formed. 2) is filled with a metal material to form the plurality of conductive vias 110 .

The barrier layer 111 may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or a combination thereof. In some embodiments, a CVD process may be used to form the barrier layer 111 . For example, the barrier layer 111 may be formed of silicon oxide formed by a low pressure CVD process. The barrier layer 111 may have a thickness of about 500 Å to about 3000 Å.

A plurality of conductive vias 110 may be formed on the barrier layer 111 by filling insides of the plurality of holes 101H (see FIG. 2 ) with a metal material. The plurality of conductive vias 110 may be composed of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or a W alloy, and may be formed by, for example, an electroplating process. .

Polishing the resulting product including the plurality of conductive vias 110 by a chemical mechanical polishing (CMP) process until the upper surface 101T of the first substrate 101 is exposed, and the plurality of conductive vias 110 and the barrier layer 111 remain only inside the plurality of holes 101H (see FIG. 2).

Referring to FIG. 4 , a metal seed layer 120M is flatly formed on an upper surface 101T of a first substrate 101 and a first redistribution layer 130 is formed on the metal seed layer 120M. indicate steps.

The metal seed layer 120M may be formed of Cu, a Cu alloy, Co, Ni, Ru, Co/Cu, or Ru/Cu on the upper surface 101T of the first substrate 101, and the metal seed layer 120M ) may use a PVD process to form.

A first redistribution layer 130 may be formed on the metal seed layer 120M. A lower surface of the first redistribution layer 130, that is, a surface in contact with the metal seed layer 120M may be a flat surface. The first redistribution layer 130 may include a first redistribution conductive layer 131 and first redistribution vias 133 and a first redistribution insulating layer 132 surrounding them.

The first redistribution conductive layer 131 is formed of, for example, copper (Cu), nickel (Ni), gold (Au), chromium (Cr), titanium (Ti), or palladium (Pd), or these It can be formed from an alloy of Also, the first redistribution conductive layer 131 may be formed of a plurality of layers.

The first redistribution layer 131 formed of a plurality of layers may be connected to each other by a tapered first redistribution via 133 . In the process of forming the first redistribution via 133 , sidewalls may be formed to have a predetermined inclination as a result of the anisotropic etching process.

In addition, a first redistribution insulating layer 132 may be disposed around the first redistribution conductive layer 131 and the first redistribution via 133 . The first redistribution insulating layer 132 may be formed of polymer, benzocyclobutene, or resin, and may be formed of photosensitive polyimide if necessary. However, the material constituting the first redistribution insulating layer 132 is not limited thereto. For example, the first redistribution insulating layer 132 may be made of silicon oxide, silicon nitride, or silicon oxynitride.

Referring to FIG. 5 , the first substrate 101 is turned over so that the first redistribution layer 130 faces down, and the first substrate 101 faces the first substrate 101 with the first redistribution layer 130 interposed therebetween. Step 2 of attaching the substrate 102 is shown.

The second substrate 102 can support the first redistribution layer 130 composed of an insulating layer and a conductive layer and can be made of a material that is stable against an etching process. In some embodiments, when the second substrate 102 is to be separated and removed by laser ablation later, it may be a light-transmissive substrate.

The second substrate 102 may have an upper surface 102T and a lower surface 102B. An adhesive layer 102P may be disposed on the upper surface 102T of the second substrate 102 . The adhesive layer 102P may serve to attach the second substrate 102 to the first redistribution layer 130 . In some embodiments, the adhesive layer 102P may later be vaporized in response to laser irradiation so that the second substrate 102 may be separated from the first redistribution layer 130 .

The second substrate 102 may be made of a material different from that of the first substrate 101 . In some embodiments, the second substrate 102 may be a glass substrate. In other embodiments, the second substrate 102 is made of a heat-resistant organic polymer material such as polyimide, polyetheretherketone, polyethersulfone, or polyphenylene sulfide. It may be made, but is not limited thereto.

Referring to FIG. 6, the plurality of conductive vias 110 and the metal seed layer 120M (see FIG. 5) are exposed by removing the first substrate 101 (see FIG. 5), and the exposed metal seed layer 120M (see FIG. 5) 5) shows a step of forming the metal pattern layer 120 by etching.

As described above, the first substrate 101 (see FIG. 5 ) may be a silicon (Si) substrate. The first substrate 101 (see FIG. 5) is completely removed using a dry etching process. Here, the second substrate 102 is made of a material different from that of the first substrate 101 (see FIG. 5), and the second substrate 102 is made of a material having stability against the dry etching process, During the dry etching process, the first redistribution layer 130 may be supported with etch resistance.

As the first substrate 101 (see FIG. 5 ) is completely removed, the plurality of conductive vias 110 and the metal seed layer 120M (see FIG. 5 ) may be exposed. Specifically, the barrier layer 111 surrounding the plurality of conductive vias 110 may be exposed to the outside, and the metal seed layer 120M (see FIG. 5) in a portion where the plurality of conductive vias 110 are not formed is may be exposed to the outside.

The metal pattern layer 120 is formed between the plurality of conductive vias 110 and the first redistribution layer 130 by removing the externally exposed metal seed layer 120M (see FIG. 5) using a wet etching process. form

Referring to FIG. 7 , a semiconductor chip 140 is mounted between a plurality of conductive vias 110 on a first redistribution layer 130 and covers the plurality of conductive vias 110 and the semiconductor chip 140. It shows a step of forming the molding member 150 so as to be.

A central portion of the first redistribution layer 130 where the plurality of conductive vias 110 are not located may be a chip mounting area. In the step of forming the plurality of conductive vias 110 , the plurality of conductive vias 110 may be disposed on the first substrate 101 (see FIG. 5 ) to partition the chip mounting area. A semiconductor chip 140 may be mounted in the chip mounting area to be electrically connected to the first redistribution layer 130 using solder bumps 141 .

The semiconductor chip 140 may be a logic chip or a memory chip. The logic chip may be, for example, a microprocessor, an analog device, or a digital signal processor. In addition, the memory chip is, for example, a volatile memory chip such as DRAM (Dynamic Random Access Memory) or SRAM (Static RAM), PRAM (Phase-change RAM), MRAM (Magnetoresistive RAM), RRAM (Resistive RAM), Alternatively, it may be a non-volatile memory chip such as Ferroelectric RAM (FeRAM). In some embodiments, the semiconductor chip 140 may be a high bandwidth memory chip. In some embodiments, a plurality of semiconductor chips 140 may be disposed.

The semiconductor chip 140 may be understood as a concept including a semiconductor device having an integrated circuit. Specifically, the semiconductor chip 140 may include a semiconductor substrate. A circuit unit for realizing an integrated circuit function of the semiconductor chip 140 may be formed on an active surface of the semiconductor substrate through a semiconductor manufacturing process.

In addition, the semiconductor chip 140 may include a bump pad formed on the semiconductor substrate to extend the function of the circuit unit to the outside. The solder bumps 141 may be attached to the bump pads, and the solder bumps 141 may be electrically connected to the first redistribution layer 130 .

Subsequently, the molding member 150 may be formed to cover both the plurality of conductive vias 110 and the semiconductor chip 140 . The molding member 150 may serve to protect the semiconductor chip 140 from external influences such as contamination and impact. To perform this role, the molding member 150 may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin containing a reinforcing material such as an inorganic filler. Specifically, a molding material such as an epoxy mold compound or a photosensitive material such as a photo imagable encapsulant (PIE) may be used as the molding member 150 . In addition, the molding member 150 may be formed by processes such as compression molding, lamination, and screen printing.

The molding member 150 may cover both the plurality of conductive vias 110 and the semiconductor chip 140 . In other words, the molding member 150 has a thickness greater than the heights of the plurality of conductive vias 110 and the height of the semiconductor chip 140, fills the gap between the solder bumps 141, and substantially covers the first redistribution layer 130. It can be formed with the same width as.

Referring to FIG. 8 , a step of polishing a portion of the molding member 150 and a portion of the plurality of conductive vias 110 to expose the plurality of conductive vias 110 is shown.

A polishing and planarization process is performed using a grinder (GR). The polishing and planarization process may be a chemical mechanical polishing process. The grinder GR removes a portion of the plurality of conductive vias 110, a portion of the barrier layer 111, and a portion of the molding member 150 through a polishing and planarization process, so that the plurality of conductive vias 110 are formed. A flat surface with an upper surface exposed may be formed. In this case, the upper surface of the semiconductor chip 140 may not be exposed. That is, the thickness of the molding member 150 may still be greater than the height of the semiconductor chip 140 .

After the polishing and planarization processes are completed, top surfaces of the plurality of conductive vias 110 , the top surfaces of the barrier layer 111 , and the top surfaces of the molding member 150 may form a coplanar surface.

Referring to FIG. 9 , a step of forming the second redistribution layer 160 on the planarized plurality of conductive vias 110 and the molding member 150 is illustrated.

A second redistribution layer 160 electrically connected to the first redistribution layer 130 through the plurality of conductive vias 110 may be formed. A lower surface of the second redistribution layer 160 , that is, a surface in contact with the plurality of conductive vias 110 and the molding member 150 may be a flat surface. The second redistribution layer 160 may include a second redistribution conductive layer 161 and second redistribution vias 163 and a second redistribution insulating layer 162 surrounding them.

The second redistribution layer 161 is formed of, for example, copper (Cu), nickel (Ni), gold (Au), chromium (Cr), titanium (Ti), or palladium (Pd), or these It can be formed from an alloy of Also, the second redistribution conductive layer 161 may be formed in a plurality of layers.

The second redistribution layer 161 formed of a plurality of layers may be connected to each other by a tapered second redistribution via 163 . In the process of forming the second redistribution via 163 , sidewalls may be formed to have a predetermined inclination as a result of the anisotropic etching process.

In addition, a second redistribution insulating layer 162 may be disposed around the second redistribution conductive layer 161 and the second redistribution via 163 . The second redistribution insulating layer 162 may be formed of polymer, benzocyclobutene, or resin, and may be formed of photosensitive polyimide, if necessary. However, the material constituting the second redistribution insulating layer 162 is not limited thereto. For example, the second redistribution insulating layer 162 may be made of silicon oxide, silicon nitride, or silicon oxynitride.

Referring to FIGS. 10 and 11 together, a step of forming the semiconductor package 10 by separating the second substrate 102 (see FIG. 9 ) and attaching the first and second connection terminals 171 and 172 is shown. . Specifically, FIG. 11 is an enlarged cross-sectional view of portion AA of FIG. 10 .

In order to separate and remove the second substrate 102 (see FIG. 9), a laser may be irradiated to the second substrate 102 (see FIG. 9). The bonding force between the adhesive layer 102P (see FIG. 9) and the second substrate 102 (see FIG. 9) may be weakened by the irradiation of the laser, and the second substrate 102 (see FIG. 9) is first reassembled. It can be completely separated from the wiring layer 130 .

The first connection terminal 171 may be formed on the lower surface of the first redistribution layer 130 and the second connection terminal 172 may be formed on the upper surface of the second redistribution layer 160 . In some embodiments, the first and second connection terminals 171 and 172 may be formed of solder balls. The solder ball may be formed in a spherical shape and attached to the first and second redistribution layers 130 and 160 . In other embodiments, the first and second connection terminals 171 and 172 form a solder layer on the first and second redistribution layers 130 and 160, and the solder layer is formed by a reflow process. It can be melted and formed into a reflow solder layer.

The tapered first shape of the first redistribution vias 133 included in the first redistribution layer 130 and the tapered second shape of the second redistribution vias 163 included in the second redistribution layer 160 are They may be in opposite directions. This is because the second redistribution layer 160 is formed by inverting the first substrate 101 on which the first redistribution layer 130 is formed. Specifically, the first redistribution via 133 included in the first redistribution layer 130 has a trapezoidal shape, and the second redistribution via 163 included in the second redistribution layer 160 has an inverse shape. It may have a trapezoidal shape.

In addition, since the wet etching process of patterning the metal seed layer 120M (see FIG. 5) into the metal pattern layer 120 has an isotropic etching characteristic, the metal pattern layer 120 positioned below the plurality of conductive vias 110 ) Both sidewalls may have a rounded shape.

The semiconductor package 10 may be manufactured by the method of manufacturing a semiconductor package ( S10 , see FIG. 1 ) according to the technical concept of the present invention including the manufacturing step.

Recently, the demand for portable electronic devices is rapidly increasing in the electronic product market, and as a result, miniaturization and light weight of electronic components mounted on portable electronic devices are continuously required. Although the overall thickness of the semiconductor package 10 is decreasing in order to reduce the size and weight of electronic components, the demand for an increase in memory capacity continues to increase. Accordingly, a wafer level package is being applied to efficiently dispose the semiconductor chip 140 within the structure of the limited semiconductor package 10 .

In addition, according to the method (S10) of manufacturing a semiconductor package according to the technical idea of the present invention, in a fan-out wafer level package, a plurality of electrically connecting the first redistribution layer 130 and the second redistribution layer 160. By pre-forming the conductive vias 110 in the first substrate 101 using a through silicon via (TSV) forming method, the plurality of conductive vias 110 may be designed with a fine pitch.

Ultimately, when the semiconductor package 10 is manufactured by the method of manufacturing a semiconductor package ( S10 ) according to the technical idea of the present invention, productivity of the semiconductor package 10 and reliability of the semiconductor package 10 are improved.

12 is a plan view illustrating a semiconductor module including a semiconductor package according to an embodiment of the inventive concept.

Referring to FIG. 12 , a semiconductor module 1000 includes a module substrate 1010, a control chip 1020 mounted on the module substrate 1010, and a plurality of semiconductor devices (mounted on the module substrate 1010). 1030).

On one side of the module substrate 1010, a plurality of input/output terminals 1050 that can be inserted into sockets of the main board are disposed. The plurality of semiconductor devices 1030 may include the semiconductor package 10 manufactured by the method ( S10 ) of manufacturing a semiconductor package according to the technical idea of the present invention described above.

13 is a configuration diagram illustrating a system of a semiconductor package according to an embodiment of the inventive concept.

Referring to FIG. 13 , a system 1100 includes a controller 1110 , an input/output device 1120 , a memory 1130 , an interface 1140 , and a bus 1150 .

System 1100 may be a mobile system or a system that transmits or receives information. In some embodiments, the mobile system may be a portable computer, web tablet, mobile phone, digital music player, or memory card.

The controller 1110 is for controlling an execution program in the system 1100, and may include a microprocessor, a digital signal processor, a microcontroller, or a device similar thereto.

Input/output device 1120 may be used to input or output data from system 1100 . The system 1100 may be connected to an external device, for example, a personal computer or a network, and exchange data with the external device using the input/output device 1120 . The input/output device 1120 may be, for example, a touch pad, a keyboard, or a display device.

The memory 1130 may store data for operation of the controller 1110 or data processed by the controller 1110 . The memory 1130 may include the semiconductor package 10 manufactured by the method ( S10 ) of manufacturing a semiconductor package according to the technical idea of the present invention described above.

The interface 1140 may be a data transmission path between the system 1100 and an external device. Controller 1110 , input/output device 1120 , memory 1130 , and interface 1140 may communicate with each other via bus 1150 .

Above, the embodiments of the technical idea of the present invention have been described with reference to the accompanying drawings, but those skilled in the art to which the present invention pertains may change the technical idea or essential features of the present invention without changing the specific shape. It will be appreciated that this can be implemented. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

S10: Manufacturing method of semiconductor package
10: semiconductor package
101: first substrate 102: second substrate
110: plurality of conductive vias 111: barrier layer
120: metal pattern layer 130: first redistribution layer
140: semiconductor chip 150: molding member
160: second redistribution layer 171, 172: connection terminal
1000: semiconductor module

Claims (10)

forming a plurality of conductive vias in the first substrate;
forming a first redistribution layer on an upper surface of the first substrate where the plurality of conductive vias are exposed;
attaching a second substrate on the first redistribution layer to face the first substrate with the first redistribution layer interposed therebetween;
etching and removing the first substrate;
mounting a semiconductor chip between the plurality of conductive vias on the first redistribution layer;
forming a molding member to cover the plurality of conductive vias and the semiconductor chip;
polishing the molding member to expose the plurality of conductive vias; and
Forming a second redistribution layer on the molding member; including,
A method of manufacturing a semiconductor package. According to claim 1,
Forming the plurality of conductive vias in the first substrate,
forming a plurality of holes at a predetermined depth from the upper surface of the first substrate;
conformally forming a barrier layer made of an insulating material on inner walls of the plurality of holes; and
and forming a metal material to contact the barrier layer and fill the plurality of holes. According to claim 2,
After forming the metal material,
The method of manufacturing a semiconductor package, further comprising forming a metal seed layer on the upper surface of the first substrate. According to claim 3,
After etching and removing the first substrate,
The method of manufacturing a semiconductor package of claim 1, further comprising forming a metal pattern layer positioned under the plurality of conductive vias by etching the exposed metal seed layer. According to claim 4,
Both sidewalls of the metal pattern layer are a method of manufacturing a semiconductor package, characterized in that the rounded shape. According to claim 4,
Etching of the first substrate is performed by a dry etching process,
The method of manufacturing a semiconductor package, characterized in that the etching of the metal seed layer is performed by a wet etching process. According to claim 6,
The first substrate and the second substrate are made of different materials,
The method of manufacturing a semiconductor package, characterized in that the second substrate is composed of a material that is not etched by the dry etching process. According to claim 2,
The step of polishing the molding member,
A top surface of the molding member, a top surface of the barrier layer, and a top surface of the plurality of conductive vias are coplanar by polishing a portion of the molding member, a portion of the barrier layer, and a portion of the plurality of conductive vias. Method for manufacturing a semiconductor package, characterized in that. According to claim 1,
A first redistribution via included in the first redistribution layer has a trapezoidal shape;
The method of manufacturing a semiconductor package, characterized in that the second redistribution via included in the second redistribution layer has an inverted trapezoidal shape. According to claim 9,
The method of manufacturing a semiconductor package, characterized in that the first redistribution layer and the second redistribution layer are electrically connected through the plurality of conductive vias.

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