KR20220034698A - Semiconductor devices and related methods - Google Patents

Abstract

In one example, a semiconductor device may comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate may comprise first and second substrate surfaces opposite each other, a substrate outer sidewall between the first substrate surface and the second substrate surface, and a substrate inner sidewall defining a cavity between the first substrate surface and the second substrate surface. The device stack may be positioned in the cavity and may comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect may be coupled to the substrate and the device stack. The second internal interconnect may be coupled to the second electronic device and the first electronic device. The encapsulant may cover the substrate inner sidewall and the device stack, and may fill the cavity. Other examples and related methods are disclosed herein. The present invention can provide electrical coupling between external components and the device stack.

Description

SEMICONDUCTOR DEVICES AND RELATED METHODS

This application is a continuation-in-part of (pending) U.S. Application No. 16/429,553, filed June 3, 2019, titled "Semiconductor Devices and Related Methods" (Document No. MCK-63846US01). This application also claims the benefit of U.S. Application Serial No. 62/902,473, filed September 19, 2019 (pending) titled "Semiconductor DEVICES AND RELATED METHODS" (document number CK-018PR). Application No. 16/429,553 and Application No. 62/902,473 are incorporated herein by reference in their entirety.

BACKGROUND The present disclosure relates generally to electronic devices, and more particularly to semiconductor devices and methods of manufacturing semiconductor devices.

Conventional semiconductor packages and methods for forming semiconductor packages are inadequate, resulting in, for example, excessive cost, reduced reliability, relatively low performance, or too large package size. Further limitations and disadvantages of the conventional and traditional methods will become apparent to those skilled in the art by comparing the present invention with these methods with reference to the drawings.

BACKGROUND The present disclosure relates generally to electronic devices, and more particularly to semiconductor devices and methods of manufacturing semiconductor devices.

A semiconductor device according to the present invention includes a first substrate surface, a second substrate surface opposite to the first substrate surface, an outer wall of a substrate between the first substrate surface and the second substrate surface, and the first substrate surface and the second substrate a substrate having an inner substrate wall defining a cavity between the faces; a device stack positioned within the cavity, the device stack having a first electronic device and a second electronic device stacked on the first electronic device; a first internal interconnect coupled to the substrate and the device stack; a second internal interconnect coupled to the first electronic device and the second electronic device; and an encapsulant covering the inner wall of the substrate and the device stack and filling the cavity.

wherein the substrate includes a substrate shelf adjacent a first edge of the substrate; the substrate shelf includes an inner terminal on the first substrate side; The encapsulant may cover the surface of the first substrate, and the substrate shelf and the inner terminal may be exposed.

and the encapsulant includes a sidewall recessed at the interface with the substrate shelf; The recessed sidewall may be inclined at an acute angle to the surface of the first substrate.

It also further includes a vertical interconnect coupled to the first internal terminal of the first substrate face, the vertical interconnect extending through the encapsulant and exposed at the top of the encapsulant.

Also, at least one side of the device stack may not be bounded by the substrate.

Also comprising: a stack cap on top of the device stack, wherein the stack cap includes a cap coefficient of thermal expansion; the device stack includes a device coefficient of thermal expansion; the encapsulant comprises an encapsulant coefficient of thermal expansion; The cap coefficient of thermal expansion may be closer to the device coefficient of thermal expansion than the encapsulant coefficient of thermal expansion.

Further, the cap coefficient of thermal expansion may be substantially equal to the device coefficient of thermal expansion.

In addition, the device further includes a stack cap on the top of the stack, wherein the stack cap is exposed on the top of the encapsulant; The device stack may be exposed on the bottom surface of the encapsulant.

Also included is a first external interconnect; and a second external interconnect, wherein the substrate includes a substrate first shelf adjacent a first edge of the substrate, and a first external terminal on a second surface of the substrate below the first shelf; the substrate includes a second shelf of the substrate adjacent a second edge of the substrate, and a second external terminal on a second surface of the substrate below the second shelf; the encapsulant covers the surface of the first substrate, leaving the substrate first shelf and the substrate second shelf exposed; a first external interconnect coupled to a first external terminal under the first shelf outside a footprint of the encapsulant; A second external interconnect may be coupled to a second external terminal below the second shelf outside the footprint of the encapsulant.

In addition, the method according to the present invention includes the step of (a) receiving a substrate, wherein the substrate is a first substrate surface, a second substrate surface opposite to the first substrate surface, the first substrate surface and the second substrate receiving a substrate, the substrate having an outer substrate wall between the faces and an inner substrate wall defining a cavity between the first and second substrate faces; (b) providing a device stack within the cavity, the device stack having a first electronic device and a second electronic device stacked on the first electronic device; (c) providing a first internal interconnect coupled to the substrate and the device stack; (d) providing a second internal interconnect coupled to the first electronic device and the second electronic device; and (e) providing an encapsulant covering the inner wall of the substrate and the device stack and filling the cavity.

wherein providing a vertical interconnect coupled to a first internal terminal on a first substrate surface prior to providing the encapsulant, the vertical interconnect extending through the encapsulant and at the top surface of the encapsulant may be exposed.

and providing a stack cap on an upper surface of the device stack.

Further, the substrate includes a substrate first shelf adjacent to a first edge of the substrate, and a first external terminal on a second substrate face under the first shelf; the substrate includes a substrate second shelf adjacent to a second edge of the substrate, and a second external terminal on a second substrate face under the second shelf; the encapsulant covers the surface of the first substrate, leaving the first front of the substrate and the second shelf of the substrate exposed; The method includes providing a first external interconnect coupled to the first external terminal on a lower portion of a first shelf, outside the footprint of the encapsulate; and providing a second external interconnect coupled to the second external terminal under the second shelf outside the footprint of the encapsulate.

In addition, a semiconductor device according to the present invention includes: a base substrate having a first surface and an internal base terminal on the first surface; a first module on the base substrate, the first module comprising: a first substrate surface; a second substrate surface opposite to the first substrate surface; a substrate outer sidewall between the first substrate surface and the second substrate surface; and a substrate comprising a substrate inner sidewall defining a cavity between the first substrate surface and the second substrate surface; and a device stack comprising a second electronic device stacked on the first electronic device, a first internal interconnect coupled to the substrate and the device stack, and a device stack covering the substrate interior sidewall and filling the cavity. a second module comprising a first encapsulant, said second module on said first module; and a second encapsulant on the base substrate and in contact with horizontal surfaces of the first module and the second module.

Here, the second encapsulant may further include a module interconnect coupled to the internal base terminal and the substrate of the first module.

and wherein the substrate of the first module comprises a substrate shelf adjacent a first edge of the substrate; the substrate shelf includes internal terminals on the first substrate surface; the first encapsulant covers the first substrate, leaving the substrate shelf and inner terminals exposed; and the module interconnect may be coupled to the inner terminal.

Further, the first encapsulant includes a sidewall recessed at the interface with the first substrate shelf; and the recessed sidewall may be inclined at an acute angle with respect to the first substrate surface.

wherein the first module includes a vertical interconnect coupled to a first internal terminal on the first substrate surface; the vertical interconnect extends through the first encapsulant and is exposed at a top surface of the first encapsulant; and the module interconnect may be coupled to the substrate through the vertical interconnect.

Also, the first module may include a stack cap on an upper surface of the device stack.

In addition, it may further include an external interconnect in the second encapsulant in contact with the top surface of the base substrate and the bottom surface of the substrate of the first module.

1A and 1B are cross-sectional views illustrating exemplary semiconductor devices.
2A-2H are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device.
3 is a cross-sectional view illustrating an exemplary semiconductor device.
4A-4H are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device.
5 is a cross-sectional view illustrating an exemplary semiconductor device.
6A-6C are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device.
7 is a cross-sectional view illustrating an exemplary semiconductor device.
8 is a cross-sectional view illustrating an exemplary semiconductor device.
9A-9G are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device.
10 is a cross-sectional view illustrating an exemplary semiconductor device.
11 is a cross-sectional view illustrating an exemplary semiconductor device.
12A-12D are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device.
13 is a cross-sectional view illustrating an exemplary semiconductor device.
14 is a cross-sectional view illustrating an exemplary semiconductor device.
15 is a cross-sectional view illustrating an exemplary semiconductor device.
16 is a cross-sectional view illustrating an exemplary semiconductor device.
17 is a cross-sectional view illustrating an exemplary semiconductor device.
18 is a cross-sectional view illustrating an exemplary semiconductor device.
19 is a cross-sectional view illustrating an exemplary semiconductor device.
20 is a cross-sectional view illustrating an exemplary semiconductor device.
21 is a cross-sectional view illustrating an exemplary semiconductor device.
22 is a cross-sectional view illustrating an exemplary semiconductor device.
23 is a cross-sectional view illustrating an exemplary semiconductor device.
24 is a cross-sectional view illustrating an exemplary semiconductor device.
25 is a cross-sectional view illustrating an exemplary semiconductor device.
26 is a cross-sectional view illustrating an exemplary semiconductor device.

The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Since these examples are non-limiting, the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the phrases "example" and "e.g.," are non-limiting.

The drawings illustrate a general manner of construction, and descriptions and details of well-known features and techniques may be omitted in order to avoid unnecessarily obscuring the present disclosure. In addition, components in the drawings are not necessarily drawn to scale. For example, the dimensions of some components in the drawings may be exaggerated relative to other components to improve understanding of examples discussed in this disclosure. Like reference numbers in different drawings indicate like elements.

The term "or" means any one or more items in the list joined by "or". For example, "x or y" means any one of a set of three elements {(x), (y), (x, y)}. As another example, "x, y or z" is {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z) } means any one of the 7 component sets.

The terms “comprises”, “comprising”, “includes” or “including” are “open-ended” terms and specify the presence of the recited feature, but one or more It does not exclude the presence or addition of other features.

Terms such as “first” and “second” may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are used only to distinguish one component from another. For example, a first component discussed in this disclosure may be referred to as a second component without departing from the teachings of this disclosure.

Unless otherwise specified, the term "coupled" may be used to describe two components that are in direct contact with each other or two components that are indirectly connected by one or more other components. For example, if component A is coupled to component B, component A may be in direct contact with component B or indirectly connected to component B by intervening component C. Similarly, the terms “over” or “on” may be used to describe two components that are in direct contact with each other or two components that are indirectly connected by one or more other components. .

In one example, a semiconductor device may include a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate defines a cavity between a first substrate surface and a second substrate surface located opposite to each other, an outer wall of the substrate between the first substrate surface and the second substrate surface, and a cavity between the first substrate surface and the second substrate surface It may include an inner wall of the substrate. The device stack may be positioned within the cavity and includes a first electronic device and a second electronic device stacked on the first electronic device. The first internal interconnect may be coupled to the substrate and the device stack. The second internal interconnect may be coupled to the first electronic device and the second electronic device. The encapsulant may cover the inner wall of the substrate and the device stack, and may fill the cavity.

In one example, the method comprises: (a) a first substrate surface, a second substrate surface opposite to the first substrate surface, a substrate outer wall between the first substrate surface and the second substrate surface, and the first substrate surface; receiving a substrate having an inner substrate wall defining a cavity between the second substrate surfaces; (b) providing in the cavity a device stack having a first electronic device and a second electronic device stacked on the first electronic device; (c) providing a first internal interconnect coupled to the substrate and the device stack; (d) providing a second internal interconnect coupled to the first electronic device and the second electronic device; and (e) providing an encapsulant covering the inner wall of the substrate and the device stack and filling the cavity.

Other examples are included in this disclosure. Examples of such can be found in the drawings, the claims, or the description of the present disclosure.

1A and 1B are cross-sectional views illustrating exemplary semiconductor devices 100 and 100'. In the present disclosure, reference numerals for the semiconductor device 100 or a component thereof may also refer to the semiconductor device 100 ′ or a component corresponding thereto.

In the example shown in FIG. 1 , the semiconductor device 100 may include a substrate 110 , a device stack 120 , an internal interconnect 130 , an encapsulant 140 , and an external interconnect 150 . In some examples, semiconductor device 100 may include or be referred to as module 101 .

The substrate 110 may include a cavity 111 , an inner terminal 112 , and an outer terminal 113 . The device stack 120 may include a number of electronic devices 121 , 122 , 123 , 124 . Also, the plurality of electronic devices 121 , 122 , 123 , and 124 may include device terminals 121a , 122a , 123a , and 124a, respectively.

The substrate 110 , the inner interconnect 130 , the encapsulant 140 , and the outer interconnect 150 may include or refer to a semiconductor package, wherein the semiconductor package includes the device stack 120 from external components or environmental exposure. can protect In addition, the semiconductor package may provide electrical coupling between the external components and the device stack 120 .

2A-2H are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device. 2A is a cross-sectional view illustrating the semiconductor device 100 in an initial stage of manufacturing.

In the example shown in FIG. 2A , the substrate 110 may be attached to the top of the carrier 10 . Although one substrate 110 is shown attached to the carrier 10 in FIG. 2A , a plurality of substrates 110 are mounted on the carrier 10 for simultaneous production of a plurality of modules 101 . can be arranged. In some examples, multiple substrates 110 may be singulated from a larger strip or substrate, and carrier 10 post-singulation to leave spacing space between adjacent substrates 110 . ) can be arranged on In some examples, multiple substrates 110 are attached to carrier 10 prior to singulation in the form of strips or larger substrates, with no spacing between adjacent substrates 110 . can be

The carrier 10 may include a base layer 11 and a separable layer 12 . In some examples, the base layer 11 may include a metal, glass, or semiconductor material. In some examples, carrier 10 or base layer 11 may comprise a rectangular shape, such as a panel or strip, or a disk shape, such as a wafer. Releasable layer 12 may comprise a temporary adhesive tape or film, revalpha tape, thermal release tape, adhesive tape or adhesive film. In some examples, the separable layer 12 may be removed by heating, chemicals, light irradiation, or physical force.

The substrate 110 may include a cavity 111 , a substrate dielectric structure 114 , and a substrate conductive structure 115 . The substrate cavity 111 may be defined as the inner wall 110i of the substrate dielectric structure 114 . Substrate dielectric structure 114 may include one or more dielectrics, and substrate conductive structure 115 may include one or more conductors stacked or embedded between dielectrics corresponding to substrate dielectric structure 114 . The substrate conductive structure 115 may include a substrate terminal such as an inner terminal 112 and an outer terminal 113 that are electrically connected to each other through the substrate 110 internally by a substrate conductor 115a.

In some examples, the substrate dielectric structure 114 may include or refer to one or more dielectrics, dielectric materials, dielectric layers, passivation layers, insulating layers, or protective layers. In some examples, the substrate dielectric structure 114 is a polymer, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), a molding material, a phenolic resin, an epoxy , an electrically insulating material such as silicone or acrylate polymer. In some examples, the substrate dielectric structure 114 may be formed by spin coating, spray coating, printing, oxidation, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), MetalOrganic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), It may be formed by various processes such as Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma-Enhanced Chemical Vapor Deposition (PECVD). Each dielectric or layer of substrate dielectric structure 114 may have a thickness ranging from about 1 μm to about 20 μm.

In some examples, the substrate conductive structure 115 may include or refer to one or more conductors, conductive materials, conductive paths, conductive layers, redistribution layers (RDLs), wiring layers, trace patterns, or circuit patterns. In some examples, the substrate conductive structure 115 may include various conductive materials such as copper, gold, or silver. The substrate conductive structure 115 may be formed by various processes such as sputtering, electroless plating, electrolytic plating, PVD, CVD, MODVD, ALD, LPCVD, or PECVD. Each conductor or layer of the substrate conductive structure 115 may have a thickness ranging from about 5 μm to about 50 μm.

In some examples, the substrate 110 may include a multi-layed PCB, a pre-formed substrate, a redistribution layer (RDL) substrate, an interposer, a lead frame, or a micro lead frame. can In some examples, the thickness of the substrate 110 may range from about 90 μm to about 110 μm.

In some examples, the cavity 111 is formed in the substrate 110 and may be formed to pass through the substrate 110 . For example, the cavity 111 may be formed by removing a partial region of the substrate 110 . In some examples, the cavity 111 may be formed by cutting a portion of the substrate 110 using a laser or blade. In some examples, the cavity 111 is formed in the substrate 110 , such that the substrate 110 can be formed into an approximately rectangular frame having an empty space. In some examples, the substrate 110 may include an open parallel frame, and the cavity 111 may be bounded by the substrate 110 on both parallel sides, although in others the substrate 110 may be ) may be open or unbounded. The width of the cavity 111 may range from about 8500 μm to about 9500 μm. In some examples, the cavity 111 may provide a space in which the device stack 120 may be seated. Also, the cavity 111 may serve to reduce the size, particularly, the height of the semiconductor device 100 .

In some examples, internal terminal 112 may include or be referred to as a pad, bond pad, circuit pattern, wiring layer, or metal layer. The inner terminal 112 may include, for example, an electrically conductive material such as aluminum, copper, an aluminum alloy, or a copper alloy. For example, the inner terminal 112 may be formed by electrolytic plating or a physical vapor deposition (PVD) processor. The inner terminal 112 may be formed on the first surface (upper surface) 110a of the substrate 110 and exposed to the upper portion of the substrate 110 . In some examples, the inner terminal 112 provides electrical signals of the substrate 110 to the device stack 120 or serves as an electrical contact for providing electrical signals of the device stack 120 to the substrate 110 . can be

In some examples, the external terminal 113 may be referred to as a pad, a circuit pattern, a wiring layer, or a metal layer. The external terminal 113 may include, for example, an electrically conductive material such as a metallic material, aluminum, copper, an aluminum alloy, or a copper alloy. For example, the external terminal 113 may be formed by electrolytic plating or a PVD (physical vapor deposition) processor. The external terminal 113 may be formed on the second surface (lower surface) 110b of the substrate 110 and exposed under the substrate 110 . In some examples, the external terminal 113 may be provided as an electrical contact for providing electrical signals of the substrate 110 to external electronic devices, or providing electrical signals of external electronic devices to the substrate 110 . there is.

In some examples, the substrate 110 may be a redistribution layer (“RDL”) substrate. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers. The one or more conductive redistribution layers and one or more dielectric layers may be formed layer by layer over (a) the electronic device to which the RDL substrate is electrically coupled, or (b) be wholly or at least partially removed after the electronic device and the RDL substrate are coupled together. It can be formed layer by layer on the carrier that can be. RDL substrates can be fabricated layer by layer as a wafer-level substrate on a circular wafer in a wafer-level process or as a panel-level substrate on a rectangular or square panel carrier in a panel-level process. The RDL substrate may be formed in an additional build-up process that may include one or more conductive layers stacked alternately with one or more dielectric layers, wherein the one or more conductive layers (a) fan-out electrical traces outside the footprint of the electronic device. or (b) each conductive redistribution pattern or trace that as a whole constitutes a fan-in electrical trace within the footprint of the electronic device. The conductive pattern may be formed using, for example, a plating process such as an electrolytic plating process or an electroless plating process. The conductive pattern may include an electrically conductive material such as, for example, copper or other platable metal. The location of the conductive pattern may be made using, for example, a photoresist material for forming a photolithographic mask and a photopatterning process such as a photolithographic process. The dielectric layer of the RDL substrate may be patterned in a photo-patterning process, which may include a photolithographic mask in which light is exposed to a photo-pattern of a desired shape, such as vias in the dielectric layer. The dielectric layer may be made of, for example, a photo-definable organic dielectric material such as polyimide (PI), benzocyclobutene (BCB) or polybenzoxazole (PBO). Such dielectric material may be radiated or otherwise coated in liquid form rather than deposited into a preformed film. To allow proper formation of a desired photo-defined shape, such a photo-definable dielectric material may omit structural reinforcement, or strands that may interfere with light from the photo-patterning process. , without weaving or other particles, and may be filler-free. In some examples, this filler-free nature of the filler-free dielectric material may allow for a reduction in the thickness of the resulting dielectric layer. Although the photo-definable dielectric material described above may be an organic material, in another example the dielectric material of the RDL substrate may include one or more inorganic dielectric layers. Some examples of the inorganic dielectric layer may include silicon nitride (Si3N4), silicon oxide (SiO2), or SiON. The inorganic dielectric layer may be formed by growing the inorganic dielectric layer using an oxidation or nitridation process instead of using a photo-defined organic dielectric material. This inorganic dielectric layer may be filler-free, free of strands, weaving, or other dissimilar inorganic particles. In some examples, the RDL substrate may omit a carrier or a permanent core structure such as, for example, a dielectric material comprising bismaleide triazine (BT) or FR4, and this type of RDL substrate is a coreless substrate. may be referred to. Other substrates in the present invention may also include RDL substrates.

In some examples, the substrate 110 may be a pre-formed substrate. A pre-formed substrate may be fabricated prior to being attached to an electronic device and may include a dielectric layer between each conductive layer. The conductive layer may include copper and may be formed using a plating process. The dielectric layer may be a relatively thick, non-photo-definable layer that can be deposited as a preformed film rather than a liquid, and includes a resin having fillers such as strands, weave, or other inorganic particles for rigidity or structural support. can do. Because the dielectric layer is non-photodefinable, features such as vias or openings can be formed using a drill or laser. In some examples, the dielectric layer may include a prepreg material or Ajinomoto Buildup Film (ABF). The preformed substrate may include a carrier or a permanent core structure such as, for example, a dielectric material comprising bismaleide triazine (BT) or FR4, wherein the dielectric and conductive layers are on the permanent core structure. can be formed in In another example, the pre-formed substrate can be a coreless substrate that omits a permanent core structure, wherein the dielectric and conductive layers are removed from the sacrificial carrier after the dielectric and conductive layers are formed and before the electronic device is attached. may be formed on the A pre-formed substrate may be referred to as a printed circuit board (PCB) or laminate substrate. Such a pre-formed substrate may be formed through a semi-additive or modified-semi-additive process. Other substrates in the present invention may also include pre-formed substrates.

2B is a cross-sectional view illustrating the semiconductor device 100 in the next stage of manufacturing. In the example shown in FIG. 2B , a device stack 120 may be formed in the cavity 111 . The device stack 120 may include a first electronic device 121 , a second electronic device 122 , a third electronic device 123 , and a fourth electronic device 124 . Although FIG. 2B shows that the device stack 120 includes four electronic devices 121 , 122 , 123 , and 124 , the present invention is not limited thereto. In some examples, device stack 120 may consist of four or more electronic devices, or may consist of fewer electronic devices. In some examples, the first electronic device 121 may be attached to a top surface of the carrier 10 within the cavity 111 , and the second electronic device 122 may include a device terminal 121a. In order to expose a portion of the upper surface of the first electronic device 121 , it may be attached to cover most of the upper surface of the first electronic device 121 using the adhesive member 20 . The third electronic device 123 uses the adhesive member 20 to expose a portion of the top surface of the second electronic device 122 including the device terminal 122a to most of the top surface of the second electronic device 122 . may be attached to cover the third electronic device 124 using an adhesive member 20 to expose a portion of the upper surface of the third electronic device 123 including the device terminal 123a. It may be attached to cover most of the upper surface of the device 123 . In some examples, the device stack 120 may be stacked in an offset structure, such as a step shape, a staggered shape, or a zigzag shape. In some examples, the offset structure may align the electronic devices 121-124 such that each device terminal 121a , 122a , 123a , 124a is exposed toward the same side of the semiconductor device 100 . The height of the device stack 120 may range from about 110 to 130 μm.

In some examples, when the device stack 120 is in the cavity 111 , a top surface of the first electronic device 121 may be lower than a top surface of the substrate 110 . In some examples, a top surface of the second electronic device 122 may also be lower than a top surface of the substrate 110 . In some examples, a top surface of the third electronic device 123 or the fourth electronic device 124 may be higher than a top surface of the substrate 110 . In some examples, a majority of the device stack 120 may be lower than a top surface of the substrate 110 . In some examples, the thickness of each of the second through fourth electronic devices 122-124 may be the same. In some examples, the thickness of the first electronic device 121 may be formed to be greater than the thickness of the other electronic devices 122-124 to provide increased structural support or integrity of the device stack 120 . In some examples, although the thickness of the first electronic device 121 is thicker than the thickness of the second electronic device 122 , the integrated circuit of the first battery device 121 is the same as the integrated circuit of the second electronic device 122 . can be the same.

In some examples, the first through fourth electronic devices 121 , 122 , 123 , 124 may include or be referred to as a semiconductor package such as a semiconductor die, a semiconductor chip, or a chip scale package. Electronic devices 121 , 122 , 123 , 124 may include, for example, a semiconductor material such as silicon (Si). Electronic devices 121 , 122 , 123 , 124 may include passive electronic circuit elements or active electronic circuit elements such as transistors. In some examples, the electronic device 121 , 122 , 123 , 124 is a digital signal processor (DSP), microprocessor, network processor, power management processor, audio processor, RF circuitry, wireless baseband system-on-chip (SoC) It may include processors, sensors, and electrical circuits such as application specific integrated circuits (ASICs). The electronic devices 121, 122, 123, and 124 may include device terminals 121a, 122a, 123a, and 124a, respectively. In some examples, each device terminal 121a , 122a , 123a , 124a transmits an electrical signal from a die pad, bond pad, bump, or electronic device 121 , 122 , 123 , 124 to a substrate 110 or a neighbor. provided to the electronic device 121, 122, 123, 124, or an electrical signal from the substrate 110 or the neighboring electronic device 121, 122, 123, 124 to the electronic device 121, 122, 123, 124 ) may include or be referred to as an electrical contact to provide.

2C is a cross-sectional view illustrating the semiconductor device 100 in the next stage of manufacturing. In the example shown in FIG. 2C , internal interconnect 130 may electrically connect substrate 110 with respective electronic devices 121 , 122 , 123 , 124 or device stack 120 . In some examples, one or more internal interconnects 130 may connect one or more device terminals 121a, 122a, 123a, 124a and one or more device terminals 121a, 122a, 123a, 124a.

In some examples, one or more internal interconnects 130 may connect internal terminal 112 of substrate 110 and one or more device terminals 121a , 122a , 123a , 124a . In some examples, a first end of the internal interconnect 130 is coupled to an internal terminal 112 of the substrate 110 , and a second end of the internal interconnect 130 is, for example, a device within the cavity 111 . It may be coupled with the stack 120 , and the height of the first end may be higher than the height of the second end of the internal interconnect 130 .

In some examples, the internal interconnect 130 may include or be referred to as a wire, a conductive wire, or a bonding wire. Internal interconnect 130 may include, for example, an electrically conductive material such as a metallic material, gold, silver, aluminum, or copper. In some examples, the internal interconnect 130 may be joined by wire bonding. The internal interconnect 130 may provide electrical coupling between the substrate 110 and the device stack 130 or between the respective electronic devices 121 , 122 , 123 , 124 .

2D and 2E are cross-sectional views illustrating the semiconductor device 100 in the next stage of manufacturing. In the example shown in FIG. 2D , encapsulant 140 may encapsulate device stack 120 and internal interconnect 130 . Also, the encapsulant 140 may be provided between the inner wall 110i of the substrate 110 and the device stack 120 to fill the cavity 111 . As shown in FIG. 2D , encapsulant 140 may overmold the device stack 120 and internal interconnect 130 , and may be ground thinly as shown in FIG. 2E . In some examples, grinding may be omitted by adjusting the height of the encapsulant 140 during the forming process.

In some examples, as shown with respect to semiconductor device 100 of FIG. 1A , outer wall 110s of substrate 110 remains uncovered by encapsulant 140 or 140) and may be substantially coplanar. This shape may be due to the above-described pre-singulation option for arranging a plurality of substrates 110 on the carrier 10 , and there is no separation space between adjacently arranged substrates 110 . .

In some examples, as shown with respect to semiconductor device 110 ′ of FIG. 1B , outer wall 110s of substrate 110 may be covered by encapsulant 140 ′. This shape can be attributed to the post-singulation option described above for arranging a plurality of substrates 110 on the carrier 10, and there is a separation space between the adjacently arranged substrates 110, This separation space is filled by the encapsulant 140'.

In some examples, encapsulant 140 may include or refer to a protective material, dielectric, mold compound, or package body. The encapsulant 140 may be formed of various encapsulating or molding materials (eg, resins, polymer composite materials, polymers having fillers, epoxy resins, epoxy resins having fillers, epoxy acrylates having fillers, silicone resins, and the like). combinations, their equivalents, etc.). The encapsulant 140 may be formed by various methods, for example, a compression molding process, a liquid encapsulant molding process, a vacuum lamination process, a paste printing process, or a film-assisted molding process. The height of the encapsulant 140 may be in the range of about 100 μm to about 200 μm. The encapsulant 140 may protect the device stack 120 and the internal interconnect 130 from external environments.

2F is a cross-sectional view illustrating the semiconductor device 100 in the next stage of manufacturing. In the example shown in FIG. 2F , the carrier 10 located under the substrate 110 may be removed. In some examples, when the carrier 10 is removed, the substrate lower surface 110b is exposed and exposed from the encapsulant 140 . In some examples, when the carrier 10 is removed, the lower surface of the electronic device 121 or the lower surface of the device stack 120 is exposed from the encapsulant 140 . In some examples, when the carrier 10 is removed, the substrate lower surface 110b may be flush with the lower surface of the device stack 120 or the lower surface of the encapsulant 140 . In some examples, carrier 10 may be separated from substrate 110 as separable layer 12 loses adhesion by heat, chemical, or irradiation. In some examples, the carrier 10 may be separated from the substrate 110 by a physical force. Accordingly, the second surface (lower surface) 110b of the substrate 110 and the lower surface 120b of the device stack 120 may be exposed.

2G and 2H are cross-sectional views and plan views illustrating the semiconductor device 100 in the next stage of manufacturing. In the example shown in FIG. 2G , an external interconnect 150 may be coupled to an external terminal 113 of the substrate 110 . External interconnect 150 may include conductive bumps, balls, or pillars (such as posts or wires), and may include, for example, a solder body, a kappa body, or a solder cap. External interconnect 150 is tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn- Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. The external interconnect 150 may be formed by, for example, a ball drop process, a screen printing process, or an electroplating process. The height of the external interconnect 150 may range from about 20 μm to 50 μm. The external interconnect 150 may provide an electrical connection path between the semiconductor device 100 and an external component. In addition, after the external interconnect 150 is connected, a singulation process for separating the arranged substrates 110 from each other may be performed. Accordingly, as shown in FIG. 2H , the semiconductor device 100 may be completed.

3 is a cross-sectional view illustrating an exemplary semiconductor device 200 . In the example shown in FIG. 3 , semiconductor device 200 includes module stack 290 with module 101 and module 201 from semiconductor device 100 of FIG. 1 and external interconnects 150 , 250 . can do. The semiconductor device 200 may be formed to have a module stack including modules 101 and 201 .

The first module 101 may include a substrate 110 , a device stack 120 , an internal interconnect 130 , and an encapsulant 140 . The second module 201 may include a substrate 210 , a device stack 220 , an internal interconnect 230 , an encapsulant 240 , and a vertical interconnect 260 . The substrate 210 may include a cavity 211 , an inner terminal 212 , and an outer terminal 213 . The device stack 220 may include a plurality of devices 221 , 222 , 223 , 224 . Also, the plurality of devices 221 , 222 , 223 , and 224 may include device terminals 221a , 222a , 223a , and 224a, respectively.

In some examples, module 201 may include corresponding components, features, materials, or forming processes similar to those of module 101 described above. For example, items 210, 211, 212, 213, 220, 221, 221a, 222, 222a, 223, 223a, 224, 224a, 230, 240, 250 of module 201 are each 101) may correspond to or be similar to items 110, 111, 112, 113, 120, 121, 121a, 122, 122a, 123, 123a, 124, 124a, 130, 140, 150. Module 201 also includes vertical interconnects 260 coupled with internal terminals 212 of substrate 210 .

In some examples, substrate 210 , internal interconnect 230 , encapsulant 240 , and external interconnect 250 may include or be referred to as a semiconductor package, wherein the semiconductor package is a device that is protected from external components or environmental exposures. The stack 220 may be protected. Additionally, the semiconductor package may provide electrical coupling between the external components and the device stack 220 . In some examples, module 201 may include or refer to a semiconductor package. In some examples, the semiconductor device 200 on which the modules 101 and 201 are stacked may include or be referred to as a package on package (POP) device.

4A-4H are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device. 4A is a cross-sectional view illustrating the semiconductor device 200 in an initial stage of manufacturing.

In the example shown in FIG. 4A , a substrate 210 may be attached to the top of the carrier 10 , and a vertical interconnect 260 may be attached or formed to the substrate 210 . Although one substrate 210 is shown attached to the carrier 10 in FIG. 4A , a plurality of substrates 210 are mounted on the carrier 10 for simultaneous production of a plurality of modules 101 . They may be arranged side by side with each other. The carrier 10 may include a base layer 11 and a separable layer 12 .

The substrate 210 may include a cavity 211 , an inner terminal 212 , and an outer terminal 213 . The inner terminal 212 and the outer terminal 213 may be electrically connected to each other by internally penetrating the substrate 210 by means of a substrate conductor or an internal circuit. The cavity 211 may pass through the substrate 210 completely.

Vertical interconnect 260 may be coupled or formed to inner terminal 212 of substrate 210 . In some examples, vertical interconnects 260 may include corresponding components, features, materials, or forming processes similar to those of interconnect 150 described above. In some examples, the height of the vertical interconnects 260 may range from about 50 μm to about 100 μm. The vertical interconnect 260 may provide an electrical connection path between the first module 101 and the second module 201 . In some examples, vertical interconnects 260 may provide terminals formed to allow stacking of modules.

4B is a cross-sectional view illustrating the semiconductor device 200 in the next stage of manufacturing. In the example shown in FIG. 4B , a device stack 220 may be formed in the cavity 211 , and an internal interconnect 230 is formed. Device stack 220 may include electronic devices 221 , 222 , 223 , 224 . Although the device stack 220 is illustrated as including four electronic devices 221 , 222 , 223 and 224 in FIG. 4B , the present invention is not limited thereto. In some examples, device stack 220 may consist of four or more electronic devices, or may consist of fewer electronic devices. In some examples, the first electronic device 221 may be attached to the top surface of the carrier 10 within the cavity 211 , and the second electronic device 222 is a first electronic device including a device terminal 221a . It may be attached to the top surface of the first electronic device 221 using the adhesive member 20 to expose a portion of the top surface of the first electronic device 221 . The third electronic device 223 is attached to the upper surface of the second electronic device 222 using the adhesive member 20 to expose a portion of the upper surface of the second electronic device 222 including the device terminal 222a. The fourth electronic device 224 uses the adhesive member 20 to expose a portion of the upper surface of the third electronic device 223 including the device terminal 223a to the third electronic device 223 . It can be attached to the upper surface of In some examples, internal interconnect 230 may electrically couple substrate 210 and one or more respective electronic devices 221 , 222 , 223 , 224 , or device terminals 221a , 222a , 223a , 224a can be connected to one or more of them. In some examples, device stack 220 is a staircase in which corresponding device terminals 221a , 222a , 223a , 224a of adjacent electronic devices 221 , 222 , 223 , 224 are exposed towards the same side of semiconductor device 200 . It can be stacked obliquely as in the shape. The height of the device stack 220 may range from about 110 μm to 130 μm.

4C is a cross-sectional view illustrating the semiconductor device 200 in the next stage of manufacturing. In the example shown in FIG. 4C , encapsulant 240 may encapsulate device stack 220 , internal interconnect 230 , and vertical interconnect 260 . Also, the encapsulant 240 may be formed between the device stack 220 and the substrate 210 in the cavity 211 . In some examples, encapsulant 240 may be top-ground after over-molding device stack 220 , inner interconnect 230 , and outer interconnect 260 . The height of the encapsulant 240 may be in the range of about 100 μm to 200 μm. Encapsulant 240 may protect device stack 220 , internal interconnect 230 , and vertical interconnect 260 from external environments.

4D is a cross-sectional view illustrating the semiconductor device 200 in the next stage of manufacturing. In the example shown in FIG. 4D , the carrier 10 positioned under the substrate 210 may be removed. Accordingly, the second surface (lower surface) 210b of the substrate 210 and the lower surface of the device stack 220 may be exposed to the outside.

4E is a cross-sectional view illustrating the semiconductor device 200 in the next stage of manufacturing. In the example shown in FIG. 4E , vertical interconnects 260 may be exposed through respective openings 241 or vias of encapsulant 240 . In some examples, the opening 241 may be formed by removing a portion of the encapsulant 240 by a sawing process, a grinding process, a laser process, or an etching process. In some examples, vertical interconnect 260 extends partially through encapsulant 240 such that a top of vertical interconnect 260 is lower than a top surface of encapsulant 240 , or It sits down against the top. In some examples, vertical interconnect 260 extends completely through encapsulant 240 such that a top of vertical interconnect 260 is substantially flush with a top surface of encapsulant 240 , or encapsulant 240 . ) and protrude past the upper surface of In some examples, vias 241 contact or match the shape or sidewalls of vertical interconnects 260 , regardless of whether they partially or completely penetrate the top surface of encapsulant 240 .

4F is a cross-sectional view showing the semiconductor device 200 in the next stage of manufacturing. In the example shown in FIG. 4F , external interconnect 250 may be connected to external terminal 213 of substrate 210 .

4G is a cross-sectional view illustrating an exemplary semiconductor device 200 . In the example shown in FIG. 4G , the semiconductor device 200 may include modules 101 and 201 stacked on one another. Although the two modules are shown as being stacked, the present invention is not limited thereto. In some examples, two or more or fewer modules may be stacked in the semiconductor device 500 . Modules 201 and 101 may be stacked such that vertical interconnects 260 and 150 are electrically connected to each other. In some examples, the vertical interconnect 260 formed in module 201 and interconnect 150 of module 101 may be melted or reflowed together to electrically connect the modules to each other. Although the semiconductor device 200 is illustrated as including modules 101 and 201, other modules or other electronic devices of the present invention are examples that may replace one or more of these modules 101 and 201. there may be

4H is a cross-sectional view illustrating an exemplary semiconductor device. In the example shown in FIG. 4H , semiconductor device 200 ′ may include semiconductor device 200 , base substrate 310 , encapsulant 340 , base interconnect 350 , and underfill 345 . . Vertical interconnect 260 is shown in FIG. 4H as one or optional pillars of vertical interconnect 260 described above, but may include any of the other interconnect 260 options. In this example, the top of the vertical interconnect 260 is substantially flush with the top surface of the encapsulant 240 . In some examples, the semiconductor device 200 ′ including the packaged semiconductor device 200 may include or be referred to as a package-in-package (PIP) device.

In some examples, the base substrate 310 may include corresponding components, features, materials, or forming processes similar to those of the substrate 110 described above. In this example, the substrate 310 does not include a cavity such as the cavity 111 of the substrate 110 . In some examples, encapsulant 340 may include corresponding components, features, materials, or forming processes similar to those of encapsulant 140 described above.

In some examples, underfill 345 may be provided between module 201 and substrate 310 or between modules 101 , 201 . In some examples, underfill 345 may cover a sidewall of module 101 . In some examples, the top surface of the module 101 or the top of the sidewalls of the module 101 may remain uncovered by the underfill 345 . Underfill 345 may be omitted in some examples, or may be considered part of encapsulant 340 . In some examples, underfill 345 and encapsulant 340 may include separate layers of material. In some examples, underfill 345 may be similar to encapsulant 340 , or underfill 345 and encapsulant 340 may include the same material layer. In some examples, underfill 345 may be referred to as a dielectric, insulating paste, or non-conductive paste. In some examples, underfill 345 may be a dielectric free of resin or inorganic filler. In some examples, underfill 345 may be inserted between substrate 310 and module 201 or between module 201 and module 101 using capillary action. In some examples, underfill 345 may be applied prior to coupling substrate 310 and module 201 or prior to coupling module 201 and module 101 . Other examples of the present invention may include an underfill similar to underfill 345 between or around each substrate or module.

5 is a cross-sectional view illustrating an exemplary semiconductor device 300 . In the example shown in FIG. 5 , the semiconductor device 300 may include a base substrate 310 , a module stack 390 , an encapsulant 340 , and a base interconnect 350 . Module stack 390 may include a stack of two or more modules described herein, such as a stack of modules 101 . The base substrate 310 may include an inner base terminal 312 and an outer base terminal 313 . In some examples, the semiconductor device 300 including the package of the module 101 may include or be referred to as a package-in-package (PIP) device.

6A-6C are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device. 6A is a cross-sectional view illustrating the semiconductor device 300 in an initial stage of manufacturing.

In the example shown in FIG. 6A , a base substrate 310 may be provided. In some examples, the base substrate 310 may include corresponding components, features, materials, or forming processes similar to those of the substrate 110 described above. For example, the base substrate 310 may include a substrate conductive structure 315 , an inner base terminal 312 , an outer base terminal 313 , and a substrate conductor 315a , which are of the substrate 110 . The substrate conductive structure 115 , the inner terminal 112 , the outer terminal 113 , and the substrate conductor 115a may correspond similarly. In this example, the base substrate 310 does not include a cavity such as the cavity 111 of the substrate 110 .

6B is a cross-sectional view illustrating the semiconductor device 300 in the next stage of manufacturing. In the example shown in FIG. 6B , module stack 390 may be added to module 101 stacked on base substrate 310 , module interconnect 330 may be coupled to base substrate 310 and module stack ( 390) can be electrically connected. The module stack 390 may be attached to the upper surface of the base substrate 310 using an adhesive so that the second surface 110b of the substrate 110 faces upward. Accordingly, the external terminal 113 of the substrate 110 may be exposed. In some examples, the module 101 may be stacked on the top surface of the base substrate 310 in a zigzag pattern. Although the semiconductor device 300 is illustrated as including four modules 101 in FIG. 6B , the present invention is not limited thereto. In some examples, the semiconductor device 300 may include four or more or fewer modules 101 . Although the semiconductor device 300 is illustrated as including a module 101 and a module stack 390 in FIG. 6B , other modules or electronic devices of the present invention may be substituted for one or more of these modules 101 . There may be examples.

A module interconnect 330 may be electrically connected between an external terminal 113 of a module 101 and an internal base terminal 312 of a base substrate 310 or between external terminals 113 of another module 101 . there is. In some examples, module interconnect 330 may be referred to as a wire, conductive wire, or bond wire. Module interconnect 330 may include, for example, an electrically conductive material such as a metallic material, gold, silver, aluminum, or copper. In some examples, module interconnect 330 may be electrically connected between external terminal 113 of module 101 and internal base terminal 312 of base substrate 310 by wire bonding. The module interconnect 330 may provide electrical coupling between the module 101 and the base substrate 310 or between other modules 101 .

6C is a cross-sectional view illustrating the semiconductor device 300 in the next stage of manufacturing. In the example shown in FIG. 6C , encapsulant 340 may cover module stack 390 , module interconnect 330 , and base substrate 310 . The base interconnect 350 may be connected to an external base terminal 313 of the base substrate 310 . In some examples, encapsulant 340 may include corresponding components, features, materials, or forming processes similar to those of encapsulant 140 described above. The encapsulant 340 may protect the module stack 390 and the module interconnect 330 from external environments.

In some examples, the base interconnect 350 may include corresponding components, features, materials, or forming processes similar to those of the interconnect 150 described above. The base interconnect 350 may provide an electrical connection path between the semiconductor device 300 and an external component such as a motherboard or PCB board.

The modules of module stack 390 may include different orientations with respect to each other. In some examples, modules of module stack 390 may be coupled to other sides or margins of base substrate 310 via module interconnects 330 .

The base substrate 310 may include base margins 316 , 317 that are not covered by the space occupied by the module stack 390 . Base margins 316 and 317 of base substrate 310 may abut module stack sides 396 and 397 of module stack 390 , respectively. In some examples, the modules of the module stack 390 may include respective module terminals 113 of their respective substrates 110 on top of their respective modules. In this example, modules 101 of module stack 390 may include modules 3011 , 3012 , 3013 , 3014 stacked on top of base substrate 310 . The modules 3011 , 3013 are oriented in a first direction such that their respective module terminals 113 are adjacent to or closer to the module stack side 396 or base margin 316 than the module stack side 397 or base margin 317 . Heading. Conversely, modules 3012 , 3014 may be configured such that their respective module terminals 113 are adjacent to or closer to module stack side 397 or base margin 317 than module stack side 396 or base margin 316 . heading in the direction Module interconnect 330 extends from module terminal 113 of module 3011 , 3013 to base margin 316 of adjacent substrate 310 . Conversely, module interconnect 330 extends from module terminal 113 of module 3012 , 3014 to base margin 317 of adjacent substrate 310 .

This different orientation of the modules of the module stack 390 more evenly distributes the signal around the base substrate 310 compared to the scenario where all modules have the same orientation and are coupled to the same base margin or substrate 310 . allow to do This different orientation of the modules of the module stack 390 is compared to a scenario where all modules have the same orientation and some of the module interconnects 330 need instead to be routed to the base margin of the more distant substrate 310 , This allows the signal path of the interconnect 330 to be shorter and faster.

7 is a cross-sectional view illustrating an exemplary semiconductor device 300'. In the example shown in FIG. 7 , the semiconductor device 300 ′ may include a base substrate 310 , a module stack 390 ′, a module interconnect 330 , an encapsulant 340 , and a base interconnect 350 . can In some examples, the semiconductor device 300 ′ may include corresponding components, features, materials, or forming processes similar to those of the semiconductor device 300 described above. In some examples, modules may be stacked in an offset structure such that corresponding external terminals 113 of adjacent modules 101 are exposed. For example, the module stack 390 shown in FIGS. 5 and 6 includes an offset structure of modules in a staggered or zigzag pattern, and the module stack 390 ′ shown in FIG. 7 has an offset structure of modules in a stepped shape. includes

8 is a cross-sectional view illustrating an exemplary semiconductor device 400 . In the example shown in FIG. 8 , the semiconductor device 400 may include a substrate 110 , a device stack 420 , an internal interconnect 130 , an encapsulant 440a , 440b , and interconnects 450a , 450b . can

Device stack 420 may include a number of electronic devices 421 , 422 , 423 , 424 . Also, the plurality of electronic devices 421 , 422 , 423 , and 424 may include device terminals 421a , 422a , 423a , and 424a , respectively.

9A-9G are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device. 9A is a cross-sectional view illustrating the semiconductor device 400 in an initial stage of manufacturing.

In the example shown in FIG. 9A , a substrate 110 and electronic devices 421 , 422 may be attached to the top of the carrier 10 . The substrate 110 may include a cavity 111 , an inner terminal 112 , and an outer terminal 113 . In some examples, electronic devices 421 , 422 may include corresponding components, features, materials, or forming processes similar to those of electronic devices 121 , 122 , 123 , 124 described above. Electronic devices 421 and 422 may include device terminals 421a and 422a, respectively. Electronic devices 421 and 422 may be sequentially stacked within cavity 111 . In some examples, the first electronic device 421 can be attached to the top surface of the carrier 10 within the cavity 111 , and the second electronic device 422 is a first electronic device including a device terminal 421a . It may be attached to the upper surface of the first electronic device 421 using the adhesive 20 so that a portion of the upper surface of the 421 is exposed. Also, in the electronic devices 421 and 422 , the sum of the heights of the first and second electronic devices 421 and 422 may be formed to be smaller than the height of the substrate 110 .

9B is a cross-sectional view illustrating the semiconductor device 400 in the next stage of manufacturing. In the example shown in FIG. 9B , interconnect 450a may be electrically connected to inner terminal 112 on first side 110a of substrate 110 . The internal interconnect 130 may electrically connect the substrate 110 and the device terminals 421a and 422a of the electronic devices 421 and 422 , or electrically connect the device terminals 421a and 422a to each other. In some examples, interconnect 450a may include corresponding components, features, materials, or forming processes similar to those of interconnects 150 and 260 described above.

9C is a cross-sectional view illustrating the semiconductor device 400 in the next stage of manufacturing. In the example shown in FIG. 9C , encapsulant 440a may encapsulate electronic devices 421 , 422 and internal interconnect 130 . In addition, the encapsulant 440a may cover the first surface (top surface) 110a of the substrate 110 , and may encapsulate a portion of the interconnect 450a. An encapsulant 440a may also be formed within the cavity 111 between the substrate 110 and the electronic devices 421 , 422 . In some examples, encapsulant 440a may include corresponding components, features, materials, or forming processes similar to those of encapsulant 140 described above. The height of the encapsulant 440a may be in a range of about 120 μm to 150 μm. The encapsulant 440a may protect the devices 421 , 422 and the internal interconnect 130 from the external environment.

9D is a cross-sectional view illustrating the semiconductor device 400 in the next stage of manufacturing. In the example shown in FIG. 9D , the carrier 10 positioned under the substrate 110 may be removed. The substrate 110 may be turned over so that the second surface (lower surface) 110b of the substrate faces upward. With carrier 10 removed, electronic device 423 may be stacked on electronic device 421 , such that electronic devices 422 , 423 are stacked on opposite sides of electronic device 421 . The electronic device 423 protrudes from the encapsulant 440a and has sidewalls and a top surface (the side away from the electronic device 421 ) exposed from the encapsulant 440a .

In some examples, electronic device 424 can be stacked on electronic device 423 as part of device stack 420 . Electronic devices 423 and 424 may include device terminals 423a and 424a, respectively. In some examples, the third electronic device 423 can be attached on top of the first electronic device 421 using the adhesive 20 , and the fourth electronic device 424 includes a device terminal 423a. It may be attached to the top of the third electronic device 423 using the adhesive 20 to expose a portion of the top surface of the third electronic device 423 . In the device stack 420 , the device terminals 421a and 422a of the first and second electronic devices 421 and 422 face the first direction, and the device terminals 423a and 424a of the third and fourth electronic devices 423 and 424 are oriented in the first direction. ) may be stacked to face a second direction opposite to the first direction.

9E is a cross-sectional view showing the semiconductor device 400 in the next stage of manufacturing. In the example shown in FIG. 9E , interconnect 450b may be electrically connected to external terminal 113 of substrate 110 . The internal interconnect 130 may electrically connect the substrate 110 and the device terminals 423a , 424a of the electronic devices 423 , 424 , or electrically connect the device terminals 423a , 424a to each other. In some examples, interconnect 450b may include corresponding components, features, materials, or forming processes similar to those of interconnects 150 , 260 , 450a described above. In some examples, interconnect 450b may provide an electrical connection path between semiconductor device 400 and another semiconductor device or package stacked on semiconductor device 400 .

9F is a cross-sectional view showing the semiconductor device 400 in the next stage of manufacturing. In the example shown in FIG. 9F , encapsulant 400b can encapsulate electronic devices 423 , 424 , internal interconnect 130 , and interconnect 450b . In some examples, the encapsulant 440b may include corresponding components, features, materials, or forming processes similar to those of the encapsulant 440a described above. The encapsulant 440b may contact the encapsulant 440a and may cover the second surface 110b of the substrate 110 . The height of the encapsulant 440b may be in a range of about 120 μm to 150 μm. Encapsulant 440b may protect electronic devices 423 , 424 , internal interconnect 130 , and external interconnect 450b from external environments.

9G is a cross-sectional view showing the semiconductor device 400 in the next stage of manufacturing. In the example shown in FIG. 9G , the interconnect 450b may be exposed by forming an opening or via 441 in the encapsulant 440b, respectively. In some examples, the opening 441 may be formed by removing a portion of the encapsulant 440b by a sawing process, a grinding process, a laser process, or an etching process. In some examples, interconnect 450b extends partially through encapsulant 440b such that a top of interconnect 450b is lower than a top surface of encapsulant 440b, or is at a top surface of encapsulant 440b. sits down about In some examples, interconnect 450b extends completely through encapsulant 440b such that a top of interconnect 450b is substantially flush with a top surface of encapsulant 440b, or that of encapsulant 440b. It protrudes past the upper surface. In some examples, vias 441 contact or coincide with the shape or sidewalls of interconnect 450b , regardless of whether they partially or completely penetrate the top surface of encapsulant 440b .

10 is a cross-sectional view illustrating an exemplary semiconductor device 500 . In the example shown in FIG. 10 , the semiconductor device 500 may include a module stack 590 in which the semiconductor devices 400 are stacked on each other. In some examples, the semiconductor device 400 may be fabricated by the methods shown in FIGS. 9A-9G . Each semiconductor device 400 stacked on each other may be referred to as a module. Although the three modules 400 are illustrated as being stacked on each other, the present invention is not limited thereto. In some examples, in the semiconductor device 500 , three or more modules may be stacked or a smaller number of modules may be stacked. The modules 400 may be stacked such that the interconnects 450a and 450b are electrically connected to each other. In some examples, the interconnect 450b formed in the opening 441 of the module 400 and the interconnect 450a formed on the first side of the substrate of another module are melted or reflowed to each other, thereby electrically connecting the modules 400 to each other. can be connected to Although semiconductor device 500 is illustrated as including module 400 , there may be instances in which other modules or electronic devices of the present disclosure may be substituted for one or more of such modules 400 .

11 is a cross-sectional view illustrating an exemplary semiconductor device. In the example shown in FIG. 11 , the semiconductor device 600 may include a substrate 610 , a device stack 120 , an internal interconnect 130 , an encapsulant 140 , and an external interconnect 150 . In some examples, semiconductor device 600 may include or be referred to as module 601 .

The substrate 610 may include a substrate ledge 6101 and a substrate vertical 6102 . The substrate ledge 6101 may include a ledge 615 . Also, the substrate 610 may include a cavity 611 , an inner terminal 612 , and an outer terminal 613 . The device stack 120 may include a plurality of devices 121 , 122 , 123 , and 124 . Also, the plurality of devices 121 , 122 , 123 , and 124 may include device terminals 121a , 122a , 123a , and 124a, respectively.

Substrate 610 , internal interconnect 130 , encapsulant 140 , and external interconnect 150 may include or be referred to as a semiconductor package, wherein the semiconductor package comprises device stack 120 from external components or environmental exposure. can protect In addition, the semiconductor package may provide electrical coupling between the external components and the device stack 120 .

12A-12D are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device. 12A is a cross-sectional view illustrating the semiconductor device 600 in an initial stage of manufacturing.

In the example shown in FIG. 12A , the substrate 610 may be formed or attached to the top of the carrier 10 . The substrate 610 may include a cavity 611 . In some examples, the cavity 611 has a first width d1 and is formed thereafter with an aperture 610d1 penetrating the first side 610a and the second side 610b of the substrate 610 , An aperture 610d2 having a second width d2 and penetrating a portion of the substrate 610 may be included. The first width d1 may be smaller than the second width d2 (d1<d2). In some examples, the first width d1 may be defined or bounded by the substrate ledge 6101 and the second width d2 may be defined or bounded by the substrate vertical 6102 . In some examples, the cavity 611 may be formed by forming an aperture 610d2 having a second width d2 and forming an aperture 610d1 having a first width d1. In some examples, cavity 611 may be formed using a laser, blade, or punch tool. In some examples, the substrate ledge portion 6101 and the substrate vertical portion 6102 may be separate substrates coupled to each other, such as a unified substrate. In some examples, a first one of the substrate ledge 6101 (with or without aperture 610d1 ) or substrate vertical 6102 (with or without aperture 610d2 ) may be formed first, and the second One may be formed on the first one. In some examples, the cavity 611 may provide a space in which the device stack 120 may be seated.

The substrate 610 may include a substrate ledge 6101 having a ledge 615 and a substrate vertical 6102 . The substrate ledge portion 6101 may be defined as a lower portion of the substrate 610 , and may include a ledge 615 that protrudes laterally more toward the cavity 611 than the substrate vertical portion 6102 . The substrate vertical portion 6102 may be defined as an upper portion of the substrate 610 and may be located on the substrate ledge 6101 .

In some examples, the substrate 610 may include an inner terminal 612 and an outer terminal 613 . The inner terminal 612 may be formed in the ledge 615 . In some examples, inner terminal 612 or outer terminal 613 may include corresponding components, features, materials, or forming processes similar to those of inner terminal 112 or outer terminal 113 described above. . In some examples, internal terminal 612 may be provided as an electrical contact for routing electrical signals from substrate 610 to device stack 120 or for routing electrical signals from device stack 120 to substrate 610 . can

The external terminal 613 may be formed on the first surface (upper surface) 610a and the second surface (lower surface) 610b of the substrate 610 . The external terminal 613 located on the first surface 610a and the external terminal 613 located on the second surface 610b internally penetrate the substrate 610 by a substrate conductor or an internal circuit to be electrically connected to each other. there is. Also, the external terminal 613 may internally penetrate the substrate 610 by a substrate conductor or internal circuit to be electrically connected to the internal terminal 612 . In some examples, the external terminal 613 routes an electrical signal of the substrate 610 to an external component such as a motherboard or PCB board, or routes an electrical signal of an external component such as a motherboard or PCB board to the substrate 610 may be provided as electrical contacts for routing to

12B is a cross-sectional view illustrating the semiconductor device 600 in the next stage of manufacturing. In the example shown in FIG. 12B , a device stack 120 is formed in a cavity 611 , and an internal interconnect 130 is formed between the substrate 610 and the device stack 120 or the respective electronic devices 121 , 122 , 123 and 124) may be electrically connected. In some examples, the device stack 120 may be formed to be lower than the height of the substrate 610 .

In some examples, the internal interconnect 130 connects the internal terminal 612 on the ledge 615 of the substrate 610 to the device terminals 121a, 122a, 123a, 124a of the electronic devices 121 , 122 , 123 , 124 . It can be electrically connected to any of them. In some examples, incorporation of the ledge 615 may reduce the size, particularly the height, of the semiconductor device 600 . In some examples, internal interconnect 130 may electrically couple device terminals 121a , 122a , 123a , 124a to each other.

12C is a cross-sectional view showing the semiconductor device 600 in the next stage of manufacturing. In the example shown in FIG. 12C , encapsulant 140 may encapsulate device stack 120 and internal interconnect 130 . In some examples, the encapsulant 140 may be formed in the cavity 611 , and the first surface 610a of the substrate 610 may be exposed to the outside. The encapsulant 140 may protect the device stack 120 and the internal interconnect 130 from external environments.

12D is a cross-sectional view showing the semiconductor device 600 in the next stage of manufacturing. In the example shown in FIG. 12D , the carrier 10 located under the substrate 610 may be removed, and the external interconnect 150 may be connected to the external terminal 613 . In some examples, the carrier 10 may be separated from the substrate 610 , and the external terminal 613 positioned on the second surface 610b of the substrate 610 may be exposed. The external interconnect 150 may provide an electrical connection path between the semiconductor device 600 and an external component such as a motherboard or PCB board.

13 is a cross-sectional view illustrating an exemplary semiconductor device 700 . In the example shown in FIG. 13 , the semiconductor device 700 may include a module stack 790 in which modules 601 are stacked on top of each other, an interface structure 730 , and an external interconnect 150 . In some examples, the semiconductor device 700 may be formed by stacking the modules 601 of FIGS. 12 and 13 . Although four modules 601 are shown, the present invention is not limited thereto. In another example, the semiconductor device 700 may be formed by stacking four or more or fewer modules 601 . Although semiconductor device 700 is illustrated as including modules 601 , there may be instances in which other modules or other electronic devices of the present invention may be substituted for one or more of such modules 601 .

Modules 601 may be coupled together via interface structure 730 and electrically connected to each other. In some examples, the interface structure 730 may include a conductive adhesive, such as an anisotropic conductive film (AFC). The conductive adhesive 760 may include an insulating layer and conductive particles such as metal particles or metal-coated polymer particles dispersed in the insulating layer. In some examples, the conductive adhesive 730 may be interposed between the modules 601 to receive heat and pressure, and the external terminals 613 may be electrically connected to each other by conductive particles. A portion of the conductive adhesive 730 without the external terminal 613 may be electrically insulated from each other by an insulating layer. In some examples, conductive adhesive 730 or conductive particles thereof may include or refer to an interconnect. The external interconnect 150 may be connected to an external terminal 613 of a lowermost module of the semiconductor device 700 . There may be instances where the interconnect structure 730 includes an interconnect similar to the interconnect 150 in addition to or in place of a conductive adhesive to couple other modules of the semiconductor device 700 .

14 is a cross-sectional view illustrating an exemplary semiconductor device 700'. In the example shown in FIG. 14 , the semiconductor device 700 ′ includes a base substrate 310 , a module stack 790 on which the modules 601 are stacked, a conductive adhesive 730 , an encapsulant 340 , and an external interconnect. (350). The base substrate 310 may include an inner base terminal 312 on a first surface (upper surface) and an outer base terminal 313 on a second surface (lower surface) opposite to the first surface. In some examples, semiconductor device 700 ′ including a package of modules 601 may include or be referred to as a package-in-package (PIP) device.

In some examples, the semiconductor device 700 ′ may be formed by stacking the modules 601 on a base substrate 310 . In some examples, the modules 601 may be laminated together using a conductive adhesive 730 . In some examples, modules 601 may be stacked on top of each other using respective interconnects 150 . The encapsulant 340 may encapsulate the module 601 and the top of the base substrate 310 , and the external interconnect 350 is electrically connected to the external base terminal 313 of the base substrate 310 . can be connected Although semiconductor device 700 ′ is illustrated as including modules 601 , there may be instances in which other modules or other electronic devices of the present invention may be substituted for one or more of such modules 601 .

15 is a cross-sectional view illustrating an exemplary semiconductor device 800 . In the example shown in FIG. 15 , the semiconductor device 800 may include a substrate 110 , a device stack 120 , an internal interconnect 130 , an encapsulant 840 , and an external interconnect 150 . In some examples, semiconductor device 800 may include or be referred to as module 801 . In some examples, module 801 may include corresponding components, features, materials, or forming processes similar to other modules described in this disclosure.

The substrate 110 may include a shelf 116 . The shelf 116 may be positioned toward the edge or end of the substrate 110 where the encapsulant 840 is not formed. The shelf 116 may protrude to one side of the semiconductor device 800 because it is not encapsulated by the encapsulant 840 . The inner terminal 112 located on the shelf 116 may be exposed on the first surface 110a of the substrate 110 .

In some examples, encapsulant 840 may include corresponding components, features, materials, or forming processes similar to those of encapsulant 140 described above. The encapsulant 840 may include a recessed sidewall 846 . Encapsulant 840 may encapsulate device stack 120 and internal interconnect 130 . An encapsulant 840 may also be formed between the device stack 120 and the substrate 110 in the cavity 111 . In some examples, the encapsulant 840 encapsulates only a portion of the first side 110a of the substrate 110 such that the recessed sidewall 846 is located inside the footprint of the substrate 110 . can make it happen The encapsulant 840 may expose a portion of the first surface 110a of the substrate 110 . In some examples, the encapsulant 840 can completely encapsulate the first side 110a of the substrate 110 , after which a portion of the encapsulant 840 is removed to remove the recessed sidewall 846 . ) can be formed. In some examples, a portion of encapsulant 840 may be removed by an etching process. Because the encapsulant 840 encapsulates only a portion of the first side 110a of the substrate 110 , the substrate 110 may include a shelf 116 . The recessed sidewall 846 may be perpendicular to the first side 110a of the substrate 110 . The encapsulant 840 may protect the substrate 110 , the device stack 120 , and the internal interconnect 130 from external environments.

The substrate 110 , the inner interconnect 130 , the encapsulant 840 , and the outer interconnect 150 may include or be referred to as a semiconductor package, and the device stack 120 from external components or environmental exposures. ) can be protected. In addition, the semiconductor package may provide electrical coupling between the external components and the device stack 120 .

16 is a cross-sectional view illustrating an exemplary semiconductor device 900 . In the example shown in FIG. 16 , the semiconductor device 900 may include a substrate 110 , a device stack 120 , an internal interconnect 130 , an encapsulant 940 , and an external interconnect 150 . . In some examples, semiconductor device 900 may include or be referred to as module 901 . In some examples, module 901 may include corresponding components, features, materials, or forming processes similar to other modules described in this disclosure.

The substrate 110 may include a shelf 116 . Shelf 116 may be positioned towards an edge or end of substrate 110 where encapsulant 940 is not formed. The shelf 116 may protrude to one side of the semiconductor device 900 because it is not encapsulated by the encapsulant 940 . The inner terminal 112 located on the shelf 116 may be exposed on the first surface 110a of the substrate 110 .

In some examples, encapsulant 940 may include corresponding components, features, materials, or forming processes similar to those of encapsulant 140 previously described. The encapsulant 940 may include a recessed sidewall 946 . The encapsulant 940 may encapsulate the device stack 120 and the internal interconnect 130 . An encapsulant 940 may also be formed in the cavity 111 between the device stack 120 and the substrate 110 . In some examples, the encapsulant 940 encapsulates only a portion of the first side 110a of the substrate 110 such that the recessed sidewall 946 is located inside the footprint of the substrate 110 . can make it happen The encapsulant 940 may expose a portion of the first surface 110a of the substrate 110 . In some examples, the encapsulant 940 may completely encapsulate the first side 110a of the substrate 110 , after which a portion of the encapsulant 940 is removed to remove the recessed sidewall 946 . ) can be formed. In some examples, a portion of the encapsulant 940 may be removed using a laser. The recessed sidewall 946 may be formed at an angle with respect to the first surface 110a of the substrate 110 . In some examples, the angle α formed between the first face 110a of the substrate 110 and the recessed sidewall 946 may be an acute angle. The encapsulant 940 may protect the substrate 110 , the device stack 120 , and the internal interconnect 130 from external environments.

The substrate 110 , the inner interconnect 130 , the encapsulant 940 , and the outer interconnect 150 may include or be referred to as a semiconductor package, and the device stack 120 from external components or environmental exposures. ) can be protected. In addition, the semiconductor package may provide electrical coupling between the external components and the device stack 120 .

17 is a cross-sectional view illustrating an exemplary semiconductor device 1000 . In the example shown in FIG. 17 , the semiconductor device 1000 can include a base substrate 310 , a module 801 , a module interconnect 1030 , an encapsulant 340 , and a base interconnect 350 . . In some examples, the semiconductor device 1000 including the stacked module 801 may include or refer to a package-in-package (PIP) apparatus. In some examples, the module semiconductor device 1000 may include corresponding components, features, materials, or forming processes similar to those of other semiconductor devices described in this disclosure.

In some examples, the semiconductor device 1000 may be formed by stacking the module 801 on the base substrate 310 . The module 801 may be attached to the upper surface of the base substrate 310 using an adhesive member that directs the substrate 110 downward. Modules 801 may be laminated to the top surface of base substrate 310, for example in a stepped or zigzag fashion, to expose internal terminals 112 located on protrusions 116 of adjacent modules 801. there is. In some examples, module interconnect 1030 may include corresponding components, features, materials, or forming processes similar to those of module interconnect 330 previously described. The module interconnect 1030 may be electrically connected between the inner terminal 112 of the module 801 and the inner base terminal 312 of the base substrate 310 or between the inner terminal 112 of the module 801 . In some examples, module interconnect 1030 can be electrically connected to inner terminal 112 located outside recessed sidewall 846 . Because the module interconnect 1030 is connected to the inner terminal 112 located on the shelf 116 , the height of the semiconductor device 1000 can be reduced. The module interconnect 1030 may provide electrical coupling between the module 801 and the base substrate 310 , or between the module 801 . In some examples, the module interconnect 1030 may be formed not to exceed the height of the top module 801 , and the top module 801 may be exposed at the top side of the encapsulant 340 .

The encapsulant 340 may encapsulate the module 801 and the module interconnect 1030 . In some examples, encapsulant 340 may include corresponding components, features, materials, or forming processes similar to those of encapsulant 140 previously described. The encapsulant 340 may protect the module 801 and the module interconnect 1030 from the external environment.

18 is a cross-sectional view illustrating an exemplary semiconductor device 1000'. In the example shown in FIG. 18 , the semiconductor device 1000 ′ may include a base substrate 310 , a module 901 , a module interconnect 1030 , an encapsulant 340 , and a base interconnect 350 . there is. In some examples, semiconductor device 1000 ′ may include corresponding components, features, materials, or forming processes similar to semiconductor device 1000 previously described.

In some examples, the semiconductor device 1000 ′ including the stacked module 901 may include or be referred to as a package-in-package (PIP) device. In some examples, the module semiconductor device 1000 ′ may include corresponding components, features, materials, or forming processes similar to those of other semiconductor devices described in this disclosure.

In some examples, the semiconductor device 1000 may be formed by stacking the module 901 on the base substrate 310 . The module 901 may be attached to the upper surface of the base substrate 310 using an adhesive member that directs the substrate 110 downward. Modules 901 may be laminated to the top surface of base substrate 310, for example in a stepped or zigzag fashion, to expose internal terminals 112 located on protrusions 116 of adjacent modules 901. there is.

In some examples, module interconnect 1030 may include corresponding components, features, materials, or forming processes similar to those of module interconnect 330 previously described. The module interconnect 1030 may be electrically connected between the inner terminal 112 of the module 901 and the inner base terminal 312 of the base substrate 310 or between the inner terminal 112 of the module 901 . In some examples, module interconnect 1030 can be electrically connected to inner terminal 112 located outside recessed sidewall 946 . Because the module interconnect 1030 is connected to the inner terminal 112 located on the shelf 116 , the height of the semiconductor device 1000 can be reduced. Module interconnect 1030 may provide electrical coupling between module 901 and base substrate 310 , or between module 901 . In some examples, the module interconnect 1030 may be formed so as not to exceed the height of the top module 901 , and the top module 901 may be exposed at the top side of the encapsulant 340 .

19 is a cross-sectional view illustrating an exemplary semiconductor device 1100 . In the example shown in FIG. 19 , semiconductor device 1100 includes substrate 110 , device stack 120 , internal interconnect 130 , encapsulant 1140 , external interconnect 150 , and vertical interconnect 1160 . ). In some examples, the semiconductor device 1100 may include or be referred to as a module 1101 . In some examples, module 1101 may include corresponding components, features, materials, or forming processes similar to other modules described in this disclosure.

Vertical interconnect 1160 may be electrically connected to inner terminal 112 of substrate 110 . The vertical interconnect 1160 may be exposed at the top surface of the encapsulant 1140 . In some examples, the top surface of the vertical interconnect 1160 will be substantially coplanar with the top surface of the encapsulant 1140 . can In some examples, vertical interconnect 1160 may include or refer to metal posts, conductive posts, copper posts, copper posts, vertical wirebonds, through-mold-vias, solder balls, or copper core solder balls. In some examples, after encapsulant 1140 is formed on substrate 110 , vertical interconnect 1160 may be formed to pass through encapsulant 1140 . In some examples, after vertical interconnect 1160 is formed at inner terminal 112 of substrate 110 , encapsulant 1140 may encapsulate vertical interconnect 1160 . Vertical interconnect 1160 may include, for example, an electrically conductive material such as gold, silver, aluminum, or copper or a metallic material. Also, the height of the vertical interconnect 1160 may be the same as the encapsulant 1140 formed on the first side 110a of the substrate 110 . Vertical interconnect 1160 may provide electrical coupling between substrate 110 and an external device.

In some examples, encapsulant 1140 may include corresponding components, features, materials, or forming processes similar to those of encapsulant 140 described above. Encapsulant 1140 may encapsulate device stack 120 , internal interconnect 130 , and vertical interconnect 1160 . An encapsulant 1140 may also be formed in the cavity 111 between the device stack 120 and the substrate 110 . The encapsulant 1140 may expose a top surface of the vertical interconnect 1160 . Encapsulant 1140 may protect substrate 110 , device stack 120 , internal interconnect 130 , and vertical external interconnect 1160 from external environments. 110.

Substrate 110 , internal interconnect 130 , encapsulant 1140 , external interconnect 150 , and vertical interconnect 1160 may include or be referred to as semiconductor packages, and may be exposed to external elements or environments. It is possible to protect the device stack 120 from In addition, the semiconductor package may provide electrical coupling between the external components and the device stack 120 .

20 is a cross-sectional view illustrating an exemplary semiconductor device 1200 . In the example shown in FIG. 20 , the semiconductor device 1200 can include a base substrate 310 , a module 1101 , a module interconnect 1230 , an encapsulant 340 , and a base interconnect 350 . . In some examples, the semiconductor device 1200 including the stacked module 1101 may include or be referred to as a package-in-package (PIP) device. In some examples, the module semiconductor device 1200 may include corresponding components, features, materials, or forming processes similar to other semiconductor devices described in this disclosure.

In some examples, the semiconductor device 1200 may be formed by stacking the module 1101 on the base substrate 310 . The module 1101 may be attached to the upper surface of the base substrate 310 using an adhesive member that directs the substrate 110 downward. In some examples, modules 1101 may be stacked on the top surface of base substrate 310 in a stepped or zigzag fashion to expose vertical interconnects 1160 of adjacent modules 1101 .

In some examples, module interconnect 1230 may include corresponding components, features, materials, or forming processes similar to module interconnect 330 described above. The module interconnect 1230 may be electrically connected between the vertical interconnect 1160 of the module 1101 and the internal base terminal 312 of the base substrate 310, or between the vertical interconnect 1160 of the stacked module 1101. can Module interconnect 1230 may provide electrical coupling between module 1101 and base substrate 310 , or between module 1101 .

The encapsulant 340 may encapsulate the module 1101 and the module interconnect 1230 and protect it from the external environment.

21 is a cross-sectional view illustrating an exemplary semiconductor device 1300 . In the example shown in FIG. 21 , the semiconductor device 1300 may include a substrate 1310 , a device stack 120 , an internal interconnect 130 , and an encapsulant 1340 . In some examples, the semiconductor device 1300 may include or be referred to as a module 1301 . In some examples, module 1300 may include corresponding components, features, materials, or forming processes similar to other modules described in this disclosure.

In some examples, the substrate 1310 may include corresponding components, features, materials, or forming processes similar to those of the substrate 110 described above. For example, the substrate 1310 includes a cavity 1311 , an inner terminal 1312 , and an outer terminal 1313 , which include a cavity 111 of the substrate 110 , an inner terminal 112 , and It may be correspondingly similar to the external terminal 113 . In this example, the cavity 1311 may be formed on one surface of the substrate 1310 .

The substrate 1310 may be positioned on a side surface of the semiconductor device 1300 . In some examples, the substrate 1310 may include or refer to a partial substrate or a side substrate, wherein at least one side of the device stack 120 is bounded by the substrate 1310 and the device stack 120 . ) is unbounded by the substrate 1310 . For example, the substrate 1310 may be formed in an open rectangle or ('c') shape in which at least one side of the rectangular frame of the substrate 110 shown in FIG. 2H may be omitted. In some examples, the substrate 1310 may be formed asymmetrically. Since the substrate 1310 has a smaller width than the substrate 110 illustrated in FIG. 2H , the semiconductor device 1300 can be reduced in size.

The cavity 1311 may be formed to pass through the substrate 1310 . For example, the cavity 1311 may be formed by removing a portion of the substrate 1310 . In some examples, cavity 1311 may be formed by cutting a portion of substrate 1310 using a laser or blade. In some examples, the cavity 1311 may provide a space in which the device stack 120 may be mounted.

In some examples, encapsulant 1340 may include corresponding elements, features, materials, or forming processes similar to those of encapsulant 140 previously described. The encapsulant 1340 may encapsulate the device stack 120 and the internal interconnect 130 . An encapsulant 1340 may also be formed in the cavity 1311 between the device stack 120 and the substrate 1310 .

The substrate 1310 , the internal interconnect 130 , and the encapsulant 1340 may include or be referred to as a semiconductor package, and may protect the device stack 120 from external elements or environmental exposure. In addition, the semiconductor package may provide electrical coupling between the external components and the device stack 120 .

22 is a cross-sectional view illustrating an exemplary semiconductor device 1400 . In the example shown in FIG. 22 , the semiconductor device 1400 can include a base substrate 310 , a module 1301 , a module interconnect 330 , an encapsulant 340 , and a base interconnect 350 . . In some examples, semiconductor device 1400 can include corresponding elements, features, materials, or forming processes similar to semiconductor device 300 previously described. In some examples, the semiconductor device 1400 including a package of modules 1301 may include or be referred to as a package-in-package (PIP) device. In some examples, the module semiconductor device 1400 can include corresponding elements, features, materials, or forming processes similar to other semiconductor devices previously described.

In some examples, semiconductor device 1400 may be formed by stacking module 1301 on base substrate 310 . The module 1301 may be attached to the upper surface of the base substrate 310 using an adhesive member so that the substrate 1310 faces upward. In some examples, the modules 1301 may be stacked on the top surface of the base substrate 310 in a stepped or zigzag fashion to expose the external terminals 1313 of adjacent modules 1301 .

The module interconnect 330 is to be electrically connected between the external terminal 1313 of the module 1301 and the internal base terminal 312 of the base substrate 310, or between the external terminal 1313 of the stacked module 1301. can Module interconnect 330 may provide electrical coupling between module 1301 and base substrate 310 , or between stacked modules 1301 .

23 is a cross-sectional view illustrating an exemplary semiconductor device 1500 . In the example shown in FIG. 23 , semiconductor device 1500 includes substrate 110 , device stack 120 , internal interconnect 130 , encapsulant 1540 , external interconnect 150 , and stack cap 1570 . ) may be included. In some examples, semiconductor device 1500 may include or be referred to as module 1501 . In some examples, module 1501 may include corresponding components, features, materials, or forming processes similar to other modules described in this disclosure.

The stack cap 1570 may be mounted on the device stack 120 . In some examples, the stack cap 1570 may be attached to the top side of the fourth electronic device 124 positioned on top of the device stack 120 using an adhesive member. The stack cap 1570 may be exposed from the upper side of the encapsulant 1540 . In some examples, the top surface of the stack cap 1570 may be coplanar with the top surface of the encapsulant 1540 . Also, the width of the stack cap 1570 may be smaller than the width of the device stack 120 . In some examples, the stack cap 1570 may be positioned at the center of the fourth electronic device 124 to expose the device terminals 124a positioned on the side of the fourth electronic device 124 . In some examples, stack cap 1570 may include or be referred to as an insert die, a dummy die, or a silicon die. Stack cap 1570 may include, for example, a semiconductor material such as silicon (Si). In some examples, the coefficient of thermal expansion of the stack cap 1570 is closer to the coefficient of thermal expansion of the electronic devices 121-124 in the device stack 120 than the coefficient of thermal expansion of the encapsulant 1540 . In some examples, the coefficient of thermal expansion of the stack cap 1570 may be substantially equal to the coefficient of thermal expansion of the electronic devices 121-124 in the device stack 120 . In some examples, the stack cap 1570 may suppress distortion caused by a difference in coefficient of thermal expansion between the device stack 120 and the encapsulant 1540 . In some examples, stack cap 1570 can provide a heat dissipation path for device stack 120 .

In some examples, encapsulant 1540 may include corresponding components, features, materials, or forming processes similar to those of encapsulant 140 previously described. Encapsulant 1540 may encapsulate device stack 120 , internal interconnect 130 , and stack cap 1570 . In some examples, encapsulant 1540 may expose a top surface of stack cap 1570 . The encapsulant 1540 may protect the substrate 110 , the device stack 120 , the internal interconnect 130 , and the stack cap 1570 from an external environment.

In some examples, the module 1501 may be stacked on the base substrate 310 to form a stacked module semiconductor device, which may be similar to other stacked module semiconductor devices described in this disclosure. .

24 is a cross-sectional view illustrating an exemplary semiconductor device 1600 . In the example shown in FIG. 24 , semiconductor device 1600 includes substrate 110 , device stack 120 , internal interconnect 130 , encapsulant 1640 , external interconnect 150 , and stack cap 1570 . ) may be included. In some examples, a semiconductor device module 1601 may be included or referred to as a module 1601 . In some examples, module 1601 may include corresponding components, features, materials, or forming processes similar to other modules described in this disclosure.

Encapsulant 1640 may encapsulate device stack 120 , internal interconnect 130 , and stack cap 1570 . Encapsulant 1640 may include sidewalls 1646 . In some examples, encapsulant 1640 can completely encapsulate the top of substrate 110 and edges or corners of encapsulant 1640 can be removed, thereby forming sidewall 1646 . can do. A portion of the encapsulant 1640 may be removed using a laser. The sidewall 1646 may be inclined with respect to the first side 110a of the substrate 110 . In some examples, the angle formed between the first side 110a of the substrate 110 and the sidewall 1646 may be an acute angle.

The substrate 110 , the internal interconnect 130 , the encapsulant 1640 , and the stack cap 1570 may include or be referred to as a semiconductor package, and the device stack 120 from external elements or environmental exposure. can protect In addition, the semiconductor package may provide electrical coupling between the external components and the device stack 120 .

In some examples, a module 1601 may be stacked on a base substrate 310 to form a stacked module semiconductor device, which may be similar to other stacked module semiconductor devices described in this disclosure.

25 is a cross-sectional view illustrating an exemplary semiconductor device 1700 . In the example shown in FIG. 25 , semiconductor device 1700 includes substrate 110 , device stack 120 , internal interconnect 130 , encapsulant 1740 , external interconnect 150 , and stack cap 1570 . ) may be included. In some examples, semiconductor device 1600 may include or be referred to as module 1701 . In some examples, module 1701 may include corresponding components, features, materials, or forming processes similar to other modules described in this disclosure.

The substrate 110 may include a shelf 1716 . A shelf 1716 may be positioned at opposite ends of the substrate 110 , and an encapsulant 1740 may leave the shelf 1716 exposed. Because shelf 1716 is not encapsulated by encapsulant 1740 , shelf 1716 can protrude away from semiconductor device 1700 . The inner terminal 112 positioned on the shelf 1716 may be exposed on the first surface 110a of the substrate 110 . In some examples, external interconnect 150 may be coupled to external terminal 113 under each shelf 1716 of substrate 110 outside a vertical footprint defined by the perimeter of encapsulant 1740 . there is.

The encapsulant 1740 may include a recessed sidewall 1746 . In some examples, the encapsulant 1740 may encapsulate only a portion of the first side 110a of the substrate 110 such that the recessed sidewall 1746 may be positioned within the substrate 110 . there is. The encapsulant 1740 may expose a portion of the first surface 110a of the substrate 110 . In some examples, the encapsulant 1740 completely encapsulates the first side 110a of the substrate 110 and then removes a portion of the encapsulant 1740 located at the edge of the substrate 110 . may be removed to form a recessed sidewall 1746 . A portion of the encapsulant 1740 may be removed using a laser. The recessed sidewall 1746 may be formed to be inclined with respect to the first surface 110a of the substrate 110 . In some examples, the angle formed between the first face 110a of the substrate 110 and the recessed sidewall 1746 may be an acute angle.

26 is a cross-sectional view illustrating an exemplary semiconductor device 1800 . In the example shown in FIG. 26 , the semiconductor device 1800 can include a base substrate 310 , a module 1701 , an encapsulant 1840 , and a base interconnect 350 . In some examples, the semiconductor device 1800 including the package of the module 1701 may include or be referred to as a package-in-package (PIP) device. In some examples, module semiconductor device 1800 can include corresponding components, features, materials, or forming processes similar to other semiconductor devices described in this disclosure, such as semiconductor device 300 .

In some examples, semiconductor device 1800 may be formed by stacking module 1701 on base substrate 310 . Module 1701 may be stacked such that external interconnect 150 is electrically connected to internal base terminal 312 of base substrate 310 . In some examples, the modules 1701 may be stacked on the base substrate 310 in a straight vertical shape instead of a step shape or a zigzag shape. In some examples, modules 1701 can be stacked so that external interconnects 150 can be positioned on shelves 1716 of adjacent modules 1701 and external interconnects 150 to internal terminals 112 of adjacent modules 1701. may be electrically connected. In a sub-example, modules 1701 may be stacked such that a device stack 120 contacts a stack cap 1570 of an adjacent module 1701 . In some examples, external interconnect 150 may act on base substrate 210 or in conjunction with interconnect modules 1701 , and perform a function similar to module interconnect 330 without wire bonding (e.g., FIG. 3 ) , 7) can be referred to as a module interconnect.

While the present invention includes reference to specific embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, modifications may be made to the disclosed examples without departing from the scope of the present invention. Accordingly, it is intended that the invention not be limited to the examples disclosed, but will include all examples falling within the scope of the appended claims.

Claims (20)

A first substrate surface, a second substrate surface opposite to the first substrate surface, an outer wall of the substrate between the first substrate surface and the second substrate surface, and a cavity between the first substrate surface and the second substrate surface a substrate having an inner wall of the substrate;
a device stack positioned within the cavity, the device stack having a first electronic device and a second electronic device stacked on the first electronic device;
a first internal interconnect coupled to the substrate and the device stack;
and an encapsulant covering the inner wall of the substrate and the device stack and filling the cavity. The method of claim 1,
the substrate includes a substrate shelf adjacent a first edge of the substrate;
the substrate shelf includes an inner terminal on the first substrate side;
The encapsulant covers the first substrate surface, and the substrate shelf and the inner terminal are left exposed. 3. The method of claim 2,
the encapsulant includes a sidewall recessed at the interface with the substrate shelf;
wherein the recessed sidewall is inclined at an acute angle with the first substrate plane. The method of claim 1,
a vertical interconnect coupled to the first inner terminal of the first substrate face;
wherein the vertical interconnect extends through the encapsulant and is exposed on top of the encapsulant. The method of claim 1,
wherein at least one side of the device stack is not bounded by a substrate. The method of claim 1,
Further comprising a stack cap on top of the device stack,
the stack cap includes a cap coefficient of thermal expansion;
the device stack includes a device coefficient of thermal expansion;
the encapsulant comprises an encapsulant coefficient of thermal expansion;
wherein the cap thermal expansion coefficient is closer to the device thermal expansion coefficient than the encapsulant thermal expansion coefficient. 7. The method of claim 6,
wherein the cap coefficient of thermal expansion is substantially equal to the device coefficient of thermal expansion. The method of claim 1,
Further comprising a stack cap on the top of the device stack,
the stack cap is exposed on top of the encapsulant;
wherein the device stack is exposed on a bottom surface of the encapsulant. The method of claim 1,
a first external interconnect; and
a second external interconnect;
the substrate includes a substrate first shelf adjacent a first edge of the substrate, and a first external terminal on a second substrate surface below the first shelf;
the substrate includes a second shelf of the substrate adjacent a second edge of the substrate, and a second external terminal on a second surface of the substrate below the second shelf;
the encapsulant covers the surface of the first substrate, leaving the substrate first shelf and the substrate second shelf exposed;
a first external interconnect coupled to a first external terminal under the first shelf outside a footprint of the encapsulant;
and a second external interconnect coupled to a second external terminal below the second shelf outside the footprint of the encapsulant. receiving a substrate, wherein the substrate is
a first substrate surface;
a second substrate surface opposite to the first substrate surface;
a substrate outer wall between the first substrate surface and the second substrate surface; and
a substrate inner wall defining a cavity between the first substrate surface and the second substrate surface;
providing a device stack within the cavity, the device stack comprising:
a first electronic device; and
a second electronic device stacked on the first electronic device;
providing a first internal interconnect coupled to the substrate and the device stack;
and providing an encapsulant covering the substrate inner wall and the device stack and filling the cavity. 11. The method of claim 10,
providing a vertical interconnect coupled to the first internal terminal on the first substrate surface prior to providing the encapsulant;
wherein the vertical interconnect extends through the encapsulant and is exposed on a top surface of the encapsulant. 11. The method of claim 10,
and providing a stack cap on a top surface of the device stack. 11. The method of claim 10,
the substrate includes a substrate first shelf adjacent to a first edge of the substrate, and a first external terminal on a second substrate face under the first shelf;
the substrate includes a substrate second shelf adjacent to a second edge of the substrate, and a second external terminal on a second substrate face under the second shelf;
the encapsulant covers the surface of the first substrate, leaving the first front of the substrate and the second shelf of the substrate exposed;
the method
providing a first external interconnect coupled to the first external terminal on the underside of a first shelf, outside the footprint of the encapsulate; and
and providing a second external interconnect coupled to the second external terminal on the underside of the second shelf, outside the footprint of the encapsulate. a base substrate having a first side and an internal base terminal on the first side;
a first module on the base substrate, the first module comprising:
a first substrate surface;
a second substrate surface opposite to the first substrate surface;
a substrate outer sidewall between the first substrate surface and the second substrate surface; and
a substrate comprising a substrate inner sidewall defining a cavity between the first substrate surface and the second substrate surface;
a first electronic device; and
a device stack comprising a second electronic device stacked on the first electronic device;
a first internal interconnect coupled to the substrate and the device stack; and
a first encapsulant covering the inner sidewall of the substrate and the device stack and filling the cavity;
a second module on the first module; and
and a second encapsulant on the base substrate and in contact with horizontal surfaces of the first module and the second module. 15. The method of claim 14,
and a module interconnect within the second encapsulant and coupled with an internal base terminal and a substrate of the first module. 16. The method of claim 15,
the substrate of the first module includes a substrate shelf adjacent a first edge of the substrate;
the substrate shelf includes internal terminals on the first substrate surface;
the first encapsulant covers the first substrate, leaving the substrate shelf and inner terminals exposed; and
wherein the module interconnect is coupled to the inner terminal. 17. The method of claim 16,
the first encapsulant includes a sidewall recessed at an interface with the first substrate shelf; and
wherein the recessed sidewall is inclined at an acute angle with respect to the first substrate surface. 16. The method of claim 15,
the first module includes a vertical interconnect coupled to a first internal terminal on the first substrate surface;
the vertical interconnect extends through the first encapsulant and is exposed at a top surface of the first encapsulant; and
and the module interconnect is coupled to the substrate via the vertical interconnect. 15. The method of claim 14,
wherein the first module includes a stack cap on a top surface of the device stack. 15. The method of claim 14,
and an external interconnect in the second encapsulant contacting a top surface of the base substrate and a bottom surface of the substrate of the first module.

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