KR20220022644A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

Embodiments of the present invention provide a semiconductor device having a lower plug and a protective spacer capable of reducing process defects and improving the device characteristics, and a method for fabricating the same. The semiconductor device of the present technology comprises: conductive line patterns on a substrate; a lower plug comprising a pillar part positioned between the conductive line patterns and an extension part extending from the pillar part and overlapping one of the conductive line patterns; a capping layer covering a sidewall of the lower plug; and a protective spacer positioned between the lower plug and the capping layer.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a lower plug and a protective spacer and a method for manufacturing the same.

As the degree of integration of semiconductor devices increases, the area occupied by the storage node contact plug is decreasing. Accordingly, since a process defect occurs when the storage node contact plug is formed, a technique for preventing process defect by forming a lower plug including a pillar part and an extension part has been proposed.

SUMMARY Embodiments of the present invention provide a semiconductor device having a lower plug and a protective spacer capable of reducing process defects and improving device characteristics, and a method of manufacturing the same.

A semiconductor device according to an embodiment of the present invention includes a lower plug including conductive line patterns on a substrate, a pillar portion positioned between the conductive line patterns, and an extension portion extending from the pillar portion and overlapping any one of the conductive line patterns; It may include a capping layer covering the sidewall of the lower plug, and a protective spacer positioned between the lower plug and the capping layer.

In the present technology, process defects can be reduced by forming a lower plug including an extension part.

According to the present technology, poor contact between the lower plug and the adjacent active region can be prevented by forming the protective spacer.

According to the present technology, the contact resistance can be improved by forming the ohmic contact layer at a level higher than the upper surface of the bit line structure.

According to the present technology, the contact defect between the contact and the memory element can be improved by making the upper plug wider.

1 is a top view illustrating a semiconductor device according to an exemplary embodiment.
2A is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment.
2B is a perspective view of the semiconductor device of FIG. 2A.
FIG. 2C is a cross-sectional view of the semiconductor device of FIG. 1 .
3A to 3O are one example of a method of manufacturing a semiconductor device according to an embodiment.
4A to 4G are cross-sectional views illustrating a semiconductor device according to an exemplary embodiment.
5 is a top view illustrating a semiconductor device according to an exemplary embodiment.
6 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment.
7A to 7S are one example of a method of manufacturing a semiconductor device according to an embodiment.

Since the embodiments described in this specification will be described with reference to a cross-sectional view, a plan view, and a block diagram, which are ideal schematic views of the present invention, the form of the illustrative view may be modified due to manufacturing technology and/or tolerance. Accordingly, embodiments of the present invention are not limited to the specific form shown, but also include a change in form generated according to a manufacturing process. That is, the regions illustrated in the drawings have schematic properties, and the shapes of the regions illustrated in the drawings are intended to illustrate a specific shape of the region of the device, and not to limit the scope of the invention. The thickness and spacing in the drawings are expressed for convenience of description, and may be exaggerated compared to the actual physical thickness. In the description of the present invention, well-known components irrelevant to the gist of the present invention may be omitted. In adding reference numbers to the components of each drawing, it should be noted that only the same components are given the same number as possible even though they are indicated on different drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Although the description has been made with reference to DRAM for simplicity of description, the inventive concept is not limited thereto, and may be applied to other memories or semiconductor devices.

1 is a diagram illustrating a top view of a semiconductor device 100 according to an exemplary embodiment.

1 , the semiconductor device 100 may include a plurality of memory cells. Each memory cell may include an active region 14 , an isolation layer (not shown), a buried gate structure BG, a bit line structure BL, and a memory element 31 . The buried gate structure BG may extend in the first direction X, and the bit line structure BL may extend in the second direction Y. The first direction (X) and the second direction (Y) may cross each other. Each bit line structure BL may include a bit line 18 and a bit line spacer 22 .

Each memory cell may include a lower plug (not shown), an upper plug 29 , a protective spacer 26 , and a capping layer 27 . The upper plug 29 may overlap the bit line structure BL. The protective spacer 26 may have a shape (Surrounding-Shape) surrounding the upper plug 29 . The protective spacer 26 may have a shape surrounding the sidewall of the upper plug 29 . The protective spacer 26 may be in contact with one side of the upper plug 29 . The protective spacer 26 may cover the upper plug 29 . The capping layer 27 may cover the upper plug 29 . The protective spacer 26 and the capping layer 27 may not overlap the upper plug 29 . The top view of the upper plug 29 may include various shapes, such as a square, a circle, an oval.

2A to 2C are views illustrating a semiconductor device 100 according to an exemplary embodiment. FIG. 2A is a cross-sectional view taken along line AA′ of FIG. 1 . FIG. 2B is a perspective view for explaining FIG. 2A. FIG. 2C is a cross-sectional view taken along line B-B' of FIG. 1 . In FIGS. 2A to 2C , the same reference numerals as in FIG. 1 denote the same components. Hereinafter, detailed descriptions of overlapping components will be omitted.

As shown in FIG. 2A , the device isolation layer 13 may be formed on the substrate 11 . The device isolation layer 13 may be located in the isolation trench 12 . The active region 14 may be defined by the device isolation layer 13 .

The substrate 11 may be a material suitable for semiconductor processing. The substrate 11 may include a semiconductor substrate. The substrate 11 may be made of a material containing silicon. The substrate 11 may include silicon, single crystal silicon, polysilicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon doped silicon, a combination thereof, or a multilayer thereof. The substrate 11 may include other semiconductor materials such as germanium. The substrate 11 may include a III-V semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The substrate 11 may include a silicon on insulator (SOI) substrate.

The device isolation layer 13 may be a shallow trench isolation region (STI) formed by trench etching. The device isolation layer 13 may be formed by filling an insulating material in a shallow trench, for example, the isolation trench 12 . The device isolation layer 13 may include silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or other deposition process may be used to fill isolation trench 12 with an insulating material. A planarization process such as chemical-mechanical polishing (CMP) may additionally be used.

A source/drain region SD may be positioned in the active region 14 . A doping process may be performed to form the source/drain regions SD. The doping process may include a process such as implantation or plasma doping (PLAD). The source/drain regions SD may be doped with conductive impurities. For example, the conductive impurities may include phosphorus (P), arsenic (As), antimony (Sb), or boron (B). A lower surface of the source/drain region SD may be located at a predetermined depth from a top surface of the active region 14 . The source/drain region SD may correspond to the source region and the drain region. The source/drain regions SD may have the same depth. The source/drain region SD may be a region to which the bit line contact plug 16 or the storage node contact plug SNC is to be connected.

An interlayer insulating layer 15 may be positioned on the substrate 11 . The interlayer insulating layer 15 may include an insulating material. The interlayer insulating layer 15 may include silicon oxide, silicon nitride, low-k materials, or a combination thereof. The interlayer insulating layer 15 may include TEOS. The interlayer insulating layer 15 may include one or more layers. The interlayer insulating layer 15 may include one or more layers formed of different materials. In this embodiment, the interlayer insulating layer 15 may include two layers. In this embodiment, the interlayer insulating layer 15 may include a layer formed of silicon oxide and a layer formed of silicon nitride.

A conductive line pattern may be formed on the substrate 11 . The conductive line pattern may include a stacked structure of a conductive layer and a hard mask. The conductive line pattern may include a bit line structure BL. In this embodiment, the semi-conductive device 100 may include a bit line contact plug 16 formed in a substrate and a bit line structure BL formed on the bit line contact plug 16 .

A bit line contact plug 16 may be positioned in the substrate 11 . The level of the upper surface of the bit line contact plug 16 may be higher than the level of the upper surface of the substrate 11 . The level of the upper surface of the bit line contact plug 16 may be the same as the level of the upper surface of the interlayer insulating layer 15 . The bit line contact plug 16 may include a semiconductor material. The bit line contact plug 16 may include a silicon-containing material. The bit line contact plug 16 may include polysilicon. Polysilicon may be doped with impurities. In another embodiment, the bit line contact plug 16 may be formed by selective epitaxial growth (SEG). For example, the bit line contact plug 16 may include SEG Silicon Phosphorus (SiP). In this way, the void-free bit line contact plug 16 can be formed by selective epitaxial growth.

A bit line structure BL may be positioned on the bit line contact plug 16 . The bit line structure BL may include a barrier metal layer 17 , a bit line 18 , and a bit line hard mask 19 . The width of the barrier metal layer 17 , the bit line 18 , and the bit line hard mask 19 may be the same. The width of the bit line contact plug 16 may be the same as the width of the bit line structure BL. The bit line structure BL may extend in a line shape.

A barrier metal layer 17 may be positioned on the bit line contact plug 16 . The barrier metal layer 17 may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. In this embodiment, the barrier metal layer 17 may include a material containing titanium nitride (TiN).

A bit line 18 may be positioned on the barrier metal layer 17 . The bit line 18 may include a material having a specific resistance lower than that of the bit line contact plug 16 . The bit line 18 may include a metal material having a specific resistance lower than that of the bit line contact plug 16 . The bit line 18 may include a metal, a metal nitride, a metal silicide, or a combination thereof. The bit line 18 may include a tungsten-containing material. The bit line 18 may be formed by stacking tungsten silicide, a tungsten nitride film, and a tungsten film. In this embodiment, the bit line 18 may include tungsten (W) or a tungsten compound.

A bit line hard mask 19 may be positioned on the bit line 18 . The bit line hard mask 19 may include an insulating material. The bit line hard mask 19 may include a material having an etch selectivity with respect to the bit line 18 . The bit line hard mask 19 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In this embodiment, the bit line hard mask 19 may be formed of silicon nitride.

The bit line spacers 22 may be positioned on both side walls of the bit line contact plug 16 and on both side walls of the bit line structure BL. The bit line spacer 22 may be independently formed on both sides of the bit line contact plug 16 . The bit line spacer 22 may extend in a line shape. The upper surface of the bit line spacer 22 may be at the same level as the upper surface of the bit line structure BL. The bit line spacer 22 may include an insulating material. The bit line spacer 22 may include a low-k material. The bit line spacer 22 may include oxide or nitride. The bit line spacer 22 may include silicon oxide, silicon nitride, or metal oxide. The bit line spacer 22 may include SiO ₂ , Si ₃ N ₄ , or SiN. The bit line spacer 22 may include a multi-layer spacer. The bit line spacer 22 may include an air gap (not shown). Accordingly, a pair of line-type air gaps may be formed on both sidewalls of the bit line spacer 22 . The pair of line-shaped air gaps may be symmetrical. In some embodiments, the multilayer spacer may include a first spacer, a second spacer, and a third spacer, and a third spacer may be positioned between the first spacer and the second spacer. The multilayer spacer may include a NON structure in which oxide spacers are positioned between nitride spacers. In another embodiment, the multilayer spacer may include a first spacer, a second spacer, and an air gap between the first spacer and the second spacer.

A lower plug 24 partially covering an upper surface of the bit line structure BL may be positioned between the bit line structures BL. The lower plug 24 may include a pillar part 24M and an extension part 24T. The pillar part 24M may be positioned between the bit line structures BL. The extension part 24T may extend from the pillar part 24M to overlap any one of the bit line structures BL. The extension 24T may partially overlap any one of the bit line structures BL. The bit line structure BL may be a concept included in the conductive line pattern. The upper surface of the lower plug 24 may be positioned at a higher level than the upper surface of the bit line structure BL. The upper surface of the extension part 24T may be positioned at a higher level than the upper surface of the bit line structure BL. The bit line spacer 22 may be positioned between the pillar part 24M and the bit line structure BL. The bit line spacer 22 may be positioned between the pillar part 24M and the bit line contact plug 16 . The bottom surface of the pillar part 24M may be located at a level lower than the top surface of the substrate 11 . A bottom surface of the pillar part 24M may be connected to the source/drain region SD. A lower portion of the pillar part 24M may be extended in a lateral direction to have a bulb type. A top-view of the pillar part 24M may include a quadrangle, a circle, or an oval.

The pillar part 24M and the extension part 24T may include the same material. The pillar part 24M and the extension part 24T may include a silicon-containing material. The pillar portion 24M and the extension portion 24T may be doped with impurities. For example, impurities may be doped by a doping process such as implantation. In this embodiment, the pillar part 24M and the extension part 24T may include polysilicon.

An ohmic contact layer 28 may be positioned on the lower plug 24 . Deposition and annealing of a silicidable metal layer may be performed to form the ohmic contact layer 28 . The ohmic contact layer 28 may include metal silicide. The ohmic contact layer 28 may include cobalt silicide (CoSi _x ). In the present embodiment, the ohmic contact layer 28 may include cobalt silicide in the 'CoSi ₂ phase'. Accordingly, it is possible to form cobalt silicide of low resistance while improving the contact resistance.

An upper plug 29 may be positioned on the ohmic contact layer 28 . The thickness of the upper plug 29 may be smaller than the thickness of the lower plug 24 . The thickness of the upper plug 29 may be smaller than the thickness of the extension 24T of the lower plug. The upper plug 29 may include a material different from that of the lower plug 24 . The upper plug 29 may include a metal-containing material. The upper plug 29 may include a conductive material. The upper plug 29 may include a metal-containing material. The upper plug 29 is gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), titanium (Ti), platinum (Pt), palladium (Pd) , tin (Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr), and may include any one or more of molybdenum (Mo). In this embodiment, the upper plug 29 may include a tungsten (W)-containing material. The upper plug 29 may include tungsten (W). The upper plug 29 may be formed by a chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) method. The upper plug 29 may use plasma to increase the deposition effect. That is, the upper plug 29 may be formed by a method such as plasma enhanced CVD (PECVD) or plasma enhanced ALD (PEALD). In this embodiment, the upper plug 29 may be formed by chemical vapor deposition (CVD).

A capping hole 25 may be positioned between the lower plugs 24 . The bottom surface of the capping hole 25 may be positioned on the lower plug 24 , the bit line spacer 22 , and the bit line hard mask 19 . The bottom surface of the capping hole 25 may be located at a higher level than the bottom surface of the bit line hard mask 19 . The bottom surface of the capping hole 25 may be located at a level lower than the top surface of the bit line hard mask 19 .

A capping layer 27 may be positioned between the lower plugs 24 . The capping layer 27 may cover a sidewall of the lower plug 24 . The capping layer 27 may cover a sidewall of the upper plug 29 . The capping layer 27 may fill the capping hole 25 . The upper surface of the capping layer 27 may be at the same level as the upper surface of the upper plug 29 . The upper surface of the capping layer 27 may be at a higher level than the upper surface of the lower plug 24 . The capping layer 27 may not overlap the upper plug 29 . The capping layer 27 may partially overlap the pillar part 24M of the lower plug 24 . The upper surface of the capping layer 27 may be at a higher level than the upper surface of the extension 24T. A portion of the capping layer 27 may be in contact with the substrate 11 . The capping layer 27 may include an insulating material. The capping layer 27 may include a nitrogen-containing material. The capping layer 27 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In this embodiment, the capping layer 27 may be formed of silicon nitride. The capping layer 27 may be formed by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method. The capping layer 27 may be selectively grown by an atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD) process using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) as reactive gases.

A protective spacer 26 may be positioned between the capping layer 27 and the lower plug 24 . The protective spacer 26 may include a Surronding-Shape surrounding the lower plug 24 . The protective spacer 26 may fully-cover the sidewall of the extension part 24T. The protective spacer 26 may partially cover the sidewall of the pillar part 24M. The protective spacer 26 may cover the sidewall of the upper plug 29 . The protective spacer 26 may include a shape surrounding the upper plug 29 . The protective spacer 26 may cover a sidewall of the ohmic contact layer 28 . The capping layer 27 may cover a sidewall of the protective spacer 26 . The upper surface of the protective spacer 26 may be positioned at the same level as the upper surface of the upper plug 29 . Referring to FIG. 1 , a top-view of the protective spacer 26 may include various shapes such as a square, a circle, an oval, and the like with a hole in the middle. In this embodiment, the top view of the protective spacer 26 may include a square ring shape.

The protective spacer 26 may include an insulating material. The protective spacer 26 may include a nitrogen-containing material. The protective spacer 26 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In this embodiment, the protective spacer 26 may include silicon nitride. The protective spacer 26 may be formed by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method. The protective spacer 26 may be selectively grown by an atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD) process using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) as reactive gases.

Referring to FIG. 1 , a narrow etch region E1 and a wide etch region E2 may be formed when the capping hole 25 is formed. The narrow etched area E1 has a narrow open area when the capping hole 25 is formed, so that the plug material may remain. The wide etched region E2 has a large open area when the capping hole 25 is formed, so that the plug material can be easily removed. The protective spacer 26 may adjust the open area of the narrow etched region E1 . The protective spacer 26 further narrows the open area of the narrow etched region E1, thereby preventing the lower lower plug 24 from being removed. Accordingly, poor contact between the lower plug 24 and the adjacent active region 14 can be prevented.

An etch stop layer 30 may be formed on the upper plug 29 . A memory element 31 electrically connected to the upper plug 29 may be formed on the upper plug 29 . The memory element 31 may include a conductive layer. The memory element 31 may be implemented in various forms. The memory element 31 may be a capacitor. Accordingly, the memory element 31 may include a storage node in contact with the upper plug 29 . The storage node may be in the form of a cylinder or a pillar. A capacitor dielectric layer may be formed on the surface of the storage node. The capacitor dielectric layer may include at least one selected from zirconium oxide, aluminum oxide, and hafnium oxide. For example, the capacitor dielectric layer may have a ZAZ structure in which a first zirconium oxide, an aluminum oxide, and a second zirconium oxide are stacked. A plate node is formed on the capacitor dielectric layer. The storage node and the plate node may include a metal-containing material. The memory element 31 may include a variable resistor. The variable resistor may include a phase change material. In another embodiment, the variable resistor may include a transition metal oxide. In another embodiment, the variable resistor may be a magnetic tunnel junction (MTJ).

According to the above-described embodiment, it is possible to reduce process defects by forming the lower plug 24 including the extension part 24T. In addition, it is possible to secure the mass productivity of the semiconductor device by simplifying the process. In addition, the protective spacer 26 may prevent the plug pattern 24B of the narrow etched region E1 from being removed by narrowing the open area of the narrow etched region E1 . Accordingly, poor contact with the adjacent active region 14 can be prevented. In addition, the ohmic contact layer 28 may be easily formed by forming the ohmic contact layer 28 at a level higher than the upper surface of the bit line structure BL. Since the ohmic contact layer 28 having a large area can be formed, contact resistance can be improved. Since the upper plug 29 having a large area can be formed, contact failure of the contact can be improved.

2B is a perspective view for explaining FIG. 2A. FIG. 2B is a view showing the bit line structure BL, the lower plug 24, the ohmic contact layer 28, and the upper plug 29 of FIG. 2A. Other components will be omitted for the sake of description.

Referring to FIG. 2B , the lower plug 24 may partially overlap the bit line structure BL. The upper surface of the lower plug 24 may be positioned at a higher level than the upper surface of the bit line structure BL.

The lower plug 24 may include a pillar part 24M and an extension part 24T. The extension part 24T may extend from the pillar part 24M and continue. The extension 24T may partially overlap the bit line structure BL. The upper surface of the extension part 24T may be positioned at a higher level than the upper surface of the bit line structure BL. The extension part 24T may include a quadrangular prism shape.

The pillar part 24M may include a pillar-shape. The pillar part 24M may be thicker as it goes down. The bit line spacer 22 may be positioned between the pillar part 24M and the bit line hard mask 19 . A bit line spacer 22 may be positioned between the pillar part 24M and the bit line 18 . A lower portion of the pillar part 24M may be extended in a lateral direction to have a bulb type.

The pillar part 24M and the extension part 24T may include the same material. The pillar part 24M and the extension part 24T may include a silicon-containing material. The pillar portion 24M and the extension portion 24T may be doped with impurities. In this embodiment, the pillar part 24M and the extension part 24T may include polysilicon.

An ohmic contact layer 28 may be positioned on the lower plug 24 . An upper plug 29 may be positioned on the ohmic contact layer 28 . The width of the extension 25T, the ohmic contact layer 28 and the upper plug 29 may be the same.

According to the above-described embodiment, by forming the upper surface of the lower plug 24 at a level higher than the upper surface of the bit line structure BL, the process can be simplified and process defects can be improved.

FIG. 2C is a cross-sectional view taken along line B-B' of FIG. 1 .

Referring to FIG. 2C , a buried gate structure BG may be positioned in the substrate 11 . The buried gate structure BG includes a buried gate trench 50 , a buried gate insulating layer 51 covering the bottom surface and sidewalls of the buried gate trench 50 , and a buried gate trench 50 on the buried gate insulating layer 51 . It may include a buried word line 52 partially filling the ? and a buried gate capping layer 53 formed on the buried word line 52 .

The buried gate trench 50 may have a line shape crossing the active region 14 and the device isolation layer 13 . The buried gate trench 50 may have a sufficient depth to increase the average cross-sectional area of a subsequent buried word line. Accordingly, the resistance of the buried word line can be reduced. Although not shown, a portion of the device isolation layer 13 may be recessed to protrude the upper portion of the active region 14 under the buried gate trench 50 . For example, the device isolation layer 13 under the buried gate trench 50 may be selectively recessed. Accordingly, a fin region (reference numeral omitted) may be formed under the buried gate trench 50 . The fin region may be a part of the channel region.

A buried gate insulating layer 51 may be positioned on the bottom surface and sidewalls of the buried gate trench 50 . The buried gate insulating layer 51 may be formed by a thermal oxidation process. In another embodiment, the buried gate insulating layer 51 may be formed by a deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The buried gate insulating layer 51 may include a high-k material, oxide, nitride, oxynitride, or a combination thereof. The buried gate insulating layer 51 may be formed by depositing a liner polysilicon layer and then radically oxidizing the liner polysilicon layer. The buried gate insulating layer 51 may be formed by radical oxidation of the liner silicon nitride layer after forming the liner silicon nitride layer.

A buried word line 52 may be positioned on the buried gate insulating layer 51 . To form the buried word line 52 , a recessing process may be performed after a conductive layer (not shown) is formed to fill the buried gate trench 50 . The recessing process may be performed as an etchback process, or a chemical mechanical polishing (CMP) process and an etchback process may be sequentially performed. The buried word line 52 may include a recessed shape partially filling the buried gate trench 50 . That is, the upper surface of the buried word line 52 may be at a lower level than the upper surface of the active region 14 . The buried word line 52 may include a metal, a metal nitride, or a combination thereof. For example, the buried word line 52 may be formed of titanium nitride (TiN), tungsten (W), or titanium nitride/tungsten (TiN/W).

A buried gate capping layer 53 may be positioned on the buried word line 52 . The upper surface of the buried gate capping layer 53 may be at the same level as the upper surface of the interlayer insulating layer 15 . The buried gate capping layer 53 includes an insulating material. The buried gate capping layer 53 may include silicon nitride. The buried gate capping layer 53 may include silicon oxide. The buried gate capping layer 53 may have a nitride-oxide-nitride (NON) structure.

A bit line contact hole 16H may be positioned between the buried gate capping layers 53 . The buried gate capping layer 53 and the device isolation layer 13 under the bit line contact hole 16H may be recessed to a predetermined depth.

The bit line contact plug 16 may fill the bit line contact hole 16H. The upper surface of the bit line contact plug 16 may be at the same level as the upper surface of the interlayer insulating layer 15 . A bit line structure BL may be positioned on the bit line contact plug 16 and the interlayer insulating layer 15 . The bit line structure BL may include a barrier metal layer 17 , a bit line 18 , and a bit line hard mask 19 . An etch stop layer 30 may be formed on the bit line structure BL.

3A to 3O are diagrams illustrating a method of manufacturing the semiconductor device 100 according to an exemplary embodiment. 4A to 4G are diagrams illustrating a method of manufacturing the semiconductor device 100 according to an exemplary embodiment. 4A to 4G are perspective views for explaining FIGS. 3H to 3N. In FIGS. 3A to 3O, the same reference numerals as in FIGS. 2A to 2C denote the same components. In Figs. 4A to 3G, the same reference numerals as in Figs. 3A to 3O denote the same components.

As shown in FIG. 3A , the substrate 11 is prepared. The substrate 11 may include a semiconductor substrate. The substrate 11 may be made of a material containing silicon. The substrate 11 may include silicon, single crystal silicon, polysilicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon doped silicon, a combination thereof, or a multilayer thereof. The substrate 11 may include a III-V group semiconductor substrate. For example, the substrate 11 may include a compound semiconductor substrate such as GaAs.

A device isolation layer 13 and an active region 14 may be formed on the substrate 11 . The active region 14 may be defined by the device isolation layer 13 . The device isolation layer 13 may include an STI region formed by trench etching. The device isolation layer 13 may be formed by filling the isolation trench 12 with an insulating material. The device isolation layer 13 may include silicon oxide, silicon nitride, or a combination thereof. A planarization process may be additionally performed.

A source/drain region SD may be formed in the active region 14 . Conductive impurities may be doped to form the source/drain regions SD. The conductive impurities may include phosphorus (P), arsenic (As), antimony (Sb), or boron (B). A lower surface of the source/drain region SD may be located at a predetermined depth from a top surface of the active region 14 . The source/drain region SD may be a region to which a bit line contact plug or a storage node contact plug is to be connected.

An interlayer insulating layer 15 may be formed on the substrate 11 . The interlayer insulating layer 15 may include an insulating material. The interlayer insulating layer 15 may include one or more layers. The interlayer insulating layer 15 may include one or more layers formed of different materials. In this embodiment, the interlayer insulating layer 15 may include a layer formed of silicon oxide and a layer formed of silicon nitride.

Although not shown, the buried gate structure BG of FIG. 2C is formed in the substrate. The buried gate structure BG includes a buried gate trench 50 , a buried gate insulating layer 51 covering the bottom surface and sidewalls of the buried gate trench 50 , and a buried gate trench 50 on the buried gate insulating layer 51 . It may include a buried word line 52 partially filling the ? and a buried gate capping layer 53 formed on the buried word line 52 .

Subsequently, the interlayer insulating layer 15 and the substrate 11 may be etched to form a bit line contact hole 16H. When viewed from a top view, the bit line contact hole 16H may have a circular shape or an oval shape. The bit line contact hole 16H may be formed through the interlayer insulating layer 15 . A portion of the substrate 11 may be exposed through the bit line contact hole 16H. The method may further include recessing the exposed surface of the substrate 11 . When the interlayer insulating layer 15 is etched to form the bit line contact hole 16H, a portion of the substrate 11 may be etched together. Accordingly, a portion of the substrate 11 may be exposed through the bit line contact hole 16H. The lower surface of the bit line contact hole 16H may be located at a level lower than the upper surface of the substrate 11 .

As shown in FIG. 3B , a spare bit line contact plug 16A may be formed in the bit line contact hole 16H. The spare bit line contact plug 16A may fill the bit line contact hole 16H. After the bit line contact material 16A' is formed to form the preliminary bit line contact plug 16A, a planarization process may be performed. The planarization process may include a CMP process. Accordingly, the upper surface of the spare bit line contact plug 16A may be at the same level as the upper surface of the interlayer insulating layer 15 . The spare bit line contact plug 16A may pass through the interlayer insulating layer 15 to contact a portion of the substrate 11 .

The spare bit line contact plug 16A may include a semiconductor material. The spare bit line contact plug 16A may include a conductive material. The spare bit line contact plug 16A may include a silicon-containing material. The spare bit line contact plug 16A may include polysilicon. Polysilicon may be doped with impurities. In another embodiment, the spare bit line contact plug 16A may be formed by selective epitaxial growth (SEG). For example, the spare bit line contact plug 16A may include SEG Silicon Phosphorus (SiP). In this way, the void-free preliminary bit line contact plug 16A can be formed by selective epitaxial growth.

As shown in FIG. 3C , a preliminary barrier metal layer 17A may be formed on the interlayer insulating layer 15 and the preliminary bit line contact plug 16A. The height of the preliminary barrier metal layer 17A may be smaller than the height of the interlayer insulating layer 15 . The preliminary barrier metal layer 17A may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. In this embodiment, the preliminary barrier metal layer 17A may include a material containing titanium nitride (TiN).

A preliminary bit line 18A may be formed on the preliminary barrier metal layer 17A. The spare bit line 18A may be formed of a material having a specific resistance lower than that of the spare bit line contact plug 16A. The spare bit line 18A may include a metal material having a specific resistance lower than that of the spare bit line contact plug 16A. The spare bit line 18A may include a metal, a metal nitride, a metal silicide, or a combination thereof. The preliminary bit line 18A may include a tungsten-containing material. The preliminary bit line 18A may be formed by stacking tungsten silicide, a tungsten nitride film, and a tungsten film. In this embodiment, the spare bit line 18A may include tungsten (W) or a tungsten compound.

A spare bit line hard mask 19A may be formed on the spare bit line 18A. The preliminary bit line hard mask 19A may be formed of an insulating material. The preliminary bit line hard mask 19A may be formed of a material having an etch selectivity with respect to the preliminary bit line 18A. The preliminary bit line hard mask 19A may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In this embodiment, the spare bit line hard mask 19A may be formed of silicon nitride.

A bit line mask 20 may be formed on the spare bit line hard mask 19A. The bit line mask 20 may include a photoresist pattern. The bit line mask 20 may include a line shape extending in any one direction. The line width of the bit line mask 20 may be smaller than the diameter of the upper surface of the spare bit line contact plug 16A.

As shown in FIG. 3D , a bit line structure BL may be formed. The bit line structure BL may include a barrier metal layer 17 , a bit line 18 , and a bit line hard mask 19 . The bit line structure BL may extend in a line shape.

The preliminary bit line hard mask 19A may be etched using the bit line mask 20 as an etch mask. Accordingly, the bit line hard mask 19 may be formed. The spare bit line 18A, the spare barrier metal layer 17A, and the spare bit line contact plug 16A may be etched using the bit line hard mask 19 as an etch mask. Accordingly, the bit line 18 , the barrier metal layer 17 , and the bit line contact plug 16 may be formed. Line widths of the bit line contact plug 16 , the barrier metal layer 17 , the bit line 18 , and the bit line hard mask 19 may be the same. The bit line 18 may extend in either direction while covering the barrier metal layer 17 .

As the spare bit line contact plug 16A is etched, the bit line contact plug 16 may be formed on the source/drain region SD. The bit line contact plug 16 may interconnect the source/drain region SD and the bit line 18 . The diameter of the bit line contact plug 16 may be smaller than the diameter of the spare bit line contact plug 16A. A gap 21 may be formed in a space in which a portion of the spare bit line contact plug 16A is removed. A gap 21 may be formed on both sidewalls of the bit line contact plug 16 . The gap 21 may be independently formed on both sidewalls of the bit line contact plug 16 . The pair of gaps 21 may be separated by a bit line contact plug 16 .

As shown in FIG. 3E , bit line spacers 22 may be formed on both side walls of the bit line contact plug 16 and on both side walls of the bit line structure BL. The bit line spacer 22 may have a pillar shape filling the gap 21 . By the bit line spacer 22, it is possible to prevent any material from being filled in the gap 21 in a subsequent process. The bit line spacer 22 may be independently formed on both sides of the bit line contact plug 16 . The bit line spacer 22 may extend in a line shape. The upper surface of the bit line spacer 22 may be at the same level as the upper surface of the bit line structure BL.

The bit line spacer 22 may include an insulating material. The bit line spacer 22 may include a low-k material. The bit line spacer 22 may include oxide or nitride. The bit line spacer 22 may include silicon oxide, silicon nitride, or metal oxide. The bit line spacer 22 may include SiO ₂ , Si ₃ N ₄ , or SiN. The bit line spacer 22 may include a multi-layer spacer. The bit line spacer 22 may include an air gap (not shown). Accordingly, a pair of line-type air gaps may be formed on both sidewalls of the bit line spacer 22 . The pair of line-shaped air gaps may be symmetrical. In some embodiments, the multilayer spacer may include a first spacer, a second spacer, and a third spacer, and a third spacer may be positioned between the first spacer and the second spacer. The multilayer spacer may include a NON structure in which oxide spacers are positioned between nitride spacers. In another embodiment, the multilayer spacer may include a first spacer, a second spacer, and an air gap between the first spacer and the second spacer.

In another embodiment, the gap 21 may be filled with a bit line contact insulating layer (not shown) other than the bit line spacers 22 . The upper surface of the bit line contact insulating layer (not shown) may be at the same level as the upper surface of the bit line contact plug 16 . A bit line spacer 22 may be formed on the bit line contact insulating layer (not shown). The bit line contact insulating layer (not shown) may include an insulating material. The bit line contact insulating layer (not shown) may include oxide or nitride. The bit line contact insulating layer (not shown) may include silicon oxide, silicon nitride, or metal oxide.

As shown in FIG. 3F , a bit line interlayer insulating layer (not shown) may be formed to fill between the bit line structures BL. The bit line interlayer insulating layer (not shown) may be planarized to expose an upper portion of the bit line structure BL. The bit line interlayer insulating layer (not shown) may extend parallel to the bit line structure BL. The bit line interlayer insulating layer (not shown) may be formed of a material having an etch selectivity with respect to the bit line spacer 22 . The bit line interlayer insulating layer (not shown) may include an insulating material. The bit line interlayer insulating layer (not shown) may include oxide or nitride. The bit line interlayer insulating layer (not shown) may include silicon oxide, silicon nitride, or metal oxide. The bit line interlayer insulating layer (not shown) may include SiO ₂ , Si ₃ N ₄ , or SiN. The bit line interlayer insulating layer (not shown) may include a spin-on insulating material (SOD).

Subsequently, a storage node contact hole 23 may be formed in the bit line interlayer insulating layer (not shown). The storage node contact hole 23 may be formed by etching the bit line interlayer insulating layer (not shown) using a storage node contact opening mask (not shown) as an etch mask. The storage node contact opening mask (not shown) may include a photoresist pattern.

The storage node contact hole 23 may be formed between the bit line structures BL. A bottom surface of the storage node contact hole 23 may extend into the substrate 11 . While the storage node contact hole 23 is formed, the device isolation layer 13 , the interlayer insulating layer 15 , and the source/drain regions SD may be recessed to a predetermined depth. A portion of the substrate 11 may be exposed through the storage node contact hole 23 . The bottom surface of the storage node contact hole 23 may be located at a level lower than the top surface of the substrate 11 . The bottom surface of the storage node contact hole 23 may be at a higher level than the bottom surface of the bit line contact plug 16 . The bottom surface of the storage node contact hole 23 may be at the same level as the bottom surface of the bit line contact plug 16 . A dip-out and trimming process may be performed to form the storage node contact hole 23 . The storage node contact hole 23 may be formed without loss of the bit line spacer 22 by the deep-out. The side and lower areas of the storage node contact hole 23 may be expanded by the trimming process. A portion of the interlayer insulating layer 15 and the substrate 11 may be removed by the trimming process. The interlayer insulating layer 15 may be etched by dry etching. In this embodiment, the interlayer insulating layer 15 may be etched by isotropic etching. The source/drain regions SD may be exposed through the storage node contact hole 23 . A lower portion of the storage node contact hole 23 may extend in a lateral direction to have a bulb type.

As shown in FIG. 3G , a plug material 24A may be formed in the storage node contact hole 23 . The plug material 24A may cover the upper surface of the bit line structure BL while filling the storage node contact hole 23 . The plug material 24A may cover the upper surface of the bit line hardmask 19 . The plug material 24A may overlap the bit line structure BL. The plug material 24A may partially overlap the bit line structure BL. The upper surface of the plug material 24A may be positioned at a higher level than the upper surface of the bit line hard mask 19 . A bit line spacer 22 may be positioned between the bit line 18 and the plug material 24A. A bit line spacer 22 may be positioned between the bit line contact plug 16 and the plug material 24A. A bottom surface of the plug material 24A may be connected to the source/drain region SD.

The plug material 24A may include a silicon-containing material. The plug material 24A may be doped with impurities. For example, impurities may be doped by a doping process such as implantation. In this embodiment, the plug material 24A may include polysilicon.

3H and 4A , a gap fill mask 25M may be formed on the plug material 24A. The gap fill mask 25M may include a photoresist pattern. The plug material 24A may be etched using the gap fill mask 25M as an etch mask. The plug pattern 24B may be formed by etching the plug material 24A. By forming the plug pattern 24B, the plug material 24A may be separated from each other. The plug pattern 24B is positioned between the bit line structures BL, and may overlap any one of the bit line structures BL. The plug pattern 24B may partially overlap any one of the plurality of bit line structures BL. The plug pattern 24B may overlap the upper surface of the bit line hard mask 19 . A top-view of the plug pattern 24B may include various shapes such as a square, a circle, an oval, and the like. The bit line structure BL may be an example of a conductive line pattern.

A preliminary capping hole 25A may be formed between the separated plug patterns 24B. When forming the plug pattern 24B, a portion of the bit line hard mask 19 and the bit line spacer 22 may be etched together. Accordingly, a portion of the bit line hard mask 19 and the bit line spacer 22 may be exposed by the preliminary capping hole 25A. The top surface of the plug pattern 24B may be at a higher level than the bottom surface of the preliminary capping hole 25A. The upper surface of the plug pattern 24B may be at a higher level than the upper surface of the bit line hard mask 19 . The lower surface of the preliminary capping hole 25A may be at a level lower than the upper surface of the bit line hard mask 19 , and may be located at a higher level than the lower surface of the bit line hard mask 19 .

3I and 4B , a protective spacer 26 may be formed on a sidewall of the plug pattern 24B. After forming a preliminary protective spacer (not shown) to form the protective spacer 26 , an etching process or an etchback process may be performed. The protective spacer 26 may cover a sidewall of the plug pattern 24B. The protective spacer 26 may include a Surrounding-Shape surrounding the plug pattern 24B. The top view of the protective spacer 26 may include various shapes such as a square ring shape or a ring shape.

The protective spacer 26 may include an insulating material. The protective spacer 26 may be a non-oxide base materail. The protective spacer 26 may be a nitride base material. The protective spacer 26 may include a nitrogen-containing material. The protective spacer 26 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In this embodiment, the protective spacer 26 may include silicon nitride. The protective spacer 26 may be formed by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method. The protective spacer 26 may be selectively grown by an atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD) process using dichlorosilane (SiH2Cl2) and ammonia (NH3) as reactive gases.

The protective spacer 26 may reduce the area of the plug pattern 24B exposed by the preliminary capping hole 25A. Accordingly, it is possible to prevent the loss of the plug pattern 24B in the subsequent process, and to prevent a contact defect with the neighboring active region 14 .

3J and 4C , the preliminary capping hole 25A may be additionally recessed. The recessing process may be performed as an etchback process, or a chemical mechanical polishing (CMP) process and an etchback process may be sequentially performed. Accordingly, the capping hole 25 may be formed. The plug pattern 24B in the capping hole 25 may be removed. The bit line hard mask 19 and the bit line spacer 22 in the capping hole 25 may be removed.

A portion of the plug pattern 24B may be exposed by the capping hole 25 . A portion of the bit line hard mask 19 and the bit line spacer 22 may be exposed by the capping hole 25 . The lower surface of the capping hole 25 may be located at a level lower than the upper surface of the bit line hard mask 19 , and may be located at a higher level than the lower surface of the bit line hard mask 19 .

Referring to FIG. 1 , a narrow etch region E1 and a wide etch region E2 may be formed when the capping hole 25 is formed. When the capping hole 25 is formed, the plug pattern 24B of the narrow etched region E1 has a narrow open area and may remain. When the capping hole 25 is formed, the plug pattern 24B of the wide etched area E2 has a large open area and thus can be removed. The protective spacer 26 may adjust the open area of the narrow etched region E1 . The protective spacer 26 may further narrow the open area of the narrow etched region E1 to prevent the plug pattern 24B of the narrow etched region E1 from being removed. Accordingly, poor contact with the adjacent active region 14 can be prevented.

3K and 4D , a capping layer 27 may be formed between the plug patterns 24B. The capping layer 27 may fill the capping hole 25 . In order to form the capping layer 27 , a preliminary capping layer 27A covering the plug pattern 24B may be formed. A process of planarizing the pre-capping layer 27A to expose the top surface of the plug pattern 24B may be included. Accordingly, the upper surface of the plug pattern 24B may be exposed. The upper surface of the capping layer 27 may be at the same level as the upper surface of the plug pattern 24B. A protective spacer 26 may be positioned between the capping layer 27 and the plug pattern 24B. A portion of the capping layer 27 may be in contact with the substrate 11 .

The capping layer 27 may include an insulating material. The capping layer 27 may include silicon oxide, silicon nitride, low-k materials, or a combination thereof. The capping layer 27 may include a nitrogen-containing material. The capping layer 27 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In this embodiment, the capping layer 27 may be formed of silicon nitride. The capping layer 27 may be formed by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method. The capping layer 27 may be selectively grown by an atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD) process using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) as reactive gases.

3L and 4E , the plug pattern 24B may be recessed to a predetermined depth. The recessing process may be performed as an etchback process, or a chemical mechanical polishing (CMP) process and an etchback process may be sequentially performed. As the plug pattern 24B is recessed, the lower plug 24 may be formed. The lower plug 24 may have the same shape as the lower plug 24 of FIG. 2B . As the lower plug 24 is formed, a plug opening 27H may be formed. As the lower plug 24 is formed, a portion of the sidewall of the protective spacer 26 may be exposed. The lower plug 24 may be referred to as a recessed plug pattern 24B.

The lower plug 24 may include a pillar part 24M and an extension part 24T. The pillar part 24M may be positioned between the bit line structures BL. The extension part 24T may extend from the pillar part 24M to overlap any one of the bit line structures BL. The upper surface of the lower plug 24 may be located at a higher level than the upper surface of the bit line hard mask 19 . The upper surface of the lower plug 24 may be located at a level lower than the upper surface of the capping layer 27 . The top view of the extension part 24T may include various shapes such as a square, a circle, an oval, and the like. The pillar part 24M may include a pillar-shape. The pillar part 24M may be in contact with the substrate.

The upper surface of the lower plug 24 may be exposed by the plug opening 27H. A portion of the protective spacer 26 may be exposed by the plug opening 27H. The protective spacer 26 may include a shape surrounding the sidewall of the lower plug 24 . The protective spacer 26 may fully-cover the sidewall of the extension part 24T. The protective spacer 26 may partially cover the sidewall of the pillar part 24M.

Process defects can be reduced by etching the plug material 24A to form the lower plug 24 including the extension part 24T and the pillar part 24M. In addition, it is possible to secure the mass productivity of the semiconductor device by simplifying the process.

As shown in FIGS. 3M and 4F , an ohmic contact layer 28 may be formed on the lower plug 24 . The ohmic contact layer 28 may be formed in the plug opening 27H. The thickness of the ohmic contact layer 28 may be smaller than the thickness of the extension part 24T.

Deposition and annealing of a silicidable metal layer may be performed to form the ohmic contact layer 28 . The ohmic contact layer 28 may include metal silicide. The ohmic contact layer 28 may include cobalt silicide (CoSi _x ). In the present embodiment, the ohmic contact layer 28 may include cobalt silicide in the 'CoSi ₂ phase'. Accordingly, it is possible to form cobalt silicide of low resistance while improving the contact resistance.

Since the ohmic contact layer 28 is formed at a level higher than the upper surface of the bit line structure BL, the ohmic contact layer 28 may be easily formed. In addition, since the ohmic contact layer 28 having a large area can be formed, contact resistance can be improved.

3N and 4G , an upper plug 29 may be formed on the ohmic contact layer 28 . A preliminary upper plug 29A covering the ohmic contact layer 28 may be formed to form the upper plug 29 . A process of planarizing the preliminary upper plug 29A so that the upper surface of the capping layer 27 is exposed may be included. Accordingly, the upper surface of the capping layer 27 may be exposed. The upper surface of the upper plug 29 may be at the same level as the upper surface of the capping layer 27 .

The upper plug 29 may fill the plug opening 27H. The upper plug 29 may partially overlap the bit line structure BL. A protective spacer 26 may be positioned between the upper plug 29 and the capping layer 27 . The upper plug 29 may have a shape in which the protective spacer 26 surrounds it. A protective spacer 26 may cover the upper plug 29 . A capping layer 27 may cover the upper plug 29 . The bottom surface of the upper plug 29 may be at a higher level than the top surface of the bit line hard mask 19 . The upper plug 29, the ohmic contact layer 28, and the extension 24T of the lower plug may have the same width. The thickness of the upper plug 29 may be smaller than the thickness of the extension 24T of the lower plug. The thickness of the upper plug 29 may be greater than the thickness of the ohmic contact layer 28 . The top view of the upper plug 29 may include various shapes, such as a square, a circle, an oval. In this embodiment, the top view of the upper plug 29 may include a rectangular shape.

The upper plug 29 may include a material different from that of the lower plug 24 . The upper plug 29 may include a metal-containing material. The upper plug 29 may include a conductive material. The upper plug 29 may include a metal. The upper plug 29 is gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), titanium (Ti), platinum (Pt), palladium (Pd) , tin (Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr), and may include any one or more of molybdenum (Mo). The upper plug 29 may include a tungsten (W)-containing material. In this embodiment, the upper plug 29 may include tungsten (W) or a tungsten compound.

The upper plug 29 may be formed by a chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) method. The upper plug 29 may use plasma to increase the deposition effect. That is, the upper plug 29 may be formed by a method such as plasma enhanced CVD (PECVD) or plasma enhanced ALD (PEALD). In this embodiment, the upper plug 29 may be formed by chemical vapor deposition (CVD).

Since the upper plug 29 is formed on the ohmic contact layer 28 , the upper plug 29 having a large area can be formed. Accordingly, the contact defect of the contact can be improved.

As shown in FIG. 3O , an etch stop layer 30 may be formed on the upper plug 29 and the capping layer 27 . A memory element 31 electrically connected to the upper plug 29 may be formed on the upper plug 29 . The memory element 31 may include a conductive layer. The memory element 31 may be implemented in various forms. The memory element 31 may be a capacitor. Accordingly, the memory element 31 may include a storage node in contact with the top plug 29 . The storage node may be in the form of a cylinder or a pillar. A capacitor dielectric layer may be formed on the surface of the storage node. The capacitor dielectric layer may include at least one selected from zirconium oxide, aluminum oxide, and hafnium oxide. For example, the capacitor dielectric layer may have a ZAZ structure in which a first zirconium oxide, an aluminum oxide, and a second zirconium oxide are stacked. A plate node is formed on the capacitor dielectric layer. The storage node and the plate node may include a metal-containing material. The memory element 31 may include a variable resistor. The variable resistor may include a phase change material. In another embodiment, the variable resistor may include a transition metal oxide. In another embodiment, the variable resistor may be a magnetic tunnel junction.

According to the above-described embodiment, it is possible to reduce process defects by forming the lower plug 24 including the extension part 24T. In addition, it is possible to secure the mass productivity of the semiconductor device by simplifying the process. In addition, the protective spacer 26 may prevent the plug pattern 24B of the narrow etched region E1 from being removed by narrowing the open area of the narrow etched region E1 . Accordingly, poor contact with the adjacent active region 14 can be prevented. In addition, the ohmic contact layer 28 may be easily formed by forming the ohmic contact layer 28 at a level higher than the upper surface of the bit line structure BL. Since the ohmic contact layer 28 having a large area can be formed, contact resistance can be improved. Since the upper plug 29 having a large area can be formed, contact failure of the contact can be improved.

5 is a diagram illustrating a semiconductor device 200 according to an exemplary embodiment. 5 is a diagram illustrating a top view of the semiconductor device 200 according to an exemplary embodiment.

The semiconductor device 200 may include a memory cell region CELL and a peripheral circuit region PERI.

The memory cell region CELL may include a plurality of memory cells. Each memory cell may include a memory cell active region 104C, an isolation layer (not shown), a buried gate structure BG, a bit line structure BL, and a memory element 133 . The buried gate structure BG may extend in the first direction X, and the bit line structure BL may extend in the second direction Y. The first direction (X) and the second direction (Y) may cross each other. Each bit line structure BL may include a bit line 111C and a bit line spacer 115C. Each memory cell may include a lower plug (not shown), an upper plug 128C, a protective spacer 123 , and a capping layer 124 . The upper plug 128C may overlap the bit line structure BL. The protective spacer 123 may have a shape (Surrounding-Shape) surrounding the upper plug 128C. The protective spacer 123 may be in contact with one side of the upper plug 128C. The protective spacer 123 may cover the upper plug 128C. The capping layer 124 may cover the upper plug 128C. The capping layer 124 may cover the protective spacer 123 . The upper plug 128C may overlap the bit line structure BL. The protective spacer 123 and the capping layer 124 may not overlap the upper plug 128C. The top view of the upper plug 128C may include various shapes, such as a square, a circle, an oval.

Transistors constituting the peripheral circuit may be formed in the peripheral circuit region PERI. The peripheral circuit region PERI may refer to a region in which at least one transistor is to be formed. The peripheral circuit area PERI may be the sense amplifier SA. The peripheral circuit area PERI may be a sub-word line driver SWD. The transistor of the peripheral circuit region PERI may be a transistor connected to the bit line of the memory cell region CELL. The transistor of the peripheral circuit region PERI may be a transistor connected to the word line of the memory cell region CELL. The peripheral circuit region PERI may include a peripheral circuit active region 104P and a perigate structure PG.

6 is a cross-sectional view taken along lines A-A' and C-C' of FIG. 5 . A cross-sectional view of the semiconductor device 200 taken along the line B-B' in FIG. 5 may be the same as that of FIG. 2C. Accordingly, only the semiconductor device 200 along lines A-A' and C-C' will be described below.

6 , the semiconductor device 200 may include a substrate 101 , a memory cell region CELL formed on the substrate 101 , and a peripheral circuit region PERI.

A device isolation layer 103 may be formed on the substrate 101 . The device isolation layer 103 may be located in the isolation trench 102 . A plurality of active regions 104C and 104P may be defined on the substrate 101 by the device isolation layer 103 . A memory cell active region 104C may be defined in the memory cell region CELL by the device isolation layer 103 . The plurality of memory cell active regions 104C may have a shape isolated by the device isolation layer 103 . The peripheral circuit active region 104P may be defined in the peripheral circuit region PERI by the device isolation layer 103 .

The substrate 101 may include a semiconductor substrate. The substrate 101 may be made of a material containing silicon. The substrate 101 may include a III-V group semiconductor substrate.

The device isolation layer 103 may be an STI region formed by trench etching. The device isolation layer 103 may be formed by filling the isolation trench 102 with an insulating material. The device isolation layer 103 may include silicon oxide, silicon nitride, or a combination thereof.

Hereinafter, the structure of the memory cell region CELL will be described.

A source/drain region SD may be located in the memory cell active region 104C. The cell source/drain region SD may be doped with an N-type impurity or a P-type impurity. The cell source/drain region SD may include N-type impurities such as arsenic (As) or phosphorus (P).

A bit line contact plug 109C may be formed on the substrate 101 . The bit line contact plug 109C may be connected to the cell source/drain region SD. The bit line contact plug 109C may be formed through the cell region interlayer insulating layer 105 . The cell region interlayer insulating layer 105 may be formed on the substrate 101 . The cell region interlayer insulating layer 105 may include an insulating material. The lower surface of the bit line contact plug 109C may have a lower level than the upper surface of the substrate 101 . The bit line contact plug 109C may be formed of polysilicon or a metal material.

A bit line structure BL may be positioned on the bit line contact plug 109C. The bit line structure BL may include a cell barrier metal layer 110C, a bit line 111C, and a bit line hard mask 112C. The cell barrier metal layer 110C, the bit line 111C, and the bit line hard mask 112C may have the same width. The width of the bit line contact plug 109C may be the same as the width of the bit line structure BL. The bit line structure BL may extend in a line shape.

A cell barrier metal layer 110C may be positioned on the bit line contact plug 109C. The cell barrier metal layer 110C may include a material containing titanium nitride (TiN). A bit line 111C may be positioned on the cell barrier metal layer 110C. The bit line 111C may include a tungsten-containing material. The bit line 111C may include tungsten (W) or a tungsten compound. A bit line hard mask 112C may be positioned on the bit line 111C. The bit line hard mask 112C may include an insulating material. The bit line hard mask 112C may include a material having an etch selectivity with respect to the bit line 111C. The bit line hard mask 112C may be formed of silicon nitride.

A bit line spacer 115C may be positioned on both sidewalls of the bit line structure BL. The bit line spacer 115C may extend in a line shape. The upper surface of the bit line spacer 115C may be at the same level as the upper surface of the bit line structure BL. The bit line spacer 115C may include an insulating material. The bit line spacer 115C may include a low-k material. The bit line spacer 115C may include a multi-layer spacer. The bit line spacer 115C may include an air gap (not shown). The multilayer spacer may include a NON structure in which oxide spacers are positioned between nitride spacers. In another embodiment, the multilayer spacer may include a first spacer, a second spacer, and an air gap between the first spacer and the second spacer.

A lower plug 120 covering the upper surface of the bit line structure BL may be positioned between the bit line structures BL. The shape of the lower plug 120 may be the same as that of the lower plug 24 of FIG. 2B . The lower plug 120 may include a pillar part 120M and an extension part 120T. The pillar part 120M may be positioned between the bit line structures BL. The extension part 120T may extend from the pillar part 120M to overlap any one of the bit line structures BL. The extension 120T may partially overlap any one of the bit line structures BL. The bit line structure BL may be a concept included in the conductive line pattern.

The upper surface of the lower plug 120 may be positioned at a higher level than the upper surface of the bit line structure BL. The upper surface of the extension part 120T may be positioned at a higher level than the upper surface of the bit line structure BL. A bit line spacer 115C may be positioned between the pillar part 120M and the bit line structure BL. The bottom surface of the pillar part 120M may be located at a level lower than the top surface of the substrate 101 . A bottom surface of the pillar part 120M may be connected to the cell source/drain region SD. A lower portion of the pillar part 120M may extend in a lateral direction to have a bulb type. A top-view of the extension part 120T may include a quadrangle, a circle, or an oval.

The lower plug 120 may include a silicon-containing material. The pillar part 120M and the extension part 120T may include the same material. The pillar part 120M and the extension part 120T may include a silicon-containing material. The pillar part 120M and the extension part 120T may be doped with impurities. For example, impurities may be doped by a doping process such as implantation. In this embodiment, the pillar part 24M and the extension part 24T may include polysilicon.

A celohmic contact layer 127C may be positioned on the lower plug 120 . The cell ohmic contact layer 127C may include cobalt silicide (CoSi _x ). In the present embodiment, the celohmic contact layer 127C may include cobalt silicide on 'CoSi ₂ phase'. Accordingly, it is possible to form cobalt silicide of low resistance while improving the contact resistance.

An upper plug 128C may be positioned on the celomic contact layer 127C. The upper plug 128C may include a metal-containing material. The upper plug 128C may include a conductive material. The upper plug 128C may include a metal-containing material. The upper plug 128C may include a tungsten (W)-containing material. The upper plug 128C may include tungsten (W).

A capping hole 122 may be positioned between the lower plugs 120 . The bottom surface of the capping hole 122 may be positioned on the lower plug 120 , the bit line spacer 115C and the bit line hard mask 112C. The bottom surface of the capping hole 122 may be located at a level higher than the bottom surface of the bit line hard mask 112C, and may be located at a level lower than the top surface of the bit line hard mask 112C. The upper surface of the capping hole 122 may be located at the same level as the upper surface of the upper plug 128C.

A capping layer 124 may be positioned between the lower plugs 120 . The capping layer 124 may fill the capping hole 122 . The capping layer 124 may cover the lower plug 120 . The capping layer 124 may cover the upper plug 128C. The upper surface of the capping layer 124 may be at the same level as the upper surface of the upper plug 128C. The upper surface of the capping layer 124 may be at a higher level than the upper surface of the lower plug 120 . The capping layer 124 may not overlap the upper plug 128C. The capping layer 124 may partially overlap the pillar part 120M of the lower plug 120 . The upper surface of the capping layer 124 may be at a higher level than the upper surface of the extension part 120T. A portion of the capping layer 124 may be in contact with the substrate 101 .

The capping layer 124 may include an insulating material. The capping layer 124 may include a nitrogen-containing material. The capping layer 124 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In this embodiment, the capping layer 124 may be formed of silicon nitride. The capping layer 124 may be formed by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method. The capping layer 124 may be selectively grown by an atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD) process using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) as reactive gases.

A protective spacer 123 may be positioned between the capping layer 124 and the upper plug 128C. A protective spacer 123 may be positioned between the capping layer 124 and the lower plug 120 . The protective spacer 123 may include a shape (Surronding-Shape) surrounding the lower plug 120 . The protective spacer 123 may fully-cover the sidewall of the extension part 120T. The protective spacer 123 may partially cover the sidewall of the pillar part 120M. The protective spacer 123 may cover the sidewall of the upper plug 128C. The capping layer 124 may cover a sidewall of the protective spacer 123 . The protective spacer 123 may be in contact with a portion of the bit line hard mask 112C. The upper surface of the protective spacer 123 may be positioned at the same level as the upper surface of the upper plug 128C.

The protective spacer 123 may include an insulating material. The protective spacer 123 may include a nitrogen-containing material. The protective spacer 123 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In this embodiment, the protective spacer 123 may include silicon nitride. The protective spacer 123 may be formed by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method. The protective spacer 123 may be selectively grown by an atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD) process using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) as reactive gases.

Referring to FIG. 5 , a narrow etch region E1 and a wide etch region E2 may be formed when the capping hole 122 is formed. When the capping hole 122 is formed, the plug material of the narrow etched region E1 may remain because the open area is narrow. When the capping hole 122 is formed, the plug material of the wide etch area E2 may be removed because the open area is large. The protective spacer 123 may adjust the open area of the narrow etched region E1 . The protective spacer 123 may further narrow the open area of the narrow etched region E1 to prevent the lower plug 120 from being removed.

A pattern insulating layer 132 may be formed on the upper plug 128C and the capping layer 124 . A memory element 133 electrically connected to the upper plug 128C may be formed on the upper plug 128C. The memory element 133 may include a conductive layer. The memory element 133 may be a capacitor.

Hereinafter, the structure of the peripheral circuit region PERI will be described.

The transistor of the peripheral circuit region PERI includes the peripheral circuit active region 104P, the perigate structure PG on the peripheral circuit active region 104P, the gate spacers 115P and the ferrigate formed on both sidewalls of the perigate structure PG. Perisource/drain regions SDPs arranged on both sides of the structure PG and formed in the peripheral circuit active region 104P may be included. The perisource/drain region SDP may be doped with an N-type impurity or a P-type impurity. The perisource/drain region SDP may include N-type impurities such as arsenic (As) or phosphorus (P). The perisource/drain region SDP may include a low-concentration source/drain region and a high-concentration source/drain region.

The peripheral gate structure PG includes a gate insulating layer 107 on the peripheral circuit active region 104P, a lower gate electrode 109P on the gate insulating layer 107, and a peripheral barrier metal layer 110P on the lower gate electrode 109P. , an upper gate electrode 111P on the peripheral barrier metal layer 110P, and a gate hard mask 112P on the upper gate electrode 111P. The ferri gate structure PG may be at least one of a Planar Gate, a Recess Gate, a Buried Gate, an Omega Gate, and a FIN Gate. . In this embodiment, the ferrigate structure PG may be a planar gate.

A gate insulating layer 107 may be positioned on the substrate 101 . The gate insulating layer 107 may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. For example, the high-k material may include hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicate nitride (HfSiON), or a combination thereof. The gate insulating layer 107 may further include an interface layer (not shown). The interfacial layer may include silicon oxide, silicon nitride, or a combination thereof. The gate insulating layer 107 may be formed by laminating an interface layer and a high-k material.

A lower gate electrode 109P may be formed on the gate insulating layer 107 . The lower gate electrode 109P may include a semiconductor material. The lower gate electrode 109P may be doped with impurities. For example, impurities may be doped by a doping process such as implantation. In this embodiment, the lower gate electrode 109P may include polysilicon. In another embodiment, the lower gate electrode 109P may be formed of a metal-containing material.

A peripheral barrier metal layer 110P may be positioned on the lower gate electrode 109P. The barrier metal layer 110P may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. . In this embodiment, the peripheral barrier metal layer 110P may include a material containing titanium nitride (TiN).

An upper gate electrode 111P may be positioned on the peripheral barrier metal layer 110P. The upper gate electrode 111P may include a metal-containing material. The upper gate electrode 111P may include a metal, a metal nitride, a metal silicide, or a combination thereof. In this embodiment, the upper gate electrode 111P may include tungsten (W) or a tungsten compound.

A gate hard mask 112P may be positioned on the upper gate electrode 111P. The gate hard mask 112P may be formed of an insulating material having an etch selectivity with respect to the upper gate electrode 111P. The height of the gate hard mask 112P may be greater than the height of the upper gate electrode 111P. The gate hard mask 112P may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In this embodiment, the gate hard mask 112P may be formed of silicon nitride.

Gate spacers 115P may be positioned on both sidewalls of the ferri gate structure PG. The gate spacer 115P may be formed of an insulating material. The gate spacer 115P may include a low-k material. The gate spacer 115P may include oxide or nitride. The gate spacer 115P may include a multilayer spacer. The gate spacer 115P may include an air gap (not shown). The multilayer spacer may include a NON structure in which oxide spacers are positioned between nitride spacers. In another embodiment, the multilayer spacer may include a first spacer, a second spacer, and an air gap between the first spacer and the second spacer.

The peripheral circuit source/drain regions 104P of the peripheral circuit region PERI may be connected to the metal wiring 128P through the periodic contact layer 127P. The periodic contact layer 127P may include metal silicide. The periodic contact layer 127P may include the same material as the celohmic contact layer 127C.

A conductive liner (not shown) may be further included between the periodical contact layer 127P and the metal wiring 128P. The conductive liner (not shown) may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof.

The metal wiring 128P may pass through the structure insulating layer 116 to be connected to the peripheral circuit source/drain regions 104P. The structure insulating layer 116 may include an insulating material. The structure insulating layer 116 may include silicon oxide, silicon nitride, a low-k material, or a combination thereof. The metal wiring 128P may be connected to the peripheral circuit source/drain region 104P through the periodical contact layer 127P. The metal wiring 128P may include a metal-containing material. The metal wiring 128P includes gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), titanium (Ti), platinum (Pt), and palladium (Pd). , tin (Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr), and may include any one or more of molybdenum (Mo). The metal wiring 128P may be formed of a single layer or a multilayer layer of a conductive material. In this embodiment, the metal wiring 128P may include a tungsten-containing material. The metal wiring 128P may include tungsten (W) or a tungsten compound. The metal wiring 128P may be formed of the same material as the upper plug 128C of the memory cell region CELL.

The capping layer 124 of the peripheral circuit region PERI may fill a space between the metal wirings 128P. The capping layer 124 of the peripheral circuit region PERI may cover an upper sidewall of the metal wiring 128P. The capping layer 124 of the peripheral circuit region PERI may serve to protect the metal wiring 128P from subsequent processes. The capping layer 124 of the peripheral circuit region PERI may include an insulating material. The capping layer 124 of the peripheral circuit region PERI may include silicon nitride.

According to the above-described embodiment, loss of the lower plug 120 can be prevented in a subsequent process by forming the protective spacer 123 . Accordingly, a contact defect between the lower plug 120 and the memory cell active region 104C can be improved. In addition, since the sel ohmic contact layer 127C is formed at a level higher than the upper surface of the bit line structure BL, the difficulty of the process may be reduced when the sel ohmic contact layer 127C is formed. Accordingly, the contact resistance can be improved. In addition, since the upper plug 128C is formed at a level higher than the upper surface of the bit line structure BL, the upper plug 128C can be formed to be large. Accordingly, a contact defect between the memory element 133 and the storage node contact plug SNC may be improved.

7A to 7S are diagrams illustrating a method of manufacturing the semiconductor device 200 according to an exemplary embodiment. In FIGS. 7A to 7S , the same reference numerals as in FIG. 6 mean the same components. Hereinafter, detailed descriptions of overlapping components will be omitted.

As shown in FIG. 7A , the substrate 101 is prepared. The substrate 101 may include a memory cell region CELL and a peripheral circuit region PERI. A plurality of memory cells may be formed in the memory cell region CELL. A transistor may be formed in the peripheral circuit region PERI.

A device isolation layer 103 and an active region 104 may be formed on the substrate 101 . A memory cell active region 104C may be defined in the memory cell region CELL by the device isolation layer 103 . The peripheral circuit active region 104P may be defined in the peripheral circuit region PERI by the device isolation layer 103 . The device isolation layer 103 may be an STI region formed by trench etching. The device isolation layer 103 may include silicon oxide, silicon nitride, or a combination thereof.

A cell source/drain region SD may be formed in the memory cell active region 104C. A doping process may be performed to form the cell source/drain regions SD. The doping process may include a process such as implantation or plasma doping (PLAD). The cell source/drain regions SD may be doped with impurities of the same conductivity type. The cell source/drain region SD may be a region to which a bit line contact plug or a storage node contact plug is to be connected.

A cell region interlayer insulating layer 105 may be formed on the substrate 101 of the memory cell region CELL. The cell region interlayer insulating layer 105 may include silicon oxide, silicon nitride, low-k materials, or a combination thereof. The cell region interlayer insulating layer 105 may include one or more layers. The cell region interlayer insulating layer 105 may include one or more layers formed of different materials. In this embodiment, the cell region interlayer insulating layer 105 may include two layers. In this embodiment, the cell region interlayer insulating layer 105 may include a layer formed of silicon oxide and a layer formed of silicon nitride.

As shown in FIG. 7B , a bit line contact hole 106 may be formed in the cell region interlayer insulating layer 105 . The bit line contact hole 106 may be formed by etching the cell region interlayer insulating layer 105 using a bit line opening mask (not shown) as an etch mask. The bit line opening mask may include a photoresist pattern. The bit line opening mask may cover the peripheral circuit area PERI. Accordingly, the peripheral circuit region PERI may be protected during the etching process of the bit line contact hole 106 .

The method may further include recessing the exposed surface of the substrate 101 to form the bit line contact hole 106 . A portion of the substrate 101 may be exposed through the bit line contact hole 106 . The lower surface of the bit line contact hole 106 may be located at a level lower than the upper surface of the substrate 101 . A portion of the device isolation layer 103 around the cell source/drain region SD may be exposed by the bit line contact hole 106 . When viewed from a top view, the bit line contact hole 106 may have a circular shape or an elliptical shape.

A preliminary gate insulating layer 107A may be formed on the substrate 101 of the peripheral circuit region PERI. The thickness of the preliminary gate insulating layer 107A may be smaller than the thickness of the cell region interlayer insulating layer 105 . While the preliminary gate insulating layer 107A is being formed, since the memory cell region CELL is covered by a mask pattern (not shown), the preliminary gate insulating layer 107A may be formed only in the peripheral circuit region PERI. The preliminary gate insulating layer 107A may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. For example, the high-k material may include hafnium oxide (HfO ₂ ), hafnium silicate (HfSiO), hafnium silicate nitride (HfSiON), or a combination thereof. The preliminary gate insulating layer 107A may further include an interface layer (not shown). The interfacial layer may include silicon oxide, silicon nitride, or a combination thereof. The preliminary gate insulating layer 107A may be formed by laminating an interface layer and a high-k material.

As shown in FIG. 7C , a spare bit line contact plug 109A may be formed in the bit line contact hole 106 of the memory cell region CELL. The spare bit line contact plug 109A may fill the bit line contact hole 106 . The upper surface of the spare bit line contact plug 109A may be at the same level as the upper surface of the cell region interlayer insulating layer 105 . In the peripheral circuit region PERI, a preliminary lower gate electrode 109B may be formed on the preliminary gate insulating layer 107A.

The preliminary bit line contact plug 109A and the preliminary lower gate electrode 109B may be simultaneously formed. A common conductive layer covering the cell region interlayer insulating layer 105, the bit line contact hole 106, and the preliminary gate insulating layer 107A to form the preliminary bit line contact plug 109A and the preliminary lower gate electrode 109B. (109) can be formed. Thereafter, a process of planarizing the common conductive layer 109 so that the upper surface of the spare bit line contact plug 109A is exposed may be included. Accordingly, the upper surface of the spare bit line contact plug 109A may be exposed. The upper surface of the spare bit line contact plug 109A may be at the same level as the upper surface of the cell region interlayer insulating layer 105 . The upper surface of the preliminary bit line contact plug 109A may be at the same level as the upper surface of the preliminary lower gate electrode 109B.

The preliminary bit line contact plug 109A and the preliminary lower gate electrode 109B may include the same material. The preliminary bit line contact plug 109A and the preliminary lower gate electrode 109B may include a semiconductor material. The preliminary bit line contact plug 109A and the preliminary lower gate electrode 109B may include a silicon-containing material. The preliminary bit line contact plug 109A and the preliminary lower gate electrode 109B may include polysilicon. Polysilicon may be doped with impurities.

As shown in FIG. 7D , a barrier metal layer 110A may be formed on the cell region interlayer insulating layer 105 , the preliminary bit line contact plug 109A, and the preliminary lower gate electrode 109B. The height of the barrier metal layer 110A may be smaller than the height of the preliminary lower gate electrode 109B. The height of the barrier metal layer 110A may be smaller than the height of the preliminary gate insulating layer 107A. The barrier metal layer 110A may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. In this embodiment, the barrier metal layer 110A may include a material containing titanium nitride (TiN).

A metal layer 111A may be formed on the barrier metal layer 110A. The metal layer 111A may include a material having a specific resistance lower than that of the preliminary bit line contact plug 109A and the preliminary lower gate electrode 109B. The metal layer 111A may include a metal material having a specific resistance lower than that of the preliminary bit line contact plug 109A and the preliminary lower gate electrode 109B. For example, the metal layer 111A may include a metal, a metal nitride, a metal silicide, or a combination thereof. In this embodiment, the metal layer 111A may include tungsten (W) or a tungsten compound.

A hard mask layer 112A may be formed on the metal layer 111A. The hard mask layer 112A may be formed of an insulating material. The hard mask layer 112A may be formed of a material having an etch selectivity with respect to the metal layer 111A. The hard mask layer 112A may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In this embodiment, the hardmask layer 112A may be formed of silicon nitride.

A line mask 113 may be formed on the hard mask layer 112A. The line mask 113 may include a photoresist pattern. The line mask 113 may include a line shape extending in one direction. A line width of the line mask 113 of the memory cell region CELL may be smaller than a diameter of the bit line contact hole 106 . The line width of the line mask 113 of the memory cell region CELL may be smaller than the line width of the line mask 113 of the peripheral circuit region PERI.

As shown in FIG. 7E , a bit line structure BL and a perigate structure PG may be formed. The bit line structure BL may be formed in the memory cell region CELL, and the perigate structure PG may be formed in the peripheral circuit region PERI. The bit line structure BL and the perigate structure PG may be simultaneously formed. The bit line structure BL may include a cell barrier metal layer 110C, a bit line 111C, and a bit line hard mask 112C. The peripheral gate structure PG may include a gate insulating layer 107 , a lower gate electrode 109P, a peripheral barrier metal layer 110P, an upper gate electrode 111P, and a gate hard mask 112P.

A method of forming the bit line structure BL will be described.

The hard mask layer 112A may be etched using the line mask 113 as an etch mask. Accordingly, the bit line hard mask 112C may be formed. The metal layer 111A, the barrier metal layer 110A, and the spare bit line contact plug 109A may be etched using the bit line hard mask 112C as an etch mask. Accordingly, the bit line 111C, the cell barrier metal layer 110C, and the bit line contact plug 109C may be formed. Line widths of the bit line contact plug 109C, the cell barrier metal layer 110C, the bit line 111C, and the bit line hard mask 112C may be the same.

A bit line contact plug 109C may be formed on the cell source/drain region SD. The bit line contact plug 109C may interconnect the cell source/drain region SD and the bit line 111C. A line width of the bit line contact plug 109C may be smaller than a diameter of the bit line contact hole 106 . Accordingly, a gap G may be formed on both sidewalls of the bit line contact plug 109C. The gap G may be independently formed on both sidewalls of the bit line contact plug 109C. Accordingly, one bit line contact plug 109C and a pair of gaps G are positioned in the bit line contact hole 106, and the pair of gaps G can be separated by the bit line contact plugs 109C. there is. The bit line 111C may extend in either direction while covering the bit line contact plug 109C. The bit line 111C may extend in a line shape.

A method of forming the ferrigate structure PG will be described.

The hard mask layer 112A may be etched using the line mask 113 as an etch mask. Accordingly, the gate hard mask 112P may be formed. The metal layer 111A, the barrier metal layer 110A, the preliminary lower gate electrode 109B, and the preliminary gate insulating layer 107A may be etched using the gate hard mask 112P as an etch mask. Accordingly, the gate insulating layer 107, the lower gate electrode 109P, the peripheral barrier metal layer 110P, and the upper gate electrode 111P may be formed. The line widths of the gate insulating layer 107 , the lower gate electrode 109P, the peripheral barrier metal layer 110P, and the upper gate electrode 111P may be the same.

The bit line structure BL and the perigate structure PG may be simultaneously formed. The bit line structure BL and the perigate structure PG may be simultaneously formed by one etching process. Accordingly, the etching process may be simplified. After the bit line structure BL and the perigate structure PG are formed, the line mask 113 may be removed.

As shown in FIG. 7F , bit line spacers 115C may be formed on both sidewalls of the bit line structure BL. The bit line spacer 115C may be formed of an insulating material. The bit line spacer 115C may include a low-k material. The bit line spacer 115C may include oxide or nitride. The bit line spacer 115C may include silicon oxide, silicon nitride, or metal oxide. The bit line spacer 115C may include SiO ₂ , Si ₃ N ₄ , or SiN. The bit line spacer 115C may include a multi-layer spacer. The bit line spacer 115C may include an air gap (not shown). Accordingly, a pair of line-type air gaps may be formed on both sidewalls of the bit line spacer 115C. The pair of line-shaped air gaps may be symmetrical. In some embodiments, the multilayer spacer may include a first spacer, a second spacer, and a third spacer, and a third spacer may be positioned between the first spacer and the second spacer. The multilayer spacer may include a NON structure in which oxide spacers are positioned between nitride spacers. In another embodiment, the multilayer spacer may include a first spacer, a second spacer, and an air gap between the first spacer and the second spacer.

In another embodiment, the gap 115C may be filled with a bit line contact insulating layer (not shown) other than the bit line spacers 115C. The upper surface of the bit line contact insulating layer (not shown) may be at the same level as the upper surface of the bit line contact plug 109C. A bit line spacer 115C may be formed on the bit line contact insulating layer (not shown). The bit line contact insulating layer (not shown) may include an insulating material. The bit line contact insulating layer (not shown) may include oxide or nitride. The bit line contact insulating layer (not shown) may include silicon oxide, silicon nitride, or metal oxide.

Gate spacers 115P may be formed on both sidewalls of the perigate structure PG. The gate spacer 115P may be formed of an insulating material. The gate spacer 115P may include a low-k material. The gate spacer 115P may include oxide or nitride. The gate spacer 115P may include silicon oxide, silicon nitride, or metal oxide. The gate spacer 115P may include SiO ₂ , Si ₃ N ₄ , or SiN. The gate spacer 115P may include a multilayer spacer. The gate spacer 115P may include an air gap (not shown). Accordingly, a pair of line-type air gaps may be formed on both sidewalls of the gate spacer 115P. The pair of line-shaped air gaps may be symmetrical. In some embodiments, the multilayer spacer may include a first spacer, a second spacer, and a third spacer, and a third spacer may be positioned between the first spacer and the second spacer. The multilayer spacer may include a NON structure in which oxide spacers are positioned between nitride spacers. In another embodiment, the multilayer spacer may include a first spacer, a second spacer, and an air gap between the first spacer and the second spacer.

The bit line spacer 115C and the gate spacer 115P may be formed simultaneously. The bit line spacer 115C and the gate spacer 115P may protect the bit line structure BL and the perigate structure PG from subsequent processes.

Subsequently, impurities may be doped into the peripheral circuit active region 104P on both sides of the perigate structure PG to form a perisource/drain region SDP. Impurities may be doped into the peripheral circuit active region 104P on both sides of the perigate structure PG to form a perisource/drain region SDP. The perisource/drain region SDP may be doped with an N-type impurity or a P-type impurity. The perisource/drain region SDP may include a low-concentration source/drain region and a high-concentration source/drain region. The perisource/drain region SDP may be formed in two steps. The perisource/drain region SDP may include a region having a deep junction depth and a region having a shallow junction depth.

As shown in FIG. 7G , a structure insulating layer 116 filling between the bit line structure BL and the ferrigate structure PG may be formed. The structure insulating layer 116 may be planarized so that upper surfaces of the bit line structure BL and the ferrigate structure PG are exposed. During the planarization process of the insulating structure layer 116 , the bit line spacer 115C may be planarized so that the upper surface of the bit line structure BL is exposed. During the planarization process of the structure insulating layer 116 , the gate spacer 115P may be planarized so that the upper surface of the ferri gate structure PG is exposed. The structure insulating layer 116 may extend parallel to the bit line structure BL. The structure insulating layer 116 may extend parallel to the ferrigate structure PG.

The structure insulating layer 116 may be formed of a material having an etch selectivity with respect to the bit line spacer 115C and the gate spacer 115P. The structure insulating layer 116 may include an insulating material. The structure insulating layer 116 may include oxide or nitride. The structure insulating layer 116 may include silicon oxide, silicon nitride, or metal oxide. The structure insulating layer 116 may include SiO ₂ , Si ₃ N ₄ or SiN. The structure insulating layer 116 may include a spin-on insulating material (SOD).

Subsequently, a peripheral circuit covering mask 117M may be formed on the structure insulating layer 116 of the peripheral circuit region PERI. The peripheral circuit covering mask 117M may open only the memory cell region CELL and cover the peripheral circuit region PERI. Accordingly, only the peripheral circuit region PERI may be protected in a subsequent process.

Subsequently, a storage node contact hole 117 may be formed in the structure insulating layer 116 of the memory cell region CELL. The storage node contact hole 117 may be formed by etching the structure insulating layer 116 of the memory cell region CELL. The storage node contact hole 117 may be formed between the bit line structures BL. A bottom surface of the storage node contact hole 117 may extend into the substrate 101 . During the formation of the storage node contact hole 117 , the device isolation layer 103 , the cell region interlayer insulating layer 105 , and the cell source/drain region SD may be recessed to a predetermined depth. A portion of the substrate 101 may be exposed through the storage node contact hole 117 . The lower surface of the storage node contact hole 117 may be located at a level lower than the upper surface of the substrate 101 . The bottom surface of the storage node contact hole 117 may be at a higher level than the bottom surface of the bit line contact plug 109C.

A dip-out and trimming process may be performed to form the storage node contact hole 117 . The storage node contact hole 117 may be formed without loss of the bit line spacer 115C by the deep-out. The side and lower areas of the storage node contact hole 117 may be expanded by the trimming process. A portion of the cell region interlayer insulating layer 105 and the substrate 101 may be removed by the trimming process. A lower portion of the storage node contact hole 117 may extend in a lateral direction to have a bulb type.

The peripheral circuit covering mask 117M may be removed after forming the storage node contact hole 117 .

As shown in FIG. 7H , a plug material 120A covering the upper surface of the bit line hard mask 112C and the upper surface of the structure insulating layer 116 may be formed in the storage node contact hole 117 . . The plug material 120A may fill the storage node contact hole 117 . The plug material 120A may cover the bit line structure BL. The upper surface of the plug material 120A may be positioned at a higher level than the upper surface of the bit line hard mask 112C. The plug material 120A may cover the peripheral circuit area PERI. The plug material 120A may cover the structure insulating layer 116 of the peripheral circuit area PERI. A bit line spacer 115C may be positioned between the bit line 111C and the plug material 120A. A lower surface of the plug material 120A may be connected to the cell source/drain region SD.

The plug material 120A may include a silicon-containing material. The plug material 120A may be doped with impurities. For example, impurities may be doped by a doping process such as implantation. In this embodiment, the plug material 120A may include polysilicon.

7I , a plug pattern mask 121 may be formed on the plug material 120A. The plug pattern mask 121 may include a photoresist pattern. The plug material 120A may be etched using the plug pattern mask 121 as an etch mask. The plug material 120A may be etched to form the plug pattern 120B. By forming the plug pattern 120B, the plug material 120A may be separated from each other. As the plug patterns 120B are formed, preliminary capping holes 122A may be formed between the plug patterns 120B. The plug pattern 120B of the memory cell region CELL may have the same shape as the plug pattern 24B of FIG. 4A .

When forming the plug pattern 120B, a portion of the bit line hard mask 112C and the bit line spacer 115C may be etched together. Accordingly, a portion of the bit line hard mask 112C and the bit line spacer 115C may be exposed by the preliminary capping hole 122A. The top surface of the plug pattern 120B may be at a higher level than the bottom surface of the preliminary capping hole 122A. The upper surface of the plug pattern 120B may be at a higher level than the upper surface of the bit line hard mask 112C. The lower surface of the preliminary capping hole 122A may be lower than the upper surface of the bit line hard mask 112C and located at a level higher than the lower surface of the bit line hard mask 112C. A top view of the plug pattern 120B may include various shapes, such as a square, a circle, and an oval.

When the plug material 120A is etched using the plug pattern mask 121 as an etch mask, the plug material 120A of the peripheral circuit region PERI may be removed. Accordingly, the upper surface of the structure insulating layer 116 of the peripheral circuit region PERI may be exposed.

7J , a protective spacer 123 may be formed on a sidewall of the plug pattern 120B. After forming a preliminary protective spacer (not shown) to form the protective spacer 123 , an etching process may be performed. Accordingly, the protective spacer may not be formed in the peripheral circuit region PERI. The protective spacer 123 may cover a sidewall of the plug pattern 120B. The protective spacer 123 may include a Surrounding-Shape surrounding the plug pattern 120B. A top view of the protective spacer 123 may include various shapes such as a square ring shape or a ring shape. The protective spacer 123 of the memory cell region CELL may have the same shape as the protective spacer 26 of FIG. 4B .

The protective spacer 123 may include an insulating material. The protective spacer 123 may be a non-oxide base materail. The protective spacer 123 may be a nitride base material. The protective spacer 123 may include a nitrogen-containing material. The protective spacer 123 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In this embodiment, the protective spacer 123 may include silicon nitride. The protective spacer 123 may be formed by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method. The protective spacer 123 may be selectively grown by an atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD) process using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) as reactive gases.

The protective spacer 123 may reduce the area of the plug pattern 120B exposed by the preliminary capping hole 122A. Accordingly, it is possible to prevent loss of the plug pattern 120B in a subsequent process and to prevent a contact failure with the neighboring memory cell active region 104C.

As shown in FIG. 7K , the plug pattern 120B may be recessed to a predetermined depth. The recessing process may be performed as an etchback process, or a chemical mechanical polishing (CMP) process and an etchback process may be sequentially performed. Accordingly, the capping hole 122 may be formed. As the capping hole 122 is formed. A portion of the bit line hard mask 111C and the bit line spacer 115C may be removed. A portion of the bit line hard mask 112C and the bit line spacer 115C in the capping hole 122 may be exposed. The lower surface of the capping hole 122 may be positioned at a level lower than the upper surface of the bit line hard mask 112C and higher than the lower surface of the bit line hard mask 112C.

Referring to FIG. 6 , a narrow etch region E1 and a wide etch region E2 may be formed when the capping hole 122 is formed. When the capping hole 25 is formed, the plug pattern 120B of the narrow etched area E1 may remain because the open area is narrow. When the capping hole 25 is formed, the plug pattern 120B of the wide etched area E2 may be removed because the open area is large. The protective spacer 123 may adjust the open area of the narrow etched region E1 . The protective spacer 123 may further narrow the open area of the narrow etched region E1 to prevent the plug pattern 120B of the narrow etched region E1 from being removed. Accordingly, it is possible to prevent a contact failure with the neighboring memory cell active region 104C.

As shown in FIG. 7L , a capping layer 124 may be formed between the plug patterns 120B of the memory cell region CELL. A capping layer 124 may be formed on the structure insulating layer 116 of the peripheral circuit region PERI. The capping layer 124 may fill the capping hole 122 .

In order to form the capping layer 124 , a preliminary capping layer 124A covering the plug pattern 120B and the structure insulating layer 116 may be formed. A process of planarizing the pre-capping layer 124A to expose the top surface of the plug pattern 120B may be included. Accordingly, the upper surface of the plug pattern 120B may be exposed. The upper surface of the capping layer 124 may be at the same level as the upper surface of the plug pattern 120B. The upper surface of the capping layer 124 may be at the same level in the memory cell region CELL and the peripheral circuit region PERI. A portion of the capping layer 124 in the memory cell region CELL may be in contact with the substrate 101 . A protective spacer 123 may be positioned between the capping layer 124 and the plug pattern 120B. The capping layer 124 of the memory cell region CELL may have the same shape as the capping layer 27 of FIG. 4D .

The capping layer 124 may include an insulating material. The capping layer 124 may include silicon oxide, silicon nitride, low-k materials, or a combination thereof. The capping layer 124 may include a nitrogen-containing material. The capping layer 124 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In this embodiment, the capping layer 124 may be formed of silicon nitride. The capping layer 124 may be formed by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method. The capping layer 124 may be selectively grown by an atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD) process using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) as reactive gases.

As shown in FIG. 7M , the plug pattern 120B may be recessed to a predetermined depth. The recessing process may be performed as an etchback process, or a chemical mechanical polishing (CMP) process and an etchback process may be sequentially performed. As the plug pattern 120B is recessed, the lower plug 120 may be formed. The lower plug 120 may be referred to as a recessed plug pattern 120B. As the lower plug 120 is formed, a portion of the sidewall of the protective spacer 123 may be exposed.

The lower plug 120 may include a pillar part 120M and an extension part 120T. The pillar part 120M may be positioned between the bit line structures BL. The extension part 120T may extend from the pillar part 120M to overlap any one of the bit line structures BL. The upper surface of the lower plug 120 may be located at a higher level than the upper surface of the bit line hard mask 112C. The upper surface of the lower plug 120 may be located at a level lower than the upper surface of the capping layer 124 . The pillar part 120M may include a pillar-shape. The pillar part 120M may be in contact with the substrate. The top view of the extension part 120T may include various shapes, such as a rectangle, a circle, and an oval. The protective spacer 123 may include a shape surrounding the lower plug 120 . The protective spacer 123 may fully-cover the sidewall of the extension part 120T. The protective spacer 123 may partially cover the sidewall of the pillar part 123M. The capping layer 124 may cover the lower plug 120 .

Process defects can be reduced by etching the plug material 120A to form the lower plug 120 including the extension part 120T. In addition, it is possible to secure the mass productivity of the semiconductor device by simplifying the process.

As shown in FIG. 7N , a metal wiring hole 126 may be formed in the peripheral circuit region PERI. A metal wiring hole mask 125 may be formed to form the metal wiring hole 126 . The metal wiring hole mask 125 may include a photoresist pattern. The metal wiring hole mask 125 may cover the memory cell region CELL. Accordingly, the memory cell region CELL may be protected during the etching process of the metal interconnection hole 126 .

The capping layer 124 and the structure insulating layer 116 may be etched using the metal wiring hole mask 125 as an etch mask. Accordingly, the metal wiring hole 126 may be formed. Accordingly, the surface of the perisource/drain region SDP may be exposed. The metal wiring hole 126 may be formed on both sides of the ferrigate structure PG. As the metal wiring hole 126 is formed, a portion of the substrate 101 of the peripheral circuit region PERI may be etched. As the metal wiring hole 126 is formed, a portion of the substrate 101 of the peripheral circuit region PERI may be exposed.

As shown in FIG. 7O , a cell ohmic contact layer 127C may be formed on the lower plug 120 of the memory cell region CELL. A periodic contact layer 127P may be formed on the exposed surface of the perisource/drain region SDP of the peripheral circuit region PERI. The celohmic contact layer 127C and the periodic contact layer 127P may be simultaneously formed. Deposition and annealing of a silicidable metal layer may be performed to form the celomic contact layer 127C and the periodic contact layer 127P.

The celohmic contact layer 127C and the periodic contact layer 127P may include the same material. The celohmic contact layer 127C and the periodic contact layer 127P may include metal silicide. The celohmic contact layer 127C and the periodic contact layer 127P may include cobalt silicide (CoSi _x ). In the present embodiment, the celomic contact layer 127C and the periodic contact layer 127P may include cobalt silicide in the 'CoSi ₂ phase'. Accordingly, it is possible to form cobalt silicide of low resistance while improving the contact resistance.

Although not shown, a conductive liner may be formed on the celohmic contact layer 127C and the periodic contact layer 127P. The conductive liner may include a metal or a metal nitride. The conductive liner may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof.

By forming the cell ohmic contact layer 127C at a level higher than the upper surface of the bit line structure BL, the formation of the cell ohmic contact layer 127C may be facilitated. In addition, since the cell ohmic contact layer 127C having a large area can be formed, the contact resistance of the memory cell region CELL can be improved.

As shown in FIG. 7P , a metal contact layer 128 may be formed on the celohmic contact layer 127C and the periodic contact layer 127P. The metal contact layer 128 may cover an upper surface of the capping layer 124 . The metal contact layer 128 may fill the metal wiring hole 126 . The metal contact layer 128 may cover the capping layer 124 of the peripheral circuit region PERI.

The metal contact layer 128 may include a metal-containing material. The metal contact layer 128 may include a conductive material. The metal contact layer 128 may include a metal. The metal contact layer 128 may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), titanium (Ti), platinum (Pt), and palladium (Pd). ), tin (Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr), and may include any one or more of molybdenum (Mo). The metal contact layer 128 may include a tungsten (W)-containing material. In this embodiment, the metal contact layer 128 may include tungsten (W) or a tungsten compound.

The metal contact layer 128 may be formed by a chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) method. The metal contact layer 128 may use plasma to increase the deposition effect. That is, the metal contact layer 128 may be formed by a method such as plasma enhanced CVD (PECVD) or plasma enhanced ALD (PEALD). In this embodiment, the metal contact layer 128 may be formed by chemical vapor deposition (CVD).

As shown in FIG. 7Q , the upper plug 128C may be formed by recessing the metal contact layer 128 . An upper plug mask 129 may be formed on the metal contact layer 128 of the peripheral circuit area PERI. The upper plug mask 129 may include a photoresist pattern. While the upper plug 128C is formed in the memory cell region CELL, the peripheral circuit region PERI may be protected. Accordingly, the metal contact layer 128 of the peripheral circuit region PERI may not be etched. As the upper plug 128C is formed in the memory cell region CELL, a preliminary metal wiring 128P′ may be formed in the peripheral circuit region PERI.

The upper surface of the upper plug 128C may be at the same level as the upper surface of the capping layer 124 . The protective spacer 123 may cover the upper plug 128C. The capping layer 124 may cover the upper plug 128C. The upper plug 128C may have the same shape as the upper plug 29 of FIG. 4G . The upper plug 128C may partially overlap the bit line hardmask 112C. The upper plug 128C may not overlap the capping layer 124 . The bottom surface of the upper plug 128C may be at a higher level than the top surface of the bit line hard mask 112C. Since the upper plug 128C is formed on the celohmic contact layer 127C, the upper plug 128C having a large area may be formed. Accordingly, the contact defect of the contact can be improved.

As shown in FIG. 7R , the metal wiring 128P may be formed by etching the preliminary metal wiring 128P'. In order to form the metal wiring 128P, the metal wiring mask 130 may be formed on the preliminary metal wiring 128P'. The metal wiring mask 130 may include a photoresist pattern. The metal wiring mask 130 may cover the memory cell region CELL. Accordingly, the memory cell region CELL may be protected while the metal wiring 128P is formed. As the metal wiring 128P is formed, the capping layer 124 of the peripheral circuit region PERI may be exposed.

As shown in FIG. 7S , a pattern insulating layer 132 may be formed on the upper plug 128C, the capping layer 124 and the metal wiring 128P. A memory element 133 electrically connected to the upper plug 128C may be formed on the upper plug 128C. The memory element 133 may be implemented in various forms. The memory element 133 may include a conductive layer. The memory element 133 may be a capacitor. Accordingly, the memory element 133 may include a storage node in contact with the top plug 128C. The storage node may be in the form of a cylinder or a pillar.

According to the above-described embodiment, process defects can be reduced by forming the lower plug 120 including the extension portion 120T. In addition, it is possible to secure the mass productivity of the semiconductor device by simplifying the process. In addition, the protective spacer 123 may prevent the plug pattern 120B of the narrow etched region E1 from being removed by narrowing the open area of the narrow etched region E1 . Accordingly, it is possible to prevent a contact failure with the neighboring memory cell active region 104C. In addition, by forming the cell ohmic contact layer 127C at a level higher than the upper surface of the bit line structure BL, the formation of the cell ohmic contact layer 127C may be facilitated. Since the cell ohmic contact layer 127C having a large area can be formed, contact resistance can be improved. Since the upper plug 128C having a large area can be formed, contact failure of the contact can be improved.

The present invention described above is not limited by the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible without departing from the technical spirit of the present invention. It will be clear to those who have the knowledge of

11: substrate 12: isolation trench
13: device isolation layer 14: active region
16: interlayer insulating layer 16: bit line contact plug
17: barrier metal layer 18: bit line
19: bit line hard mask 24: lower plug
24M: pillar part 24T: extension part
25: capping hole 26: protective spacer
27: gap fill layer 28: ohmic contact layer
29: upper plug 30: etch stop layer
31: memory element

Claims (48)

conductive line patterns on the substrate;
a lower plug including a pillar part positioned between the conductive line patterns and an extension part extending from the pillar part and overlapping any one of the conductive line patterns;
a capping layer covering a sidewall of the lower plug; and
a protective spacer positioned between the lower plug and the capping layer;
semiconductor device comprising
According to claim 1,
The protective spacer is
The shape surrounding the lower plug (Surronding-Shape)
semiconductor device
According to claim 1,
The protective spacer is
Fully-covering the sidewall of the extension,
Partially covering the sidewall of the pillar part
semiconductor device
According to claim 1,
The protective spacer includes silicon nitride.
semiconductor device
According to claim 1,
The upper surface of the lower plug is
a level lower than the upper surface of the capping layer
semiconductor device
According to claim 1,
located on the lower plug,
An upper plug containing a material different from that of the lower plug
A semiconductor device further comprising
7. The method of claim 6,
The lower plug includes polysilicon,
The upper plug includes a metal-containing material
semiconductor device
7. The method of claim 6,
The upper surface of the upper plug is
at the same level as the upper surface of the capping layer
semiconductor device
7. The method of claim 6,
The thickness of the upper plug is
smaller than the thickness of the extension
semiconductor device
7. The method of claim 6,
The protective spacer covers the upper plug.
semiconductor device
7. The method of claim 6,
The capping layer covers the upper plug.
semiconductor device
7. The method of claim 6,
An ohmic contact layer positioned between the lower plug and the upper plug
A semiconductor device further comprising
7. The method of claim 6,
a conductive layer positioned on the upper plug
A semiconductor device further comprising
bit line structures on the substrate;
lower plugs including a pillar portion positioned between the bit line structures and an extension portion extending from the pillar portion to overlap any one of the bit line structures;
a capping layer positioned between the lower plugs;
protective spacers positioned between the capping layer and the lower plugs and having a shape (Surrounding-Shape) surrounding the lower plugs, respectively;
upper plugs respectively positioned on the lower plugs; and
Capacitors respectively positioned on the upper plugs
semiconductor device comprising
15. The method of claim 14,
The protective spacers are each
Fully-covering the sidewall of the extension,
Partially covering the sidewall of the pillar part
semiconductor device
15. The method of claim 14,
The protective spacers include silicon nitride.
semiconductor device
15. The method of claim 14,
A portion of the capping layer is in contact with the substrate
semiconductor device
15. The method of claim 14,
The upper surface of each of the lower plugs is
a level lower than the upper surface of the capping layer
semiconductor device
15. The method of claim 14,
The upper surface of each of the upper plugs is
at the same level as the upper surface of the capping layer
semiconductor device
15. The method of claim 14,
The lower plugs include polysilicon,
The upper plugs include a metal-containing material.
semiconductor device
15. The method of claim 14,
The thickness of each of the upper plugs is
smaller than the thickness of each of the extensions of the lower plugs
semiconductor device

15. The method of claim 14,
The protective spacers are
each covering the upper plugs
semiconductor device
15. The method of claim 14,
The capping layer is
covering the upper plugs
semiconductor device
15. The method of claim 14,
An ohmic contact layer positioned between the lower plugs and the upper plugs, respectively
A semiconductor device further comprising
forming conductive line patterns on a substrate;
forming a plug pattern positioned between the conductive line patterns to overlap any one of the conductive line patterns;
forming a protective spacer on a sidewall of the plug pattern;
forming a capping layer between the plug patterns; and
forming a lower plug including a pillar portion positioned between the conductive line patterns and an extension portion extending from the pillar portion and overlapping any one of the conductive line patterns by recessing the plug pattern;
A method of manufacturing a semiconductor device comprising

26. The method of claim 25,
The protective spacer is
The shape surrounding the lower plug (Surronding-Shape)
Semiconductor device manufacturing method
26. The method of claim 25,
The protective spacer is
Fully-covering the sidewall of the extension,
Partially covering the sidewall of the pillar part
Semiconductor device manufacturing method
26. The method of claim 25,
The protective spacer is
containing silicon nitride
Semiconductor device manufacturing method
26. The method of claim 25,
The upper surface of the lower plug is
a level lower than the upper surface of the capping layer
Semiconductor device manufacturing method

26. The method of claim 25,
forming an upper plug on the lower plug
further comprising,
The upper plug includes a material different from that of the lower plug.
Semiconductor device manufacturing method

31. The method of claim 30,
The lower plug includes polysilicon,
The upper plug includes a metal-containing material
Semiconductor device manufacturing method
31. The method of claim 30,
The upper surface of the upper plug is
at the same level as the upper surface of the capping layer
Semiconductor device manufacturing method
31. The method of claim 30,
The thickness of the upper plug is
smaller than the thickness of the extension
Semiconductor device manufacturing method
31. The method of claim 30,
The protective spacer is
covering the upper plug
Semiconductor device manufacturing method
31. The method of claim 30,
The capping layer is
covering the upper plug
Semiconductor device manufacturing method
31. The method of claim 30,
Before the step of forming the upper plug,
forming an ohmic contact layer on the lower plug
A method of manufacturing a semiconductor device further comprising
31. The method of claim 30,
forming a conductive layer on the upper plug
A method of manufacturing a semiconductor device further comprising
forming a substrate including bit line structures;
forming plug patterns positioned between the bit line structures to overlap any one of the bit line structures;
forming protective spacers surrounding the plug patterns;
forming a capping layer between the plug patterns;
forming lower plugs including a pillar portion positioned between the bit line structures and an extension portion extending from the pillar portion and overlapping any one of the bit line structures by recessing the plug pattern;
forming upper plugs on the lower plugs, respectively; and
forming capacitors on the upper plugs, respectively
A method of manufacturing a semiconductor device comprising
39. The method of claim 38,
The protective spacers are each
Fully-covering the sidewall of the extension,
Partially covering the sidewall of the pillar part
Semiconductor device manufacturing method
39. The method of claim 38,
The protective spacers are
containing silicon nitride
Semiconductor device manufacturing method
39. The method of claim 38,
A portion of the capping layer is
in contact with the substrate
Semiconductor device manufacturing method
39. The method of claim 38,
The upper surface of each of the lower plugs is
a level lower than the upper surface of the capping layer
Semiconductor device manufacturing method
39. The method of claim 38,
The upper surface of each of the upper plugs is
at the same level as the upper surface of the capping layer
Semiconductor device manufacturing method
39. The method of claim 38,
The lower plugs include polysilicon,
The upper plugs include a metal-containing material.
Semiconductor device manufacturing method
39. The method of claim 38,
The thickness of each of the upper plugs is
smaller than the thickness of each of the extensions
Semiconductor device manufacturing method
39. The method of claim 38,
The protective spacers are each
covering the upper plugs
Semiconductor device manufacturing method
39. The method of claim 38,
The capping layer is
covering the upper plugs
Semiconductor device manufacturing method
39. The method of claim 38,
Before the step of forming the upper plugs,
forming an ohmic contact layer on each of the lower plugs;
A semiconductor device further comprising

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