KR20210086282A - Display apparatus - Google Patents

Abstract

According to an embodiment of the present specification, a display device includes: a demultiplexing circuit unit which performs time-division of a data signal output from a data driver into first to third sub-horizontal periods and distributes them to first to third data lines. The demultiplexing circuit unit includes: an input unit for outputting first to third data selection signals to first to third control lines in response to first to third time division control signals and first to third auxiliary signals; and a switching unit which performs time-division of the data signal in response to three data selection signals and distributing them to the first to third data lines, wherein a period of the first and third time division control signals is longer than that of the second time division control signal. Accordingly, it is possible to reduce the number of rising and falling voltages of a control line and reduce power consumption.

Description

display device {DISPLAY APPARATUS}

This specification relates to a display device.

A display device is used to display a screen on various types of devices, such as a notebook computer, a tablet computer, a smart phone, a portable display device, and a portable information device, in addition to a television or a monitor.

As process technology and driving circuit technology of display devices are developed, pixels per inch (PPI) are continuously increasing to realize high-resolution display devices.

Such a display device includes a display panel, a data driver for driving the display panel, a gate driver, and a timing controller for controlling the drivers.

The display panel includes a plurality of sub-pixels having thin film transistors provided for each pixel area defined by each of a plurality of data lines and a plurality of gate lines, wherein at least three adjacent sub-pixels display one image. constitute a unit pixel. The data driver supplies a data signal to the data lines, and the gate driver supplies a scan signal to the gate lines.

In a conventional display device, a data driver is mounted on a flexible circuit film in order to reduce a lower bezel area, and the number of channels of the data driver is reduced through data time division driving using demultiplexing circuits.

Demultiplexing circuits control a switching element disposed on a data line through a control line to supply a data signal to the data line, but driving the demultiplexing circuits has a problem in that a lot of power is consumed.

In addition, in order to stably supply the data signal to the data line, the voltage of the control line must be stably maintained, but there is a problem in that stable control of the voltage of the control line has not been performed yet.

The present specification is intended to solve the problems of the prior art as described above, and includes a demultiplexing circuit unit that provides a data signal provided from an output channel of a data driver to each of three data lines, and the demultiplexing circuit unit includes three data signals. It is a technical task to provide a display device capable of reducing the number of rising and falling voltages of a control line and reducing power consumption by changing the order provided to each of the data lines by changing two horizontal periods of a scan signal to one cycle do it with

The present specification changes the order in which the switching elements of each of the first to third demultiplexing circuits are turned on by changing two horizontal periods of the scan signal to one period, so that RGB is sequentially converted into data lines in the first one horizontal period within one period. A technical task is to provide a display device capable of implementing RGB-BGR rendering and reducing power consumption by sequentially supplying BGR to data lines in the second horizontal period within one cycle.

In the present specification, the second demultiplexing circuit among the first to third demultiplexing circuits uses a longer signal used during pre-charging to reduce the number of rises and falls, thereby reducing power consumption when implementing RGB-BGR rendering. It is a technical problem to provide a display device capable of reducing the

The problems to be solved according to the example of the present specification are not limited to the above-mentioned problems, and other problems not mentioned are from the description below to those of ordinary skill in the art to which the technical idea of the present specification belongs. can be clearly understood.

A display device according to an embodiment of the present specification for achieving the above technical problem is a demultiplexing circuit unit for time-dividing a data signal output from a data driver into first to third sub-horizontal periods and distributing it to first to third data lines. an input unit for outputting first to third data selection signals to first to third control lines in response to first to third time division control signals and first to third auxiliary signals; and 3 and a switching unit that time-divisions data in response to data selection signals and distributes the data to first to third data lines, wherein a period of the first and third time-division control signals is longer than a period of the second time-division control signal.

Specific details according to various examples of the present specification other than the means for solving the above-mentioned problems are included in the description and drawings below.

A display device according to an example of the present specification includes a demultiplexing circuit unit that provides a data signal provided from an output channel of a data driver to each of three data lines, and the demultiplexing circuit unit provides a data signal to each of the three data lines By changing the order in which the two horizontal periods of the scan signal are one period, the number of rises and falls of the voltage of the control line can be reduced and power consumption can be reduced.

The display device according to an example of the present specification changes the order in which the switching elements of each of the first to third demultiplexing circuits are turned on by changing two horizontal periods of a scan signal to one period, so that in the first one horizontal period within one period, RGB-BGR rendering can be realized and power consumption can be reduced by sequentially supplying RGB to data lines and sequentially supplying BGR to data lines in the second horizontal period within one period.

Since the contents of the problems to be solved, the problem solving means, and the effects mentioned above do not specify the essential characteristics of the claims, the scope of the claims is not limited by the matters described in the contents of the specification.

The accompanying drawings are provided to help understanding of the present embodiment, and provide embodiments together with detailed description. However, the technical features of the present embodiment are not limited to specific drawings, and features disclosed in each drawing may be combined with each other to constitute a new embodiment.
1 is a diagram illustrating a configuration of an example of a display device according to an embodiment of the present specification.
FIG. 2 is an exemplary diagram schematically illustrating an example in which the demultiplexing circuit unit of FIG. 1 drives three data lines from one source channel.
FIG. 3 is a circuit diagram illustrating the configuration of a first demultiplexing circuit of the demultiplexing circuit unit of FIG. 2 .
4 is a diagram illustrating waveforms of signals supplied to the first demultiplexing circuit of FIG. 3 , a voltage of a charging node, and a voltage of a control line.
FIG. 5 is a circuit diagram showing the configuration of a second demultiplexing circuit of the demultiplexing circuit unit of FIG. 2 .
FIG. 6 is a diagram illustrating waveforms of signals supplied to the second demultiplexing circuit of FIG. 5, a voltage of a charging node, and a voltage of a control line;
FIG. 7 is a circuit diagram showing the configuration of a third demultiplexing circuit of the demultiplexing circuit unit of FIG. 2 .
8 is a diagram illustrating waveforms of signals supplied to the first demultiplexing circuit of FIG. 7 , a voltage of a charging node, and a voltage of a control line.
9 is a circuit diagram illustrating a configuration including first to third demultiplexing in the demultiplexing circuit of FIG. 2 .
FIG. 10 is a diagram illustrating waveforms of signals supplied to the demultiplexing circuit unit of FIG. 9 , a voltage of a charging node, and a voltage of a control line.

Advantages and features of the present specification and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present specification to be complete, and in the technical field to which the technical spirit of the present specification belongs It is provided to inform those of ordinary skill in the scope of the technical idea, and the technical idea of the present specification is only defined by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining an example of the present specification are exemplary, the present specification is not limited to the matters shown in the drawings. Like elements may be referred to by the same reference numerals throughout the specification. In addition, in describing an example of the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless the expression 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise. In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless the expression "

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present specification.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It may mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present specification may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently with respect to each other or may be implemented together in a related relationship. may be

In adding reference numerals to the components of each drawing describing the embodiments of the present specification, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings.

Hereinafter, a display device of the present specification will be described with reference to the accompanying drawings and examples.

1 is a diagram illustrating a configuration of an example of a display device according to an embodiment of the present specification.

The display device of the present specification includes a liquid crystal display device (LCD), an organic light emitting display (OLED), an electrophoretic display (EPD), and a plasma display panel (PDP). device, PDP), Field Emission Display device (FED), Electro luminescence Display device (ELD), Electro-Wetting Display (EWD), etc. display devices capable of realizing color can be

Referring to FIG. 1 , the display device may include a display panel 110 , a data driver 120 , a gate driver 130 , and a demultiplexing circuit unit 140 .

The display panel 110 includes a plurality of sub-pixels provided in a pixel area defined by the exchange of the plurality of gate lines GL1 to GLm and the data lines DL1 to DLn and having thin film transistors. One sub-pixel may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and at least three adjacent sub-pixels constitute a unit pixel UP displaying one image.

The data driver 120 may include a plurality of circuit films 121 , a plurality of driving integrated circuits 123 , a printed circuit board 125 , and a timing controller 127 .

Each of the plurality of circuit films 121 may be attached to the pad part of the display panel 110 and the printed circuit board 125 . Accordingly, the plurality of circuit films 121 may be used as a physical connection structure between the display panel 110 and the printed circuit board 125 .

For example, the input terminal provided on one side of each of the plurality of circuit films 121 is attached to the printed circuit board 125 by a film attaching process, and the output terminal provided on the other side of the plurality of circuit films 121 is attached to the film. It may be attached to the pad portion of the display panel 110 through a process.

Each of the plurality of driving integrated circuits 123 may be individually mounted on each of the plurality of circuit films 121 . Each of the plurality of driving integrated circuits 123 may receive image data and a data control signal provided from the timing controller 127 , and convert the image data into an analog data signal for each pixel according to the data control signal and output it. have.

The printed circuit board 125 may support the timing controller 127 and transmit signals and power between components of the data driver 120 .

The timing controller 127 is mounted and supported on the printed circuit board 125 , and may receive image data and a timing synchronization signal provided from the display driving system through a user connector provided on the printed circuit board 125 .

For example, a display driving system is an electric device that has a display device and outputs an image through the display device, for example, a TV (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, and a personal computer. (PC), a home theater system, a phone system, and the like.

The timing controller 127 generates a data control signal and a gate control signal, respectively, based on the timing synchronization signal, controls the driving timing of each of the driving integrated circuits 123 through the data control signal, and a gate driver through the gate control signal The driving timing of 130 may be controlled.

In the present embodiment, the data driver 120 is attached to the display panel 110 via the plurality of circuit films 121 , but may be mounted on the display panel 110 . In addition, although it is exemplified that the timing controller 127 is a configuration of the data driver 120 in this embodiment, it may be provided separately from the data driver 120 .

The gate driver 130 is connected to each of the gate lines GL1 to GLm, and generates a scan pulse according to a gate control signal provided from the timing controller 127 and sequentially supplies the scan pulses to each of the gate lines GL1 to GLm. do.

In the present exemplary embodiment, one gate driver 130 is disposed at one edge of the display panel 110 , but gate drivers may be disposed at both edges of the display panel 110 . According to an example, the gate driver 130 may include m stages (not shown) connected to each of the m gate lines GL1 to GLm.

The demultiplexing circuit unit 140 may sequentially supply the data signal supplied from the data driver 120 to at least three data lines DL.

The demultiplexing circuit unit 140 is connected to each source channel of the driving integrated circuit 123 and is electrically connected to each of the n data lines DL1 to DLn provided in the display panel 110 of the display panel 110 . It may be disposed on one side.

The demultiplexing circuit unit 140 may include at least one demultiplexing circuit that sequentially supplies the data signal supplied from the data driver 120 to at least three data lines.

The demultiplexing circuit unit 140 sequentially distributes the data signals input from the driving integrated circuit 123 for each of a plurality of sub-horizontal periods SH of one horizontal period 1H to the n data lines DL1 to DLn. can

Although the embodiments herein are described on the assumption that the switching unit is turned on when a high potential voltage is supplied, the switching unit may be turned on when a low potential voltage is supplied, and a high voltage that turns on the switching unit The upper voltage or the lower potential voltage is a voltage for supplying a data signal to a data line and may be expressed as a 'data supply voltage' or a 'data supply signal'.

FIG. 2 is an exemplary diagram schematically illustrating an example in which the demultiplexing circuit unit of FIG. 1 drives three data lines from one source channel.

Referring to FIG. 2 , since the demultiplexing circuit unit 140 is connected to three data lines DL1 to DL3 through three control lines CL_A, CL_B, and CL_C, the display device displays n/3 (n is data). It is possible to implement a high-resolution image while having the number of sources SH (total number of lines).

The demultiplexing circuit unit 140 time-divisions the data signal DS output from the source channel SH of the data driver and distributes it to the first to third data lines DL1 to DL3, and performs switching with the input unit I-IC. Includes sub (S-IC).

The input unit I-IC is connected to the first to third control lines CL_A to CL_A in response to the first to third time division control signals ASW1, BSW1, CSW1 and the first to third auxiliary signals ASW2, BSW2, and CSW2. The first to third data selection signals are outputted to CL_C, and the switching unit S-IC time-divisions the data signals in response to the three data selection signals from the input unit I-IC to three data lines DL1. ~ DL3).

Here, the first to third data selection signals may be voltages, and outputting the first to third data selection signals to the first to third control lines CL_A to CL_C means corresponding to the switching S-IC. It may mean supplying a voltage for turning on the first to third switching elements.

The input unit I-IC is connected to the first to third control lines CL_A to CL_A in response to the first to third time division control signals ASW1, BSW1, CSW1 and the first to third auxiliary signals ASW2, BSW2, and CSW2. CL_C) is charged (pre-charging), the voltage charged in the first to third control lines (CL_A to CL_C) is bootstrapped, or the first to third control lines are (CL_A to CL_C) Dis-charging the voltage charged to the

The input unit I-IC includes first to third demultiplexing circuits 140A, 140B, and 140C respectively connected to the first to third control lines CL_A to CL_C, and the respective demultiplexing circuits 140A and 140B. , 140C) performs a pre-charging operation, a bootstrapping operation, and a dis-charging operation for each of the control lines CL_A to CL_C.

The switching unit S_IC time-divisions the data signal DS in response to the data selection signal from the input unit I-IC and supplies it to the three data lines DL1 to DL3.

The switching unit S-IC includes first to third switching elements S1 respectively connected to the first to third demultiplexing circuits 140A, 140B, and 140C through the first to third control lines CL_A to CL_C. , S2, S3).

The first switching element S1 is disposed on the first data line DL1 and is turned on based on the first control voltage VA_A charged in the first control line CL_A for a first sub-horizontal period. The data signal DS1 is supplied to the first data line DL1.

The second switching element S2 is disposed on the second data line DL2 and is turned on based on the second voltage VA_B charged in the second control line CL_B to obtain data for the second sub-horizontal period. The signal DS2 is supplied to the second data line DL2.

The third switching element S3 is disposed on the third data line DL3 and is turned on based on the third voltage VA_C charged in the third control line CL_C to provide data for the third sub-horizontal period. The signal DS3 is supplied to the third data line DL3.

As will be described later, the period of the first and third time division control signals ASW1 and CSW1 corresponds to 6 sub-horizontal periods, and the period of the second time division control signal BSW1 corresponds to 3 sub-horizontal periods. and a period of the third time division control signals ASW1 and CSW1 is two longer than a period of the second time division control signal BSW1.

In addition, the turn-on periods T1 and T3 of the first and third time division control signals ASW1 and CSW1 are longer than the turn-on periods T2 of the second time division control signal BSW1, and the first and third The turn-on periods T4 and T6 of the auxiliary signals ASW2 and CSW2 are longer than the turn-on periods T5 of the second auxiliary signal BSW2.

In addition, the turn-on periods T1 and T3 of the first and third time division control signals ASW1 and CSW1 and the turn-on periods T4 and T6 of the first and third auxiliary signals ASW2 and CSW2 are It is maintained for 2 sub-horizontal periods, and the turn-on period T2 of the second time division control signal BSW1 and the turn-on period T5 of the second auxiliary signal BSW2 are maintained for 1 sub-horizontal period.

In this case, the data signal output in the turn-on period T1 during the 2 sub-horizontal period of the first time division control signal ASW1 includes grayscale information of red light or blue light, and the second time division control signal BSW1 The data signal output in the turn-on period T2 for one sub-horizontal period includes gray level information of green light, and in the turn-on period T3 for the second sub-horizontal period of the third time division control signal CSW1 The output data signal includes grayscale information of blue light or red light, thereby realizing RGB-BGR rendering.

That is, the demultiplexing circuit unit 140 implements RGB during the first to third sub-horizontal periods of the odd-numbered first horizontal period, and implements the BGR during the first to third sub-horizontal periods of the even-numbered first horizontal period.

The first auxiliary signal ASW2 overlaps the first time division control signal ASW1 , the second auxiliary signal BSW2 overlaps the second time division control signal BSW1 , and the third auxiliary signal CSW2 It overlaps with the time division control signal CSW1.

In this case, the first transition time of the first auxiliary signal ASW2 is later than the first transition time of the first time division control signal ASW1, and the second transition time of the second auxiliary signal BSW2 is the first time division control signal ( It is the same as the second transition time of ASW1).

The first transition time of the second auxiliary signal BSW2 is later than the first transition time of the second time division control signal BSW1 , and the second transition time of the second auxiliary signal BSW2 is the second time division control signal BSW1 . It is the same as the second transition point of

The first transition time of the third auxiliary signal CSW2 is later than the first transition time of the third time division control signal CSW1 , and the second transition time of the third auxiliary signal CSW2 is the third time division control signal CSW1 . It is the same as the second transition point of

In the present specification, the first transition time may correspond to a rising edge and the second transition time may correspond to a falling edge, but is not limited thereto.

In order to distinguish voltages used below, the voltage VA_A charged in the first control line CL_A is the first control voltage, and the voltage VA_B charged in the second control line CL_B is the second control voltage. , the voltage VA_C charged in the third control line CL_C is the third control voltage, the voltage VB_A charged in the first charging node CN_A is the first charging voltage, and the second charging node CN_B ) may be expressed as a second charging voltage, and a voltage VB_C charged at the third charging node CN_C may be expressed as a third charging voltage.

3 is a circuit diagram showing the configuration of the first demultiplexing circuit of the demultiplexing circuit unit of FIG. 2, and FIG. 4 is a signal supplied to the first demultiplexing circuit of FIG. 3, the voltage of the charging node, and the voltage of the control line. It is a diagram showing a waveform.

3 and 4, the first demultiplexing circuit 140A responds to the first to third time division control signals ASW1, BSW1, and CSW1 and the first and third auxiliary signals ASW2 and CSW2. Pre-charging the first control voltage VA_A in the first control line CL_A, bootstrapping the first control voltage VA_A charged in the first control line CL_A, or Dis-charging the first control voltage VA_A charged in the first control line CL_A, and controlling the first switching element S1 through the voltage control of the first control line CL_A to control the first sub The horizontal period data signal DS1 is supplied to the first data line DL1.

The first data signal DS1 supplied to the first data line DL1 through the first switching element S1 under the control of the first demultiplexing circuit 140A may include grayscale information of red light or blue light. have. The first demultiplexing circuit 140A may include a first charging control unit 141A, a first boosting unit 143A, and a first discharging unit 145A.

The first charging control unit 141A of the first demultiplexing circuit 140A responds to the first and second time division control signals ASW1 and BSW1 and the first and third auxiliary signals ASW2 and CSW2 to the first control line The voltage (VA_A) is charged to (CL_A).

The first charging control unit 141A may include a first transistor M1 , a first charging transistor M11 , and a first discharging transistor M12 .

The first transistor M1 is turned on based on the voltage VB_A of the first charging node CN_A controlled by the first auxiliary signal ASW2 and the third auxiliary signal CSW2 to obtain a first time division control signal (ASW1) may be provided as the first control line CL_A.

The gate electrode of the first transistor M1 is connected to the first charging node CN_A, the drain electrode of the first transistor M2 receives the first time division control signal ASW1, and The source electrode may be connected to the first control line CL_A.

Accordingly, when the voltage VB_A of the first charging node CN_A and the first time division control signal ASW1 are high potential voltages, the first transistor M1 is turned on and the voltage of the first control line CL_A is turned on. (VA_A) can also maintain a high potential voltage.

The first charging transistor M11 is turned on based on the third auxiliary signal CSW2 overlapping the third time division control signal CSW1 to supply the third auxiliary signal CSW2 to the first charging node CN_A. can

The gate electrode and the drain electrode of the first charging transistor M11 may receive the third auxiliary signal CSW2 , and the source electrode of the first charging transistor M11 may be connected to the first charging node CN_A.

Accordingly, the first charging transistor M11 is turned on as the third auxiliary signal CSW2 of the high potential voltage is supplied, and supplies the third auxiliary signal CSW2 to the first charging node CN_A, 1 Charging node CN_A can be charged.

As such, before the first time division control signal ASW1 of the high potential voltage is supplied to the drain electrode of the first transistor M1 , the first charging transistor M11 is turned on by the third auxiliary signal CSW2 . Thus, by charging the first charging node CN_A with a high potential voltage, the charging of the first control line CL_A may be strengthened to stably maintain the output of the first demultiplexing circuit 140A and improve the pixel charging rate. .

The first discharge transistor M12 receives the second time division control signal BSW1 and the first auxiliary signal ASW2, is turned on based on the second auxiliary signal ASW2, and is charged in the charging node CN_A. Discharge the voltage (VB_A).

The gate electrode of the first discharge transistor M12 receives the first auxiliary signal ASW2 , the drain electrode of the first discharge transistor M12 is connected to the first charging node CN_A, and the first discharge transistor M12 ) is supplied with the second time division control signal BSW1.

At this time, the turn-on period T2 of the second time division control signal BSW1 and the turn-on period T4 of the first auxiliary signal ASW2 do not overlap, and the first transition of the first auxiliary signal ASW2 Since the second time division control signal BSW1 has a low potential voltage at a time point, when the first auxiliary signal ASW2 having a high potential voltage is supplied, the first discharging transistor M12 is turned on and is applied to the charging node CN_A. The charged voltage VB_A is discharged.

As described above, the voltage VB_A of the first charging node CN_A is charged by the first charging transistor M11 turned on by the third auxiliary signal CSW2, and the first auxiliary signal ASW2 is discharged by the first discharge transistor M12 turned on by

When the voltage VB_A of the first charging node CN_A is at a high potential, the first time division control signal ASW1 of the high potential voltage is applied to the first control line CL_A through the turned-on first transistor M1. When supplied, the voltage VB_A of the first charging node CN_A may additionally increase by the gate-source capacitance of the first transistor M1 .

When the voltage VB_A of the first charging node CN_A increases, the first control line CL_A is initially charged (pre-charging), so that the charging of the first control line CL_A is strengthened and the first demultiplexing circuit The output of (140A) can be stably maintained.

Accordingly, the first demultiplexing circuit 140A controls the voltage VB_A of the first charging node CN_A through the first charging transistor M11 and the first discharging transistor M12, so that the first and second transistors Even when the (M1, M2) and the second discharging transistor M21 are deteriorated, the charging characteristic of the first control line CL_A may be improved and generation of a leakage current may be prevented. As a result, the first demultiplexing circuit 140A stably maintains the output of the first switching element S1 that is turned on based on the voltage VA_A of the first control line CL_A, so that the luminance of the display panel is maintained. It is possible to prevent deterioration and realize a high-resolution image of the display panel.

The first booster 143A of the first demultiplexing circuit 140A bootstraps the voltage VA_A charged in the first control line CL_A based on the first auxiliary signal ASW2, and the first capacitor ( C1) may be composed.

One end of the first capacitor C1 receives the first auxiliary signal ASW2 , and the other end of the first capacitor C1 is connected to the first control line CL_A.

The time point at which the first auxiliary signal ASW2 of the high potential voltage is supplied to one end of the first capacitor C1 may correspond to between the first transition time point and the second transition time point of the first time division control signal ASW1 .

As such, the first booster 143A bootstraps the first voltage VA_A of the first control line CL_A maintained by the first charge controller 141A using the first auxiliary signal ASW2. , the input voltage of the first switching element S1 may be stably maintained by increasing the voltage to a higher voltage than the voltage of the first time division control signal ASW1 .

The first discharge unit 145A of the first demultiplexing circuit 140A discharges the first voltage VA_A charged in the first control line CL_A, and may be composed of a second transistor M2, By additionally discharging the first voltage VA_A charged in the first control line CL_A by further including the second discharging transistor M21 , the discharge characteristic may be improved and the occurrence of leakage current may be prevented.

The second transistor M2 is turned on based on the second time division control signal BSW1 to discharge the first voltage VA_A charged in the first control line CL_A, and the second discharge transistor M21 ) may be turned on based on the third time division control signal CSW1 to additionally discharge the first voltage VA_A charged in the first control line CL_A.

The gate electrode of the second transistor M2 receives the second time division control signal BSW1 , the drain electrode of the second transistor M2 is connected to the first control line CL_A, and the The source electrode receives the first time division control signal ASW1.

The gate electrode of the second discharge transistor M21 is supplied with the third time division control signal CSW1, the drain electrode of the second discharge transistor M21 is connected to the first control line CL_A, and the second discharge transistor ( The source electrode of M21 is supplied with the first time division control signal ASW1.

The drain electrode of the second transistor M2 and the drain electrode of the second discharge transistor M21 are commonly connected to the first control line CL_A, and the source electrode of the second transistor M2 and the second discharge transistor M21 are connected in common. ), the source electrode receives the first time division control signal ASW1 in common.

The second transistor M2 is turned on when the second time division control signal BSW1 of the high potential voltage is supplied to the gate electrode while the first time division control signal ASW1 of the low potential voltage is supplied to the source electrode. to discharge the first voltage VA_A charged in the first control line CL_A.

The second discharge transistor M21 is turned on when the third time-division control signal CSW1 of the high potential voltage is supplied to the gate electrode while the first time-division control signal ASW1 of the low potential voltage is supplied to the source electrode. It is turned on to additionally discharge the first voltage VA_A charged in the first control line CL_A.

5 is a circuit diagram showing the configuration of the second demultiplexing circuit of the demultiplexing circuit unit of FIG. 2 , and FIG. 6 is a signal supplied to the second demultiplexing circuit of FIG. 5 , the voltage of the charging node, and the voltage of the control line. It is a diagram showing a waveform.

5 and 6, the second demultiplexing circuit 140B responds to first to third time division control signals ASW1, BSW1, CSW1 and first to third auxiliary signals ASW2, BSW2, and CSW2. , pre-charging the voltage VA_B in the second control line CL_B, bootstrapong the voltage VA_B charged in the second control line CL_B, or the second control line ( Dis-charging the voltage VA_B charged to CL_B, and controlling the second switching element S1 through the voltage control of the second control line CL_B to control the second sub-horizontal period data signal DS2 ) is supplied to the second data line DL2.

The second data signal DS2 supplied to the second data line DL2 through the second switching element S2 under the control of the second demultiplexing circuit 140B may include grayscale information of green light.

The second demultiplexing circuit 140B of FIG. 4 further includes a second charging transistor M13 in the configuration of the first demultiplexing circuit of FIG. 3, and the received signals are different, for the same configuration as the above-described configuration. Descriptions may be omitted or briefly described.

The second demultiplexing circuit 140B may include a second charging control unit 141B, a second boosting unit 143B, and a second discharging unit 145B.

The second charging control unit 141B is configured to apply the voltage VA_B to the second control line CL_B in response to the second and third time division control signals BSW1 and CSW1 and the first to third auxiliary signals ASW2, BSW2, and CSW2. ) is charged.

The second charging control unit 141B may include a first transistor M1 , a first charging transistor M11 , a second charging transistor M13 , and a first discharging transistor M12 .

As will be described later, the source electrode of the first charging transistor M11 and the source electrode of the second charging transistor M13 are commonly connected to the second charging node CN_B, so that the first charging transistor M11 and the second The charging transistor M13 is connected in parallel to the second charging node CN_B. Accordingly, when one of the first and second charging transistors M11 and M13 is turned on, the second charging node CN_B is converted to a high potential voltage by the first auxiliary signal ASW2 or the third auxiliary signal CSW2. can be charged.

The first transistor M1 of the second charging control unit 141B is turned based on the voltage VB_B of the second charging node CN_B controlled by the first to third auxiliary signals ASW2, BSW2, and CSW2; may be turned on to provide the second time division control signal BSW1 to the second control line CL_B.

Specifically, the gate electrode of the first transistor M1 is connected to the second charging node CN_B, the drain electrode of the first transistor M1 receives the second time division control signal BSW1, and the first transistor M1 ( The source electrode of M1 may be connected to the second control line CL_B.

Accordingly, when the voltage VB_B of the second charging node CN_B and the second time-division control signal BSW1 are high potential voltages, the first transistor M1 is turned on and the second control line CL_B The voltage VA_B may also maintain a high potential voltage.

The first charging transistor M11 of the second charging control unit 141B is turned on based on the first auxiliary signal ASW2 overlapping the first time division control signal ASW1 to generate the first auxiliary signal ASW2. 2 can be supplied to the charging node (CN_B).

Specifically, the gate electrode and the drain electrode of the first charging transistor M11 may receive the first auxiliary signal ASW2 , and the source electrode of the first charging transistor M1 may be connected to the second charging node CN_B. .

Accordingly, the first charging transistor M11 is turned on as the first auxiliary signal ASW2 of the high potential voltage is supplied, and supplies the first auxiliary signal ASW2 to the second charging node CN_B, 2 The charging node CN_B can be charged.

Before the second time division control signal BSW1 of the high potential voltage is supplied to the drain electrode of the first transistor M1 (before the first transition point of the second time division control signal), the first auxiliary signal ASW2 of the high potential voltage ) is supplied to the first charging transistor M11, the first charging transistor M11 is turned on to charge the second charging node CN_B to a high potential voltage, thereby charging the second control line CL_B. By strengthening it, the output of the second demultiplexing circuit 140B may be stably maintained and the pixel filling rate may be improved.

The second charging transistor M13 of the second charging control unit 141B is turned on based on the third auxiliary signal CSW2 overlapping the third time division control signal CSW1 to generate the third auxiliary signal CSW2. 2 can be supplied to the charging node (CN_B).

Specifically, the gate electrode and the drain electrode of the second charging transistor M13 may receive the third auxiliary signal CSW2 , and the source electrode of the second charging transistor M13 may be connected to the second charging node CN_B. .

Accordingly, the second charging transistor M13 is turned on as the third auxiliary signal CSW2 of the high potential voltage is supplied to supply the third auxiliary signal CSW2 to the second charging node CN_B for the second charging. The node CN_B can be charged.

Before the second time division control signal BSW1 of the high potential voltage is supplied to the drain electrode of the first transistor M1 (before the first transition point of the second time division control signal), the third auxiliary signal CSW2 of the high potential voltage ) is supplied to the second charging transistor M13, the second charging transistor M13 is turned on to charge the second charging node CN_B to a high potential voltage, thereby charging the second control line CL_B. By strengthening it, the output of the second demultiplexing circuit 140B may be stably maintained and the pixel filling rate may be improved.

As described above, the source electrode of the first charging transistor M11 and the source electrode of the second charging transistor M13 are commonly connected to the second charging node CN_B, so that the first charging transistor M11 and the second charging transistor M11 are connected in common. (M13) is connected in parallel to the second charging node (CN_B). Accordingly, when one of the first and second charging transistors M11 and M13 is turned on, the second charging node CN_B is converted to a high potential voltage by the first auxiliary signal ASW2 or the third auxiliary signal CSW2. can be charged.

The first discharge transistor M12 receives the third time division control signal CSW1 and the second auxiliary signal BSW2, is turned on based on the second auxiliary signal BSW2, and is applied to the second charging node CN_B. The charged voltage VB_B is discharged.

The gate electrode of the first discharge transistor M12 receives the second auxiliary signal BSW2 , the drain electrode of the first discharge transistor M12 is connected to the second charging node CN_B, and the first discharge transistor M12 ) is supplied with the third time division control signal CSW1.

In this case, the turn-on period T3 of the third time division control signal CSW1 and the turn-on period T5 of the second auxiliary signal BSW2 do not overlap, and the first transition of the second auxiliary signal BSW2 does not overlap. Since the third time division control signal CSW1 has a low potential voltage at a time point, when the second auxiliary signal BSW2 having a high potential is supplied, the first discharge transistor M12 is turned on to turn on the second charging node CN_B. Discharge the charged voltage (VB_B).

As described above, the voltage VB_B of the second charging node CN_B is turned on by the first charging transistor M11 turned on by the first auxiliary signal ASW2 or the third auxiliary signal CSW2. It is charged by the turned-on second charging transistor M13 and discharged by the first discharging transistor M12 turned on by the second auxiliary signal BSW2.

When the voltage VB_B of the second charging node CN_B is at a high potential, the second time division control signal BSW1 of the high potential voltage is applied to the second control line CL_B through the turned-on first transistor M1. When supplied, the voltage VB_B of the second charging node CN_B may additionally increase by the gate-source capacitance of the first transistor M1 .

When the voltage VB_B of the second charging node CN_B increases, the second control line CL_B is initially charged (pre-charging), so that the charging of the second control line CL_B is strengthened and the second demultiplexing circuit The output of (140B) can be stably maintained.

Accordingly, the second demultiplexing circuit 140B controls the voltage VB_B of the second charging node CN_B through the first and second charging transistors M11 and M13 and the first discharging transistor M12, Even when the first and second transistors M1 and M2 and the second discharging transistor M21 are deteriorated, the charging characteristic of the second control line CL_B may be improved and leakage current may be prevented from occurring. As a result, the second demultiplexing circuit 140B stably maintains the output of the second switching element S2 that is turned on based on the voltage VA_B of the second control line CL_B, so that the luminance of the display panel is maintained. It is possible to prevent deterioration and realize a high-resolution image of the display panel.

The second booster 143B bootstraps the voltage VA_B charged in the second control line CL_B based on the second auxiliary signal BSW2, and may include a second capacitor C2.

One end of the second capacitor C2 receives the second auxiliary signal BSW2 , and the other end of the second capacitor C2 is connected to the second control line CL_B.

The time point at which the second auxiliary signal BSW2 of the high potential voltage is supplied to one end of the second capacitor C2 may correspond to between the first transition time and the second transition time of the second time division control signal BSW1 .

As described above, the second booster 143B bootstraps the second voltage VA_B of the second control line CL_B maintained by the second charge controller 141B using the second auxiliary signal BSW2. , it is possible to stably maintain the input voltage of the second switching element S2 by increasing the voltage to a higher voltage than the voltage of the second time division control signal BSW1 .

The second second discharge unit 145B discharges the second voltage VA_B charged in the second control line CL_B, and may include the second transistor M2 and the second discharge transistor M21. In addition, by additionally discharging the second voltage VA_B charged in the second control line CL_B, discharge characteristics may be improved to prevent leakage current.

The second transistor M2 is turned on based on the third time division control signal CSW1 to discharge the second voltage VA_B charged in the second control line CL_B, and the second discharge transistor M21 ) may be turned on based on the first time division control signal ASW1 to additionally discharge the second voltage VA_B charged in the second control line CL_B.

The gate electrode of the second transistor M2 receives the third time division control signal CSW1 , the drain electrode of the second transistor M2 is connected to the second control line CL_B, and the The source electrode receives the second time division control signal BSW1.

The gate electrode of the second discharge transistor M21 is supplied with the first time division control signal ASW1, the drain electrode of the second discharge transistor M21 is connected to the second control line CL_B, and the second discharge transistor ( The source electrode of M21 is supplied with the second time division control signal BSW1.

The drain electrode of the second transistor M2 and the drain electrode of the second discharge transistor M21 are commonly connected to the second control line CL_B, and the source electrode of the second transistor M2 and the second discharge transistor M21 are connected in common. ), the source electrode is supplied with the second time division control signal BSW1 in common.

The second transistor M2 is turned on when the third time division control signal CSW1 of the high potential voltage is supplied to the gate electrode while the second time division control signal BSW1 of the low potential voltage is supplied to the source electrode. to discharge the second voltage VA_B charged in the second control line CL_B. The time at which the third time division control signal CSW1 of the high potential voltage is supplied to the gate electrode of the second transistor M2 may correspond to the start time of the third sub-horizontal period SH3 .

The second discharge transistor M21 is turned on when the first time-division control signal ASW1 of the high potential voltage is supplied to the gate electrode while the second time-division control signal BSW1 of the low potential voltage is supplied to the source electrode. It is turned on to additionally discharge the second voltage VA_B charged in the second control line CL_B.

The second discharge transistor M21 is turned on when the third time-division control signal CSW1 of the high potential voltage is supplied to the gate electrode while the first time-division control signal ASW1 of the low potential voltage is supplied to the source electrode. It is turned on to additionally discharge the first voltage VA_A charged in the first control line CL_A.

7 is a circuit diagram showing the configuration of a third demultiplexing circuit of the demultiplexing circuit unit of FIG. 2 , and FIG. 8 is a signal supplied to the first demultiplexing circuit of FIG. 7 , the voltage of the charging node and the voltage of the control line It is a diagram showing a waveform.

7 and 8, the third demultiplexing circuit 140C responds to first to third time division control signals ASW1, BSW1, CSW1, and second and third auxiliary signals BSW2 and CSW2. The third control line CL_C is pre-charged with the voltage VA_C, the voltage VA_C charged with the third control line CL_C is bootstrapped, or the third control line CL_C is Dis-charging the voltage VA_C charged to the , and controlling the third switching element S3 through the voltage control of the third control line CL_C to generate the data signal DS3 for the third sub-horizontal period. It is supplied to the first data line DL3.

The third data signal DS3 supplied to the third data line DL3 through the third switching element S3 under the control of the third demultiplexing circuit 140C may include grayscale information of red light or blue light. have.

The third demultiplexing circuit 140C may include a third charging control unit 141C, a third boosting unit 143C, and a third discharging unit 145C.

The third charging control unit 141C of the third demultiplexing circuit 140C performs third control in response to the first and third time division control signals ASW1 and CSW1 and the second and third auxiliary signals BSW2 and CSW2. A voltage VA_C is charged to the line CL_C.

The third charge controller 141C may include a first transistor M1 , a first charge transistor M1 , and a first discharge transistor M12 .

The first transistor M1 is turned on based on the voltage VB_C of the third charging node CN_C controlled by the second auxiliary signal BSW2 and the third auxiliary signal CSW2 to obtain a third time division control signal (CSW1) may be provided as the third control line CL_C.

The gate electrode of the first transistor M1 is connected to the third charging node CN_C, the drain electrode of the first transistor M1 receives the third time division control signal CSW1, and the The source electrode may be connected to the third control line CL_C.

Accordingly, when the voltage VB_C of the third charging node CN_C and the third time division control signal CSW1 are high potential voltages, the first transistor M1 is turned on and the voltage of the third control line CL_C is turned on. (VA_C) can also maintain a high potential voltage.

The first charging transistor M11 is turned on based on the second auxiliary signal BSW2 overlapping the second time division control signal BSW1 to supply the second auxiliary signal BSW2 to the third charging node CN_C. can

The gate electrode and the drain electrode of the first charging transistor M11 may supply the second auxiliary signal BSW2 , and the source electrode of the first charging transistor M11 may be connected to the third charging node CN_C.

Accordingly, the first charging transistor M11 is turned on according to the supply of the second auxiliary signal BSW2 of the high potential voltage to supply the second auxiliary signal BSW2 to the third charging node CN_C, so that the third The charging node CN_C may be charged.

As described above, before the third time division control signal CSW1 of a high voltage is supplied to the drain electrode of the first transistor M1 , the first charging transistor M11 is turned on by the second auxiliary signal BSW2 . and charging the third charging node CN_C with a high potential voltage, thereby strengthening the charging of the third control line CL_C to stably maintain the output of the third demultiplexing circuit 140C and improve the pixel charging rate .

The first discharge transistor M12 receives the first time division control signal ASW1 and the third auxiliary signal CSW2, is turned on based on the third auxiliary signal CSW2, and is charged in the charging node CN_C. Discharge the voltage (VB_C).

The gate electrode of the first discharge transistor M12 receives the third auxiliary signal CSW2 , the drain electrode of the first discharge transistor M12 is connected to the third charging node CN_C, and the first discharge transistor M12 ) is supplied with the first time division control signal ASW1.

In this case, the turn-on period T1 of the first time division control signal ASW1 and the turn-on period T6 of the third auxiliary signal CSW2 do not overlap, and the first transition of the third auxiliary signal CSW2 At a time point, since the first time division control signal ASW1 has a low potential voltage, when the third auxiliary signal CSW2 of a high potential voltage is supplied, the first discharge transistor M12 is turned on and is applied to the charging node CN_C. The charged voltage VB_C is discharged.

As described above, the voltage VB_C of the third charging node CN_C is charged by the first charging transistor M11 turned on by the second auxiliary signal BSW2, and the third auxiliary signal CSW2 is discharged by the first discharge transistor M12 turned on by

In a state in which the voltage VB_C of the third charging node CN_C is at a high potential, the third time division control signal CSW1 of the high potential voltage is applied to the third control line CL_C through the turned-on first transistor M1. When supplied, the voltage VB_C of the third charging node CN_C may additionally increase by the gate-source capacitance of the first transistor M1 .

When the voltage VB_C of the third charging node CN_C increases, the third control line CL_C is initially pre-charged, so that the charging of the third control line CL_C is strengthened and the third demultiplexing circuit The output of (140C) can be stably maintained.

Accordingly, the third demultiplexing circuit 140C controls the voltage VB_C of the third charging node CN_C through the first charging transistor M11 and the first discharging transistor M12, so that the first and second transistors Even when the (M1, M2) and the second discharging transistors M21 are deteriorated, the charging characteristics of the third control line CL_C may be improved and the occurrence of leakage current may be prevented. As a result, the third multiplexing circuit 140C stably maintains the output of the third switching element S3 turned on based on the voltage VA_C of the third control line CL_C, so that the luminance of the display panel is increased. It is possible to prevent deterioration and realize a high-resolution image of the display panel.

The third booster 143C of the third demultiplexing circuit 140C bootstraps the voltage VA_C charged in the third control line CL_C based on the third auxiliary signal CSW2, and the third capacitor ( C3) may be composed.

One end of the third capacitor C3 receives the third auxiliary signal CSW2 , and the other end of the third capacitor C3 is connected to the third control line CL_C.

One end of the third capacitor C3 supplies the third auxiliary signal CSW2 , and the other end of the third capacitor C3 is connected to the third control line CL_C.

The time point at which the third auxiliary signal CSW2 of the high potential voltage is supplied to one end of the third capacitor C3 may correspond to between the first transition time and the second transition time of the third time division control signal CSW1 .

As such, the third booster 140C bootstraps the voltage VA_C of the third control line CL_C maintained by the third charge controller 141C using the third auxiliary signal CSW2, The input voltage of the third switching element S3 may be stably maintained by rising to a voltage higher than the voltage of the third time division control signal CSW1 .

The third discharge unit 145C of the third demultiplexing circuit 140C discharges the third voltage VA_C charged in the third control line CL_C, and may be composed of a second transistor M2, By additionally discharging the third voltage VA_C charged in the third control line CL_C by further including the second discharging transistor M21, the discharge characteristic may be improved, thereby preventing the occurrence of leakage current.

The second transistor M2 is turned on based on the second time division control signal BSW1 to discharge the third voltage VA_C charged in the third control line CL_C, and the second discharge transistor M21 ) may be turned on based on the first time division control signal ASW1 to additionally discharge the third voltage VA_C charged in the third control line CL_C.

The gate electrode of the second transistor M2 receives the second time division control signal BSW1 , the drain electrode of the second transistor M2 is connected to the third control line CL_C, and the The source electrode receives the third time division control signal CSW1.

The gate electrode of the second discharge transistor M21 is supplied with the first time division control signal ASW1, the drain electrode of the second discharge transistor M21 is connected to the third control line CL_C, and the second discharge transistor ( The source electrode of M21 receives the third time division control signal CSW1.

The drain electrode of the second transistor M2 and the drain electrode of the second discharge transistor M21 are commonly connected to the third control line CL_C, and the source electrode of the second transistor M2 and the second discharge transistor M21 are connected in common. ), the source electrode receives the third time division control signal CSW1 in common.

The second transistor M2 is turned on when the second time division control signal BSW1 of the high potential voltage is supplied to the gate electrode while the third time division control signal CSW1 of the low potential voltage is supplied to the source electrode. to discharge the third voltage VA_C charged in the third control line CL_C.

The second discharge transistor M21 is turned on when receiving the first time-division control signal ASW1 of the high potential voltage to the gate electrode while the third time-division control signal CSW1 of the low potential voltage is supplied to the source electrode. It is turned on to additionally discharge the third voltage VA_C charged in the third control line CL_C.

9 is a circuit diagram illustrating a configuration including first to third demultiplexing in the demultiplexing circuit unit of FIG. 2 , and FIG. 10 is a signal supplied to the demultiplexing circuit unit of FIG. 9 , a voltage of a charging node, and a control line It is a diagram showing a waveform with respect to the voltage of

9 and 10, the demultiplexing circuit unit 140 responds to first to third time division control signals ASW1, BSW1, and CSW1 and first to third auxiliary signals ASW2, BSW2, and CSW2. The first to third data selection signals are output to the to third control lines CL_A to CL_C, and the switching unit S-IC responds to the three data selection signals from the input unit I-IC to the data signals ( DS) is time-divided and distributed to three data lines DL1 to DL3.

The demultiplexing circuit unit 140 receives the first to third data selection signals output from the first to third demultiplexing circuits 140A, 140B, and 140C through the first to third control lines CL_A to CL_C. The first to third data signals DS1 to DS3 are applied to the first to third data signals DS1 to DS3 every 3 sub-horizontal periods by dividing the data signal DS supplied through the source channel SH by controlling the third switching elements S1 to S3. It is supplied to the third data lines DL1 to DL3.

The demultiplexing circuit unit 140 operates two horizontal periods (2H) in one period (T) to implement RGB-BGR, but during the first horizontal period (t1), every sub-horizontal period (SH1, SH2, SH3) The first to third demultiplexing circuits 140A, 140B, and 140C operate sequentially, and during the second horizontal period t2, the first to third demultiplexing circuits 140A and 140B for each sub-horizontal period SH1, SH2, SH3. , 140C) operates in the reverse order.

To this end, in the first horizontal period t1 under the control of the first to third demultiplexing circuits 140A, 140B, and 140C, the first data line DL1, the second data line DL2, and the third data The data signals DS1, DS2, and DS3 for sub-horizontal periods are sequentially supplied to the line DL3, and in the second horizontal period t2, the third data line DL3, the second data line DL2, and the first Data signals D3, D2, and D1 for sub-horizontal periods are sequentially supplied to the data line DL1.

The first data signal DS1 supplied to the first data line DL1 under the control of the first demultiplexing circuit 140A includes red light grayscale information, and according to the control of the second demultiplexing circuit 140B The second data signal DS2 supplied to the second data line DL2 includes green light grayscale information, and the third data signal DS2 supplied to the third data line DL3 is controlled by the third demultiplexing circuit 140C. The data signal DS3 includes blue light grayscale information.

Accordingly, the demultiplexing circuit unit 140 implements RGB during the first to third sub-horizontal periods of the first one horizontal period t1 within the period T, and the first to third sub-horizontal periods of the second one horizontal period t2. Implement BGR during the horizontal period.

Accordingly, the demultiplexing circuit unit 140 supplies the second data signal DS2 to the second data line DL2 for one sub-horizontal period 1H, and applies the first and third data signals DS1 and DS3. It is supplied to the first and third data lines DL1 and DL3 for 2 sub-horizontal periods.

The first demultiplexing circuit 140A transmits the first data signal DS1 to the first data line DL1 in response to the first time division control signal ASW1 having a turn-on period T1 corresponding to two sub-horizontal periods. ), and the second demultiplexing circuit 140B outputs the second data signal DS2 in response to the second time division control signal BSW1 having a turn-on period T2 corresponding to one sub-horizontal period. is supplied to the second data line DL2, and the third multiplexing circuit 140C responds to the third time division control signal CSW1 having a turn-on period T3 corresponding to two sub-horizontal periods. DS3) is supplied to the third data line DL3.

In this case, the period of the first and third time division control signals ASW1 and CSW1 corresponds to 6 sub-horizontal periods (2 horizontal periods), and the period of the second time division control signal BSW1 corresponds to 3 sub-horizontal periods (one horizontal period). ), the period of the first and third time division control signals ASW1 and CSW1 is two longer than the period of the second time division control signal BSW1.

In addition, the turn-on periods T1 and T3 of the first and third time division control signals ASW1 and CSW1 are longer than the turn-on periods T2 of the second time division control signal BSW1, and the first and third The turn-on periods T4 and T6 of the auxiliary signals ASW2 and CSW2 are longer than the turn-on periods T5 of the second auxiliary signal BSW2.

The turn-on periods T1 and T3 of the first and third time division control signals ASW1 and CSW1 and the turn-on periods T4 and T6 of the first and third auxiliary signals ASW2 and CSW2 are 2 sub It is maintained over a horizontal period, and the turn-on period T2 of the second time division control signal BSW1 and the turn-on period T5 of the second auxiliary signal BSW2 are maintained within one sub-horizontal period.

A display device according to the present specification may be described as follows.

A display device according to an embodiment of the present specification includes a demultiplexing circuit unit that time-divisions a data signal output from a data driver into first to third sub-horizontal periods and distributes the data signal to first to third data lines.

According to an embodiment of the present specification, the demultiplexing circuit unit outputs the first to third data selection signals to the first to third control lines in response to the first to third time division control signals and the first to third auxiliary signals. and a switching unit for time-dividing data to first to third data lines in response to the three data selection signals, wherein the period of the first and third time-division control signals is greater than the period of the second time-division control signal. long.

According to an embodiment of the present specification, the first to third auxiliary signals overlap the first to third time division control signals, respectively, and the turn-on period of the first to third auxiliary signals is respectively the first to third time division control signals. It is smaller than the turn-on period of the control signal.

According to an embodiment of the present specification, the first transition time of each of the first to third auxiliary signals is later than the first transition time of each of the first to third time division control signals, and the second time of each of the first to third auxiliary signals The second transition time is the same as the second transition time of each of the first to third time division control signals.

According to an embodiment of the present specification, the period of the first and third time division control signals corresponds to two horizontal periods, and the period of the second time division control signal corresponds to one horizontal period.

According to an embodiment of the present specification, the first and third time division control signals have a turn-on period corresponding to 2 sub-horizontal periods, and the second time division control signal has a turn-on period corresponding to 1 sub-horizontal period. have

According to an embodiment of the present specification, the demultiplexing circuit unit operates with two horizontal periods as one period, and sequentially transmits first to third data signals to the first to third data lines during three sub-horizontal periods of the first horizontal period. and sequentially supplying the third to first data signals to the third to first data lines during three sub-horizontal periods of the second horizontal period.

According to an embodiment of the present specification, the demultiplexing circuit unit operates with two horizontal periods as one cycle, supplies a first data signal to the first data line during a second horizontal period, and provides a second data signal during the first horizontal period. is supplied to the second data line, and a third data signal is supplied to the third data line during the second horizontal period.

According to an embodiment of the present specification, the demultiplexing circuit unit charges the first control line at the first transition time of the first time division control signal for 2 sub-horizontal periods, and the first auxiliary signal overlaps the first time division control signal. The first control voltage of the first control line is bootstrapped at the first transition time of , and the first control voltage of the first control line is discharged at the first transition time of the second time division control signal.

According to an embodiment of the present specification, the demultiplexing circuit unit charges the second control line at the first transition time of the second time division control signal for one sub-horizontal period, and a second auxiliary signal overlapping the second time division control signal. The second control voltage of the second control line is bootstrapped at the first transition time of , and the second control voltage of the second control line is discharged at the first transition time of the third time division control signal.

According to an embodiment of the present specification, the demultiplexing circuit unit charges the third control line at the first transition time of the third time division control signal during the 2 sub-horizontal period, and the third auxiliary signal overlaps the third time division control signal. The third control voltage of the third control line is bootstrapped at the first transition time of , and the third control voltage of the third control line is discharged at the first transition time of the second time division control signal.

According to an embodiment of the present specification, the input unit includes: a first demultiplexing circuit for controlling a first control voltage of a first control line in response to first to third time division control signals and first and third auxiliary signals; a second demultiplexing circuit for controlling the second control voltage of the second control line in response to the first to third time division control signals and the first to third auxiliary signals, and the first to third time division control signals and the second and a third demultiplexing circuit for controlling a third control voltage of the third control line in response to the third auxiliary signal.

According to an embodiment of the present specification, the first demultiplexing circuit includes a first for charging a first control voltage in a first control line in response to first and second time division control signals and first and third auxiliary signals. The charging control unit, the first boosting unit for bootstrapping the first control voltage of the first control line based on the first auxiliary signal, and the first control voltage of the first control line in response to the first and second time division control signals It includes a first discharge unit for discharging.

According to an embodiment of the present specification, the first charging control unit is turned on based on the first charging voltage on the first charging node to supply the first time division control signal to the first control line, the first transistor, the third The charging transistor is turned on based on the auxiliary signal to supply the third auxiliary signal to the first charging node, and the first charging transistor is turned on based on the first auxiliary signal to discharge the first charging voltage of the first charging node. It includes a discharge transistor.

According to an embodiment of the present specification, the first discharge unit includes a second transistor that is turned on based on the second time division control signal to discharge the first control voltage of the first control node.

According to an embodiment of the present specification, the second demultiplexing circuit is configured to charge a second control voltage to a second control line in response to second and third time division control signals and first to third auxiliary signals. The charging control unit, a second boosting unit for bootstrapping the second control voltage of the second control line based on the second auxiliary signal, and the second control voltage of the second control line in response to the second and third time division control signals and a second discharging unit for discharging.

According to one embodiment of the present specification, the second charging control unit is turned on based on the second charging voltage on the second charging node, the first transistor supplying the first time division control signal to the second control line, the first The first charging transistor is turned on based on the auxiliary signal to supply the first auxiliary signal to the second charging node, and the first charging transistor is turned on based on the third auxiliary signal to supply the third auxiliary signal to the second charging node. 2 charging transistors, and a first discharging transistor turned on based on the second auxiliary signal to discharge a second charging voltage of the second charging node.

According to an embodiment of the present specification, the second discharge unit includes a second transistor that is turned on based on the third time division control signal to discharge the second control voltage of the second control line.

According to an embodiment of the present specification, the third demultiplexing circuit is configured to charge the third control voltage of the third control line in response to the second and third time division control signals and the second and third auxiliary signals. The charging control unit, a third boosting unit for bootstrapping the third control voltage of the third control line based on the third auxiliary signal, and the third control voltage of the third control line in response to the second and third time division control signals and a third discharging unit for discharging.

According to an embodiment of the present specification, the third charging control unit is turned on based on the third charging voltage on the third charging node to supply the third time division control signal to the third control line, the first transistor, the second The charging transistor is turned on based on the auxiliary signal to supply the second auxiliary signal to the third charging node, and the first charging transistor is turned on based on the third auxiliary signal to discharge the third charging voltage of the third charging node. It includes a discharge transistor.

According to an embodiment of the present specification, the third discharge unit includes a second transistor that is turned on based on the first time division control signal to discharge the third control voltage of the third control line.

Features, structures, effects, etc. described in various examples of the present specification are included in at least one example of the present specification, and are not necessarily limited to only one example. Furthermore, features, structures, effects, etc. illustrated in at least one example of the present specification can be combined or modified with respect to other examples by those of ordinary skill in the art to which the technical idea of the present specification pertains. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the technical scope or scope of the present specification.

The present specification described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which this specification belongs that various substitutions, modifications, and changes are possible without departing from the technical spirit of the present specification. It will be clear to those who have the knowledge of Therefore, the scope of the present specification is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present specification.

110: display panel
120: data driver
130: gate driver
140 Demultiplex circuit part
140A, 140B, 140C: Demultiplex circuit
141A, 141B, 141C: charging control unit
143A, 143B, 143C: step-up unit
145A, 145B, 145C: Discharge part
I-IC: input
S-IC : Switching part
S1, S2, S3: switching element

Claims (20)

a demultiplexing circuit unit for time-dividing the data signal output from the data driver into first to third sub-horizontal periods and distributing it to first to third data lines;
The demultiplexing circuit unit,
an input unit for outputting first to third data selection signals to first to third control lines in response to first to third time division control signals and first to third auxiliary signals; and
a switching unit for time-dividing the data signal in response to the three data selection signals and distributing it to first to third data lines;
and a period of the first and third time division control signals is longer than a period of the second time division control signal. The method of claim 1,
The first to third auxiliary signals overlap the first to third time division control signals, respectively, and the turn-on period of the first to third auxiliary signals is the turn-on period of the first to third time division control signals. Smaller than the on interval, the display device. The method of claim 1,
A first transition time of each of the first to third auxiliary signals is later than a first transition time of each of the first to third time division control signals, and a second transition time of each of the first to third auxiliary signals is the second transition time of the first to third auxiliary signals. The display device is identical to the second transition time of each of the first to third time division control signals. The method of claim 1,
A period of the first and third time division control signals corresponds to two horizontal periods, and a period of the second time division control signal corresponds to one horizontal period. The method of claim 1,
The first and third time division control signals have a turn-on period corresponding to two sub-horizontal periods, and the second time-division control signal has a turn-on period corresponding to one sub-horizontal period. The method of claim 1,
The demultiplexing circuit unit operates with two horizontal periods as one period, and sequentially supplies first to third data signals to the first to third data lines during three sub-horizontal periods of the first horizontal period, and and sequentially supplying the third to first data signals to the third to first data lines during three sub-horizontal periods of a period. The method of claim 1,
The demultiplexing circuit unit operates with two horizontal periods as one period, supplies a first data signal to the first data line during a second horizontal period, and transmits a second data signal to the second data line during a first horizontal period. and supplying a third data signal to the third data line during a second horizontal period. The method of claim 1,
The demultiplexing circuit unit charges the first control line at a first transition point of the first time division control signal for 2 sub-horizontal periods, and a first transition of the first auxiliary signal overlaps with the first time division control signal bootstrapping the first control voltage of the first control line at a time point and discharging the first control voltage of the first control line at a first transition time point of the second time division control signal. The method of claim 1,
The demultiplexing circuit unit charges the second control line at a first transition point of the second time division control signal for one sub-horizontal period, and a first transition of the second auxiliary signal overlaps with the second time division control signal. Bootstrapping the second control voltage of the second control line at a timing point and discharging the second control voltage of the second control line at a first transition point of the third time division control signal. The method of claim 1,
The demultiplexing circuit unit charges the third control line at a first transition time of the third time division control signal for 2 sub-horizontal periods, and a first transition of the third auxiliary signal overlaps with the third time division control signal Bootstrapping the third control voltage of the third control line at a time point and discharging the third control voltage of the third control line at a first transition time point of the second time division control signal. The method of claim 1,
The input unit,
a first demultiplexing circuit for controlling a first control voltage of the first control line in response to the first to third time division control signals and the first and third auxiliary signals;
a second demultiplexing circuit for controlling a second control voltage of the second control line in response to the first to third time division control signals and the first to third auxiliary signals; and
and a third demultiplexing circuit configured to control a third control voltage of the third control line in response to the first to third time division control signals and the second and third auxiliary signals. 12. The method of claim 11,
The first demultiplexing circuit comprises:
a first charging control unit configured to charge the first control voltage to the first control line in response to the first and second time division control signals and the first and third auxiliary signals;
a first booster configured to bootstrap the first control voltage of the first control line based on the first auxiliary signal; and
and a first discharge unit configured to discharge the first control voltage of the first control line in response to the first and second time division control signals. 13. The method of claim 12,
The first charging control unit,
a first transistor turned on based on a first charging voltage on a first charging node to supply the first time division control signal to the first control line;
a charging transistor turned on based on the third auxiliary signal to supply the third auxiliary signal to the first charging node; and
and a first discharging transistor turned on based on the first auxiliary signal to discharge the first charging voltage of the first charging node. 13. The method of claim 12,
and the first discharge unit includes a second transistor that is turned on based on the second time division control signal to discharge the first control voltage of the first control node. 12. The method of claim 11,
The second demultiplexing circuit comprises:
a second charging control unit configured to charge the second control voltage to the second control line in response to the second and third time division control signals and the first to third auxiliary signals;
a second booster configured to bootstrap the second control voltage of the second control line based on the second auxiliary signal; and
and a second discharge unit configured to discharge the second control voltage of the second control line in response to the second and third time division control signals. 16. The method of claim 15,
The second charging control unit,
a first transistor turned on based on a second charging voltage on a second charging node to supply the first time division control signal to the second control line;
a first charging transistor turned on based on the first auxiliary signal to supply the first auxiliary signal to the second charging node;
a second charging transistor turned on based on the third auxiliary signal to supply the third auxiliary signal to the second charging node; and
and a first discharging transistor turned on based on the second auxiliary signal to discharge the second charging voltage of the second charging node. 16. The method of claim 15,
and a second transistor that is turned on based on the third time division control signal to discharge the second control voltage of the second control line. 12. The method of claim 11,
The third demultiplexing circuit comprises:
a third charging control unit configured to charge the third control voltage of the third control line in response to the second and third time division control signals and the second and third auxiliary signals;
a third booster configured to bootstrap the third control voltage of the third control line based on the third auxiliary signal; and
and a third discharge unit configured to discharge the third control voltage of the third control line in response to the second and third time division control signals. 19. The method of claim 18,
The third charging control unit,
a first transistor turned on based on a third charging voltage on a third charging node to supply the third time division control signal to the third control line;
a charging transistor turned on based on the second auxiliary signal to supply the second auxiliary signal to the third charging node; and
and a first discharging transistor turned on based on the third auxiliary signal to discharge the third charging voltage of the third charging node. 20. The method of claim 19,
and a second transistor turned on based on the first time division control signal to discharge the third control voltage of the third control line.

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