KR20210035723A - Signal processing device and image display apparatus including the same - Google Patents

Abstract

The present invention relates to a signal processing device and an image display apparatus including the same. According to one embodiment of the present invention, the signal processing device comprises: an input interface receiving a video signal from the outside; a first image processing unit generating first image frame data on the basis of the image signal; a second image processing unit generating second image frame data scaled down compared to the first image frame data on the basis of the image signal; and an output interface receiving the first image frame data from the first image processing unit, receiving the second image frame data from the second image processing unit, and outputting the first image frame data and the second image frame data, wherein the first image frame data output from the output interface is delayed more than the second image frame data. Accordingly, a timing controller can accurately and quickly perform signal processing for a panel.

Description

Signal processing device and image display apparatus including the same

The present invention relates to a signal processing device and an image display device having the same, and more particularly, to a signal processing device capable of accurately and quickly performing signal processing for a panel in a timing controller, and an image display device having the same. About.

The signal processing device is a device that performs signal processing on an input image so that an image can be displayed.

For example, the signal processing apparatus receives various video signals such as a broadcast signal or an external input signal (for example, an HDMI signal), and performs signal processing based on the received broadcast signal or an external input signal. The video signal can be output to the display.

Meanwhile, the display may include a panel and a timing controller that operates to output a signal to the panel.

Recently, in order to make the display slimmer, research is being conducted for slimming panels and timing controllers.

In particular, in order to make the timing controller slimmer, a method of removing or hardly using the memory in the timing controller has been devised.

However, if the memory of the timing controller is removed, there is no image stored in the memory. Therefore, if the timing controller performs signal processing for lowering the luminance to reduce the power consumption of the panel, it is difficult to predict the image luminance. There is a problem in that the signal processing is not accurately processed, and thus damage to the panel may occur.

An object of the present invention is to provide a signal processing apparatus capable of outputting a signal to enable accurate and rapid signal processing in a timing controller, and an image display apparatus having the same.

On the other hand, another object of the present invention is to provide a signal processing apparatus capable of accurately and quickly performing signal processing for reducing power consumption in a timing controller, and an image display apparatus having the same.

On the other hand, another object of the present invention is to provide a signal processing device capable of outputting first image frame data and second image frame data through the same transmission line, and an image display device having the same.

Meanwhile, another object of the present invention is to provide an image display device capable of removing a memory from a timing controller.

On the other hand, another object of the present invention is to provide a signal processing device capable of generating scaled-down second image frame data with reduced error compared with first image frame data, and an image display device having the same. .

A signal processing apparatus according to an embodiment of the present invention for achieving the above object includes an input interface for receiving an external image signal, a first image processing unit for generating first image frame data based on the image signal, Based on the image signal, a second image processing unit that generates second image frame data scaled down from the first image frame data, first image frame data from the first image processing unit, and second image frame data from the second image processing unit And an output interface configured to receive image frame data and output first image frame data and second image frame data, and the first image frame data output from the output interface is output after being delayed from the second image frame data.

Meanwhile, the first image frame data output from the first image processing unit may be delayed and output from the second image frame data output from the second image processing unit.

Meanwhile, the output interface may output the first image frame data by delaying it from the second image frame data.

Meanwhile, when the output first image frame data is n frame data, the output interface may output frame data after the n frame data as second image frame data.

Meanwhile, the signal processing apparatus according to an embodiment of the present invention may further include a memory for storing frame data for image processing by the first image processing unit.

Meanwhile, the output interface may simultaneously output first image frame data for n-1 image frames and second image frame data for n image frames.

Meanwhile, the output interface includes a first output terminal for transmitting a vertical synchronization signal, a second output terminal for transmitting a horizontal synchronization signal, a third output terminal for transmitting an image data signal, and a fourth output terminal for transmitting a data enable signal. And transmits the first image frame data and the second image frame data through the third output terminal.

Meanwhile, the output interface outputs a data enable signal divided into an active period and a blank period, and the first image frame data is more than the first active period of the first data enable signal when only the first image frame data is output. The second active period of the second data enable signal when the and second image frame data are output may be larger.

Meanwhile, the output interface outputs a data enable signal divided into an active period and a blank period, and when only the first image frame data is output, the first image frame data is more than the first blank period of the first data enable signal. The second blank period of the second data enable signal when the and second image frame data are output may be smaller.

Meanwhile, the output interface outputs a data enable signal divided into an active period and a blank period, and may set the length of the active period based on the resolution information of the panel and the driving frequency of the panel.

On the other hand, the output interface adds the section for transmitting the second video frame data to the section for transmitting the first video frame data having the first length, and obtains an active section having a second length greater than the first length. Can be set.

On the other hand, the output interface outputs a data enable signal divided into an active period and a blank period, and when the resolution of the panel is the first resolution and the driving frequency of the panel is the first frequency, When a blank section having a length of 2 is set, and when the first video frame data and the second video frame data are output, at least part of the first video frame data is transmitted during the active section of the first length, and a blank section of the second length During some of the periods, at least part of the second image frame data may be transmitted.

Meanwhile, the output interface includes a first output terminal for transmitting a vertical synchronization signal, a second output terminal for transmitting a horizontal synchronization signal, a third output terminal for transmitting a data signal of the first image frame data, and the first image frame data. A fourth output terminal for transmitting a data enable signal, a fifth output terminal for transmitting a data signal of the second image frame data, and a sixth output terminal for transmitting a data enable signal of the second image frame data may be included. .

Meanwhile, the output interface may output the first image frame data and the second image frame data using different output terminals.

Meanwhile, when the image output mode is a low-delay mode, the output interface outputs the first image frame data for n image frames and the second image frame data for n image frames together, or the second image frame data. May not be printed.

Meanwhile, the low delay mode may include at least one of a game mode and a mirroring mode.

Meanwhile, the second image processor may include a scaler that generates second image frame data scaled down from the first image frame data based on the image signal.

Meanwhile, the scaler may generate at least one super pixel or super block based on some of the image blocks of the image signal, and output scaled-down second image frame data including the super pixel or super block.

Meanwhile, the scaler may change the size of the super pixel or the super block according to the resolution or image size of the image signal.

Meanwhile, a signal processing apparatus according to another embodiment of the present invention includes an input interface for receiving an image signal from an external source, a first image processing unit that generates first image frame data based on the image signal, and the image signal. Thus, a second image processing unit for generating image frame data, an output for outputting a data enable signal divided into an active period and a blank period, a data signal of the first image frame data, and a data signal of the second image frame data And an interface, wherein when only the data signal of the first image frame data is output, the active section of the first data enable signal is set to a first length, and the data signal of the first image frame data When the data signals of the two image frame data are output together, the active section of the second data enable signal is set to a second length that is greater than the first length.

On the other hand, when only the data signal of the first image frame data is output, the output interface sets the blank section of the first data enable signal to a third length, the data signal of the first image frame data, and the second image frame. When the data signal of the data is output together, the blank section of the second data enable signal may be set to a fourth length smaller than the third length.

Meanwhile, the output interface may vary the length of the active section of the second data enable signal based on the resolution information of the panel and the driving frequency of the panel.

On the other hand, the image display device according to an embodiment of the present invention, a signal processing device in which the first image frame data is output with a delay compared to the second image frame data, and a signal processing based on the image signal output from the signal processing device. A timing controller that performs the operation and a panel that displays an image based on a signal from the timing controller may be provided.

Meanwhile, the timing controller extracts information on the first image frame data based on the second image frame data from the signal processing apparatus, and performs signal processing on the first image frame data based on the extracted information. , A signal for the signal-processed first image frame data may be output to the panel.

On the other hand, the timing controller extracts information on the first image frame data based on the second image frame data from the signal processing apparatus, and when the power information based on the luminance information in the extracted information exceeds the reference value, The luminance level of the first image frame data is lowered from the first level to the second level so that the power consumed by the panel is less than the allowable value, and the signal for the first image frame data whose luminance is changed to the second level is transferred to the panel. Can be printed.

On the other hand, the timing controller can control the power level consumed by the panel to be less than or equal to an allowable value based on the luminance information in the extracted information.

On the other hand, the timing controller sets the luminance level of the partial region of the first image frame data to the first when the power information based on the luminance information on the partial region of the first image frame data exceeds the reference value based on the extracted information. A signal for a partial region of the first image frame data lowered from the level to the second level and whose luminance is changed to the second level may be output to the panel.

Meanwhile, when the image output mode of the signal processing apparatus is the first mode, the timing controller receives the first image frame data and the second image frame data, and based on the second image frame data, the timing controller receives the first image frame data. The signal-processed first image frame data is controlled to be displayed on the panel, and when the image output mode of the signal processing apparatus is the second mode, the received first image frame data without information on the second image frame data By signal processing, the signal-processed first image frame data may be controlled to be displayed on the panel.

A signal processing apparatus according to an embodiment of the present invention includes an input interface for receiving an external image signal, a first image processing unit that generates first image frame data based on the image signal, and based on the image signal, Receives a second image processing unit that generates second image frame data scaled down from the first image frame data, first image frame data from the first image processing unit, and second image frame data from the second image processing unit, And an output interface that outputs the first image frame data and the second image frame data, and the first image frame data output from the output interface is output after being delayed from the second image frame data. Accordingly, it is possible to output a signal to enable accurate and rapid signal processing in the timing controller.

Meanwhile, the timing controller can accurately and quickly perform signal processing on the delayed and output first image frame data based on the second image frame data. In particular, it is possible to accurately and quickly perform signal processing for reducing power consumption in the timing controller.

Meanwhile, the first image frame data output from the first image processing unit may be delayed and output from the second image frame data output from the second image processing unit. Accordingly, the timing controller can accurately and quickly perform signal processing for the panel.

Meanwhile, the output interface may output the first image frame data by delaying it from the second image frame data. Accordingly, the timing controller can accurately and quickly perform signal processing for the panel.

Meanwhile, when the output first image frame data is n frame data, the output interface may output frame data after the n frame data as second image frame data. Accordingly, the timing controller can accurately and quickly perform signal processing for the panel.

Meanwhile, the signal processing apparatus according to an embodiment of the present invention may further include a memory for storing frame data for image processing by the first image processing unit. Since the frame data is stored in the memory and then read, the first image frame data is output with a delay compared to the second image frame data. Accordingly, the timing controller can accurately and quickly perform signal processing for the panel.

Meanwhile, the output interface may simultaneously output first image frame data for n-1 image frames and second image frame data for n image frames. Accordingly, the timing controller can accurately and quickly perform signal processing for the panel.

Meanwhile, the output interface includes a first output terminal for transmitting a vertical synchronization signal, a second output terminal for transmitting a horizontal synchronization signal, a third output terminal for transmitting an image data signal, and a fourth output terminal for transmitting a data enable signal. And transmits the first image frame data and the second image frame data through the third output terminal. Accordingly, it is possible to output the first image frame data and the second image frame data through the same transmission line. In addition, the first image frame data is output after being delayed from the second image frame data.

Meanwhile, the output interface outputs a data enable signal divided into an active period and a blank period, and the first image frame data is more than the first active period of the first data enable signal when only the first image frame data is output. The second active period of the second data enable signal when the and second image frame data are output may be larger. Accordingly, it is possible to output the first image frame data and the second image frame data through the same transmission line. In addition, the first image frame data is output after being delayed from the second image frame data.

Meanwhile, the output interface outputs a data enable signal divided into an active period and a blank period, and when only the first image frame data is output, the first image frame data is more than the first blank period of the first data enable signal. The second blank period of the second data enable signal when the and second image frame data are output may be smaller. Accordingly, it is possible to output the first image frame data and the second image frame data through the same transmission line. In addition, the first image frame data is output after being delayed from the second image frame data.

Meanwhile, the output interface outputs a data enable signal divided into an active period and a blank period, and may set the length of the active period based on the resolution information of the panel and the driving frequency of the panel. Accordingly, it is possible to output the first image frame data and the second image frame data through the same transmission line. In addition, the first image frame data is output after being delayed from the second image frame data.

On the other hand, the output interface adds the section for transmitting the second video frame data to the section for transmitting the first video frame data having the first length, and obtains an active section having a second length greater than the first length. Can be set. Accordingly, it is possible to output the first image frame data and the second image frame data through the same transmission line. In addition, the first image frame data is output after being delayed from the second image frame data.

On the other hand, the output interface outputs a data enable signal divided into an active period and a blank period, and when the resolution of the panel is the first resolution and the driving frequency of the panel is the first frequency, When a blank section having a length of 2 is set, and when the first video frame data and the second video frame data are output, at least part of the first video frame data is transmitted during the active section of the first length, and a blank section of the second length During some of the periods, at least part of the second image frame data may be transmitted. Accordingly, it is possible to output the first image frame data and the second image frame data through the same transmission line. In addition, the first image frame data is output after being delayed from the second image frame data.

Meanwhile, the output interface includes a first output terminal for transmitting a vertical synchronization signal, a second output terminal for transmitting a horizontal synchronization signal, a third output terminal for transmitting a data signal of the first image frame data, and the first image frame data. A fourth output terminal for transmitting a data enable signal, a fifth output terminal for transmitting a data signal of the second image frame data, and a sixth output terminal for transmitting a data enable signal of the second image frame data may be included. . Accordingly, it is possible to output the first image frame data and the second image frame data through different transmission lines. In addition, the first image frame data is output after being delayed from the second image frame data.

Meanwhile, the output interface may output the first image frame data and the second image frame data using different output terminals. Accordingly, it is possible to output the first image frame data and the second image frame data through different transmission lines. In addition, the first image frame data is output after being delayed from the second image frame data.

Meanwhile, when the image output mode is a low-delay mode, the output interface outputs the first image frame data for n image frames and the second image frame data for n image frames together, or the second image frame data. May not be printed. Accordingly, the amount of signal processing of the timing controller in the case of the low-delay mode and the case of the non-low-delay mode is different. In addition, in the case of the non-low delay mode, the panel display timing may be further shortened in the low delay mode.

Meanwhile, the low delay mode may include at least one of a game mode and a mirroring mode. Accordingly, in the low delay mode, a delay can be reduced when an image is displayed.

Meanwhile, the second image processor may include a scaler that generates second image frame data scaled down from the first image frame data based on the image signal. Accordingly, it is possible to generate scaled-down second image frame data with reduced errors compared with the first image frame data.

Meanwhile, the scaler may generate at least one super pixel or super block based on some of the image blocks of the image signal, and output scaled-down second image frame data including the super pixel or super block. Accordingly, it is possible to generate scaled-down second image frame data with reduced errors compared with the first image frame data.

Meanwhile, the scaler may change the size of the super pixel or the super block according to the resolution or image size of the image signal. Accordingly, it is possible to generate scaled-down second image frame data with reduced errors compared with the first image frame data.

Meanwhile, a signal processing apparatus according to another embodiment of the present invention includes an input interface for receiving an image signal from an external source, a first image processing unit that generates first image frame data based on the image signal, and the image signal. Thus, a second image processing unit for generating image frame data, an output for outputting a data enable signal divided into an active period and a blank period, a data signal of the first image frame data, and a data signal of the second image frame data And an interface, wherein when only the data signal of the first image frame data is output, the active section of the first data enable signal is set to a first length, and the data signal of the first image frame data When the data signals of the two image frame data are output together, the active section of the second data enable signal is set to a second length that is greater than the first length. Accordingly, it is possible to output a signal to enable accurate and rapid signal processing in the timing controller.

Meanwhile, the timing controller can accurately and quickly perform signal processing on the delayed and output first image frame data based on the second image frame data. In particular, it is possible to accurately and quickly perform signal processing for reducing power consumption in the timing controller.

On the other hand, when only the data signal of the first image frame data is output, the output interface sets the blank section of the first data enable signal to a third length, the data signal of the first image frame data, and the second image frame. When the data signal of the data is output together, the blank section of the second data enable signal may be set to a fourth length smaller than the third length. Accordingly, when the data signal of the first image frame data and the data signal of the second image frame data are simultaneously output, the timing controller can accurately and quickly perform signal processing on the panel.

Meanwhile, the output interface may vary the length of the active section of the second data enable signal based on the resolution information of the panel and the driving frequency of the panel. Accordingly, it is possible to output the data signal of the first image frame data and the second image frame data in response to the resolution information of the panel and the driving frequency of the panel. As a result, it is possible to accurately and quickly perform signal processing on the panel in the timing controller.

On the other hand, the image display device according to an embodiment of the present invention, a signal processing device in which the first image frame data is output with a delay compared to the second image frame data, and a signal processing based on the image signal output from the signal processing device. A timing controller that performs the operation and a panel that displays an image based on a signal from the timing controller may be provided. Accordingly, the timing controller can accurately and quickly perform signal processing for the panel.

Meanwhile, the timing controller extracts information on the first image frame data based on the second image frame data from the signal processing apparatus, and performs signal processing on the first image frame data based on the extracted information. , A signal for the signal-processed first image frame data may be output to the panel. Meanwhile, the timing controller can accurately and quickly perform signal processing on the delayed and output first image frame data based on the second image frame data. In particular, it is possible to accurately and quickly perform signal processing for reducing power consumption in the timing controller.

On the other hand, the timing controller extracts information on the first image frame data based on the second image frame data from the signal processing apparatus, and when the power information based on the luminance information in the extracted information exceeds the reference value, The luminance level of the first image frame data is lowered from the first level to the second level so that the power consumed by the panel is less than the allowable value, and the signal for the first image frame data whose luminance is changed to the second level is transferred to the panel. Can be printed. Accordingly, the timing controller can accurately and quickly perform signal processing for the panel. In particular, it is possible to accurately and quickly perform signal processing for reducing power consumption in the timing controller. In addition, it is possible to remove the memory from the timing controller.

On the other hand, the timing controller can control the power level consumed by the panel to be less than or equal to an allowable value based on the luminance information in the extracted information. Accordingly, it is possible to reduce the power consumption of the image display device.

On the other hand, the timing controller sets the luminance level of the partial region of the first image frame data to the first when the power information based on the luminance information on the partial region of the first image frame data exceeds the reference value based on the extracted information. A signal for a partial region of the first image frame data lowered from the level to the second level and whose luminance is changed to the second level may be output to the panel. Accordingly, the timing controller can accurately and quickly perform signal processing for the panel. In particular, it is possible to accurately and quickly perform signal processing for reducing power consumption in the timing controller. In addition, it is possible to remove the memory from the timing controller.

Meanwhile, when the image output mode of the signal processing apparatus is the first mode, the timing controller receives the first image frame data and the second image frame data, and based on the second image frame data, the timing controller receives the first image frame data. The signal-processed first image frame data is controlled to be displayed on the panel, and when the image output mode of the signal processing apparatus is the second mode, the received first image frame data without information on the second image frame data By signal processing, the signal-processed first image frame data may be controlled to be displayed on the panel. Accordingly, the amount of signal processing by the timing controller in the first mode and the second mode is different. In addition, in the second mode, the panel display time may be shorter than that in the first mode.

1 is a diagram illustrating an image display device according to an exemplary embodiment of the present invention.
2 is an example of an internal block diagram of the image display device of FIG. 1.
3 is an example of an internal block diagram of the signal processing unit of FIG. 2.
4A is a diagram illustrating a control method of the remote control device of FIG. 2.
4B is an internal block diagram of the remote control device of FIG. 2.
5 is an internal block diagram of the display of FIG. 2.
6A to 6B are views referenced for explanation of the organic light emitting panel of FIG. 5.
7A is a simplified block diagram of an image display device related to the present invention.
7B is a front view and a side view of the image display device of FIG. 7A.
8A to 8C are views referenced for explaining the operation of the image display device of FIG. 7A.
9A is a simplified block diagram of an image display device according to an embodiment of the present invention.
9B is a front view and a side view of the image display device of FIG. 9A.
10 is a detailed block diagram of an image display device according to an exemplary embodiment of the present invention.
11 is an example of an internal block diagram of a first image quality processor of FIG. 10.
12 is a flowchart illustrating a method of operating a signal processing apparatus according to an embodiment of the present invention.
13A to 14B are views referenced for describing the operation method of FIG. 12.
15A is a flowchart illustrating a method of operating a signal processing apparatus according to another embodiment of the present invention.
15B is a flowchart illustrating a method of operating a signal processing apparatus according to another embodiment of the present invention.
16A to 16B are views referenced for describing the operation method of FIG. 15A or 15B.
17 is a detailed block diagram of an image display device according to another exemplary embodiment of the present invention.
18A to 19D are views referenced for explanation of the operation of FIG. 17.
20 is a flowchart illustrating a method of operating a signal processing apparatus according to another embodiment of the present invention.
21A to 23C are views referenced for explanation of the operation method of FIG. 20.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

The suffixes "module" and "unit" for the constituent elements used in the following description are given in consideration of only the ease of writing in the present specification, and do not impart a particularly important meaning or role by themselves. Therefore, the "module" and "unit" may be used interchangeably with each other.

1 is a diagram illustrating an image display device according to an exemplary embodiment of the present invention.

Referring to the drawings, the image display device 100 may include a display 180.

The image display device 100 may receive image signals from various external devices, process them, and display them on the display 180.

Various external devices may be, for example, a computer (PC), a mobile terminal 600 such as a smart phone, a set-top box (STB), a game console (GSB), a server (SVR), and the like.

Meanwhile, the display 180 may be implemented with any one of various panels. For example, the display 180 may be any one of a self-luminous panel such as an organic light-emitting panel (OLED panel), an inorganic light-emitting panel (LED panel), and a micro LED panel.

In the present invention, description will be made focusing on that the display 180 includes an organic light emitting panel (OLED panel).

On the other hand, an organic light-emitting panel (OLED panel) has advantages in that panel response speed is faster than that of a liquid crystal display panel, has excellent color reproduction effect, and excellent color reproducibility.

Accordingly, when the display 180 includes an organic light emitting panel, it is preferable that the signal processing unit 170 of FIG. 2 in the image display device 100 performs image quality processing corresponding to the organic light emitting panel.

Meanwhile, the display 180 may include a panel and a timing controller, and an image can be displayed on the panel by signal processing by the timing controller.

Meanwhile, when the timing controller outputs an image signal to the panel, when using a memory, the image signal may be output to the panel by using data stored in the memory.

On the other hand, for slimming of the timing controller, when the timing controller does not use or does not have a memory, the amount of signal processing in the timing controller increases, and in particular, when the resolution of the image increases, the amount of signal processing is further increased. It will be.

Accordingly, in accordance with the trend of slimming timing controllers, the present invention proposes a method that enables the timing controller to accurately and quickly perform signal processing on the panel when the memory is not used or rarely used.

To this end, in the present invention, in addition to signal-processing the received image and outputting the signal-processed first frame image data, additionally, the down-scaled second image frame data is additionally output based on the received image. It suggests a way to do it.

The image display device 100 according to an embodiment of the present invention includes a signal processing device 170 in which a first image frame data ImgL is output after being delayed from a second image frame data ImgS, and a signal processing device. A timing controller 232 that performs signal processing based on an image signal output from 170 and a panel 210 that displays an image based on a signal from the timing controller 232 may be provided. Accordingly, the timing controller 232 can accurately and quickly perform signal processing for the panel 210.

Meanwhile, the signal processing device 170 in the image display device 100 according to an embodiment of the present invention includes an input interface (IIP) for receiving an image signal from the outside and a first image frame data based on the image signal. A first image processing unit 1010 that generates (ImgL), and a second image processing unit 1020 that generates second image frame data ImgS that is scaled down from the first image frame data ImgL based on the image signal. ), the first image frame data ImgL from the first image processing unit 1010 and the second image frame data ImgS from the second image processing unit 1020, and the first image frame data ImgL ) And an output interface (OIP) that outputs the second image frame data (ImgS), and the first image frame data (ImgL) output from the output interface (OIP) is delayed than the second image frame data (ImgS) And output. Accordingly, it is possible to output a signal to enable accurate and rapid signal processing in the timing controller. Meanwhile, the timing controller can accurately and quickly perform signal processing on the delayed output first image frame data ImgL based on the second image frame data ImgS. In particular, it is possible to accurately and quickly perform signal processing for reducing power consumption in the timing controller.

Meanwhile, the signal processing device 170 in the image display device 100 according to another embodiment of the present invention includes an input interface (IIP) for receiving an image signal from the outside, and the first image frame data ( A first image processing unit 1010 generating ImgL), a second image processing unit 1020 generating image frame data based on an image signal, and data divided into an active period HA and a blank period HB And an output interface (OIP) that outputs an enable signal (DE), a data signal of the first image frame data (ImgL), and a data signal of the second image frame data (ImgS), and the output interface (OIP) is , When only the data signal of the first image frame data ImgL is output, the active period HA of the first data enable signal DE is set to the first length Wa, and the first image frame data ImgL When the data signal of) and the data signal of the second image frame data ImgS are output together, the active period HA of the second data enable signal DE is set to a second greater than the first length Wa. It is set in length (Wb). Accordingly, it is possible to output a signal to enable accurate and rapid signal processing in the timing controller.

Meanwhile, the image display device 100 of FIG. 1 may be a TV, a monitor, a tablet PC, a mobile terminal, or a vehicle display device.

2 is an example of an internal block diagram of the image display device of FIG. 1.

Referring to FIG. 2, an image display device 100 according to an embodiment of the present invention includes an image receiving unit 105, an external device interface unit 130, a storage unit 140, a user input interface unit 150, and A sensor unit (not shown), a signal processing unit 170, a display 180, and an audio output unit 185 may be included.

The image receiving unit 105 may include a tuner unit 110, a demodulation unit 120, a network interface unit 130, and an external device interface unit 130.

Meanwhile, unlike the drawings, the image receiving unit 105 may include only the tuner unit 110, the demodulation unit 120, and the external device interface unit 130. That is, the network interface unit 130 may not be included.

The tuner unit 110 selects a channel selected by a user from among radio frequency (RF) broadcast signals received through an antenna (not shown) or an RF broadcast signal corresponding to all pre-stored channels. In addition, the selected RF broadcast signal is converted into an intermediate frequency signal or a baseband video or audio signal.

Meanwhile, the tuner unit 110 may include a plurality of tuners in order to receive broadcast signals of a plurality of channels. Alternatively, a single tuner that simultaneously receives broadcast signals of multiple channels is also possible.

The demodulation unit 120 receives the digital IF signal DIF converted by the tuner unit 110 and performs a demodulation operation.

The demodulator 120 may output a stream signal TS after performing demodulation and channel decoding. In this case, the stream signal may be a signal in which a video signal, an audio signal, or a data signal is multiplexed.

The stream signal output from the demodulation unit 120 may be input to the signal processing unit 170. The signal processing unit 170 performs demultiplexing, video/audio signal processing, and the like, and then outputs an image to the display 180 and outputs an audio to the audio output unit 185.

The external device interface unit 130 may transmit or receive data with a connected external device (not shown), for example, a set-top box (STB). To this end, the external device interface unit 130 may include an A/V input/output unit (not shown).

The external device interface unit 130 may be connected to an external device such as a digital versatile disk (DVD), a Blu ray, a game device, a camera, a camcorder, a computer (laptop), a set-top box, etc. by wire or wireless , It is also possible to perform input/output operations with external devices.

The A/V input/output unit may receive video and audio signals from an external device. Meanwhile, the wireless communication unit (not shown) may perform short-range wireless communication with another electronic device.

Through such a wireless communication unit (not shown), the external device interface unit 130 may exchange data with an adjacent mobile terminal 600. In particular, in the mirroring mode, the external device interface unit 130 may receive device information, executed application information, application image, and the like from the mobile terminal 600.

The network interface unit 135 provides an interface for connecting the image display device 100 to a wired/wireless network including an Internet network. For example, the network interface unit 135 may receive content or data provided by the Internet or a content provider or a network operator through a network.

Meanwhile, the network interface unit 135 may include a wireless communication unit (not shown).

The storage unit 140 may store a program for processing and controlling each signal in the signal processing unit 170 or may store a signal-processed video, audio, or data signal.

In addition, the storage unit 140 may perform a function for temporary storage of a video, audio, or data signal input to the external device interface unit 130. In addition, the storage unit 140 may store information on a predetermined broadcast channel through a channel storage function such as a channel map.

2 illustrates an embodiment in which the storage unit 140 is provided separately from the signal processing unit 170, but the scope of the present invention is not limited thereto. The storage unit 140 may be included in the signal processing unit 170.

The user input interface unit 150 transmits a signal input by the user to the signal processing unit 170 or transmits a signal from the signal processing unit 170 to the user.

For example, the remote control device 200 transmits/receives user input signals such as power on/off, channel selection, and screen setting, or local keys such as power keys, channel keys, volume keys, and set values (not shown). The user input signal input from the signal processing unit 170 is transmitted to the signal processing unit 170, or a user input signal input from a sensor unit (not shown) that senses the user's gesture is transmitted to the signal processing unit 170, or from the signal processing unit 170. The signal of may be transmitted to the sensor unit (not shown).

The signal processing unit 170, through the tuner unit 110, the demodulation unit 120, the network interface unit 135, or the external device interface unit 130, demultiplexes the input stream or processes demultiplexed signals. Thus, a signal for video or audio output can be generated and output.

For example, the signal processing unit 170 receives a broadcast signal or an HDMI signal received from the image receiving unit 105, performs signal processing based on the received broadcast signal or HDMI signal, and receives the processed image signal. Can be printed.

The image signal processed by the signal processor 170 may be input to the display 180 and displayed as an image corresponding to the corresponding image signal. In addition, the image signal processed by the signal processing unit 170 may be input to an external output device through the external device interface unit 130.

The audio signal processed by the signal processing unit 170 may be sound output to the audio output unit 185. In addition, the audio signal processed by the signal processing unit 170 may be input to an external output device through the external device interface unit 130.

Although not shown in FIG. 2, the signal processing unit 170 may include a demultiplexing unit, an image processing unit, and the like. That is, the signal processing unit 170 may perform various signal processing, and accordingly, may be implemented in the form of a system on chip (SOC). This will be described later with reference to FIG. 3.

In addition, the signal processing unit 170 may control the overall operation of the image display apparatus 100. For example, the signal processing unit 170 may control the tuner unit 110 to select (Tuning) an RF broadcast corresponding to a channel selected by the user or a pre-stored channel.

In addition, the signal processing unit 170 may control the image display apparatus 100 according to a user command or an internal program input through the user input interface unit 150.

Meanwhile, the signal processing unit 170 may control the display 180 to display an image. In this case, the image displayed on the display 180 may be a still image or a moving image, and may be a 2D image or a 3D image.

Meanwhile, the signal processing unit 170 may cause a predetermined object to be displayed in an image displayed on the display 180. For example, the object may be at least one of a connected web screen (newspaper, magazine, etc.), EPG (Electronic Program Guide), various menus, widgets, icons, still images, moving pictures, and text.

Meanwhile, the signal processing unit 170 may recognize a user's location based on an image captured by a photographing unit (not shown). For example, a distance (z-axis coordinate) between the user and the image display device 100 may be determined. In addition, x-axis coordinates and y-axis coordinates in the display 180 corresponding to the user's location may be identified.

The display 180 converts an image signal, a data signal, an OSD signal, a control signal or an image signal, a data signal, and a control signal received from the external device interface unit 130 to be processed by the signal processing unit 170 to provide a driving signal. Create

Meanwhile, the display 180 may be configured as a touch screen and used as an input device other than an output device.

The audio output unit 185 receives a signal processed by the signal processing unit 170 and outputs it as a voice.

The photographing unit (not shown) photographs the user. The photographing unit (not shown) may be implemented with one camera, but is not limited thereto, and may be implemented with a plurality of cameras. Image information captured by the photographing unit (not shown) may be input to the signal processing unit 170.

The signal processing unit 170 may detect a user's gesture based on an image captured from a photographing unit (not shown) or a signal detected from a sensor unit (not shown), or a combination thereof.

The power supply unit 190 supplies corresponding power throughout the image display device 100. In particular, the power supply unit 190 includes a signal processing unit 170 that can be implemented in the form of a System On Chip (SOC), a display 180 for displaying an image, and an audio output unit for outputting an audio. Power can be supplied to the back (185).

Specifically, the power supply unit 190 may include a converter that converts AC power into DC power and a dc/dc converter that converts the level of DC power.

The remote control device 200 transmits a user input to the user input interface unit 150. To this end, the remote control device 200 may use Bluetooth, Radio Frequency (RF) communication, infrared (IR) communication, Ultra Wideband (UWB), ZigBee, or the like. In addition, the remote control device 200 may receive an image, audio, or data signal output from the user input interface unit 150, and display or output an audio signal on the remote control device 200.

Meanwhile, the above-described image display device 100 may be a digital broadcast receiver capable of receiving a fixed or mobile digital broadcast.

Meanwhile, a block diagram of the image display device 100 shown in FIG. 2 is a block diagram for an embodiment of the present invention. Each component of the block diagram may be integrated, added, or omitted according to the specifications of the image display device 100 that is actually implemented. That is, if necessary, two or more components may be combined into one component, or one component may be subdivided into two or more components to be configured. In addition, functions performed by each block are for explaining the embodiments of the present invention, and specific operations or devices thereof do not limit the scope of the present invention.

3 is an example of an internal block diagram of the signal processing unit of FIG. 2.

Referring to the drawings, the signal processing unit 170 according to an embodiment of the present invention may include a demultiplexing unit 310, an image processing unit 320, a processor 330, and an audio processing unit 370. . In addition, a data processing unit (not shown) may be further included.

The demultiplexer 310 demultiplexes an input stream. For example, when an MPEG-2 TS is input, it can be demultiplexed and separated into video, audio, and data signals, respectively. Here, the stream signal input to the demultiplexer 310 may be a stream signal output from the tuner unit 110 or the demodulation unit 120 or the external device interface unit 130.

The image processing unit 320 may perform signal processing on an input image. For example, the image processing unit 320 may perform image processing of an image signal demultiplexed from the demultiplexer 310.

To this end, the image processing unit 320 includes an image decoder 325, a scaler 335, an image quality processing unit 635, an image encoder (not shown), an OSD processing unit 340, a frame rate conversion unit 350, and a formatter. (360) and the like.

The video decoder 325 decodes the demultiplexed video signal, and the scaler 335 performs scaling so that the resolution of the decoded video signal can be output from the display 180.

The video decoder 325 may include decoders of various standards. For example, an MPEG-2, H,264 decoder, a 3D image decoder for a color image and a depth image, a decoder for a multi-view image, and the like may be provided.

The scaler 335 may scale an input video signal that has been decoded by the video decoder 325 or the like.

For example, the scaler 335 may upscale when the size or resolution of the input image signal is small, and downscale when the size or resolution of the input image signal is large.

The image quality processing unit 635 may perform image quality processing on an input image signal that has been decoded by the image decoder 325 or the like.

For example, the image quality processing unit 635 may perform noise removal processing of the input image signal, extend the resolution of the grayscale of the input image signal, improve the image resolution, or perform high dynamic range (HDR)-based signal processing, or , The frame rate may be varied, or panel characteristics, in particular, image quality processing corresponding to the organic light emitting panel may be performed.

The OSD processing unit 340 generates an OSD signal by itself or according to a user input. For example, based on a user input signal, a signal for displaying various types of information as a graphic or text on the screen of the display 180 may be generated. The generated OSD signal may include various data such as a user interface screen, various menu screens, widgets, and icons of the image display device 100. In addition, the generated OSD signal may include a 2D object or a 3D object.

In addition, the OSD processing unit 340 may generate a pointer that can be displayed on the display based on the pointing signal input from the remote control device 200. In particular, such a pointer may be generated by a pointing signal processing unit, and the OSD processing unit 240 may include such a pointing signal processing unit (not shown). Of course, the pointing signal processing unit (not shown) may not be provided in the OSD processing unit 240 and may be provided separately.

The frame rate converter (FRC) 350 may convert a frame rate of an input image. On the other hand, the frame rate conversion unit 350 may output as it is without any separate frame rate conversion.

Meanwhile, the formatter 360 may change the format of an input image signal into an image signal for display on a display and output it.

In particular, the formatter 360 may change the format of the image signal to correspond to the display panel.

The processor 330 may control overall operations within the image display apparatus 100 or within the signal processing unit 170.

For example, the processor 330 may control the tuner unit 110 to select (Tuning) an RF broadcast corresponding to a channel selected by the user or a pre-stored channel.

In addition, the processor 330 may control the image display device 100 by a user command or an internal program input through the user input interface unit 150.

In addition, the processor 330 may control data transmission with the network interface unit 135 or the external device interface unit 130.

In addition, the processor 330 may control operations of the demultiplexer 310 and the image processor 320 in the signal processor 170.

Meanwhile, the audio processing unit 370 in the signal processing unit 170 may perform speech processing of the demultiplexed speech signal. To this end, the audio processing unit 370 may include various decoders.

In addition, the audio processing unit 370 in the signal processing unit 170 may process a base, a treble, and a volume control.

A data processing unit (not shown) in the signal processing unit 170 may perform data processing on a demultiplexed data signal. For example, when the demultiplexed data signal is an encoded data signal, it may be decoded. The encoded data signal may be electronic program guide information including broadcast information such as a start time and an end time of a broadcast program aired on each channel.

Meanwhile, a block diagram of the signal processing unit 170 shown in FIG. 3 is a block diagram for an embodiment of the present invention. Each component of the block diagram may be integrated, added, or omitted according to the specifications of the signal processing unit 170 that is actually implemented.

In particular, the frame rate converter 350 and the formatter 360 may be separately provided in addition to the image processing unit 320.

4A is a diagram illustrating a control method of the remote control device of FIG. 2.

As illustrated in (a) of FIG. 4A, a pointer 205 corresponding to the remote control device 200 is displayed on the display 180.

The user can move or rotate the remote control device 200 up and down, left and right (FIG. 4A (b)), and back and forth (FIG. 4A (c)). The pointer 205 displayed on the display 180 of the image display device corresponds to the movement of the remote control device 200. Since the corresponding pointer 205 is moved and displayed according to movement in 3D space, as shown in the drawing, the remote control device 200 may be referred to as a space remote controller or a 3D pointing device.

4A(b) illustrates that when the user moves the remote control device 200 to the left, the pointer 205 displayed on the display 180 of the image display device also moves to the left in response thereto.

Information on the movement of the remote control device 200 detected through the sensor of the remote control device 200 is transmitted to the image display device. The image display device may calculate the coordinates of the pointer 205 from information about the movement of the remote control device 200. The image display device may display the pointer 205 to correspond to the calculated coordinates.

4A (c) illustrates a case in which a user moves the remote control device 200 away from the display 180 while pressing a specific button in the remote control device 200. Accordingly, the selection area in the display 180 corresponding to the pointer 205 can be zoomed in and displayed in an enlarged manner. Conversely, when the user moves the remote control device 200 to be close to the display 180, the selection area in the display 180 corresponding to the pointer 205 may be zoomed out and displayed in a reduced size. On the other hand, when the remote control device 200 moves away from the display 180, the selection area is zoomed out, and when the remote control device 200 approaches the display 180, the selection area may be zoomed in.

On the other hand, when a specific button in the remote control device 200 is pressed, recognition of vertical and horizontal movement may be excluded. That is, when the remote control device 200 moves away from or approaches the display 180, up, down, left, and right movements are not recognized, and only forward and backward movements may be recognized. When a specific button in the remote control device 200 is not pressed, only the pointer 205 moves according to the up, down, left, and right movement of the remote control device 200.

Meanwhile, the moving speed or moving direction of the pointer 205 may correspond to the moving speed or moving direction of the remote control device 200.

4B is an internal block diagram of the remote control device of FIG. 2.

Referring to the drawings, the remote control device 200 includes a wireless communication unit 425, a user input unit 435, a sensor unit 440, an output unit 450, a power supply unit 460, a storage unit 470, It may include a control unit 480.

The wireless communication unit 425 transmits and receives a signal to and from any one of the image display apparatuses according to the embodiments of the present invention described above. Among the image display devices according to embodiments of the present invention, one image display device 100 will be described as an example.

In this embodiment, the remote control device 200 may include an RF module 421 capable of transmitting and receiving signals to and from the image display device 100 according to an RF communication standard. In addition, the remote control device 200 may include an IR module 423 capable of transmitting and receiving signals to and from the image display device 100 according to the IR communication standard.

In this embodiment, the remote control device 200 transmits a signal containing information about the movement of the remote control device 200 to the image display device 100 through the RF module 421.

In addition, the remote control device 200 may receive a signal transmitted from the image display device 100 through the RF module 421. In addition, the remote control device 200 may transmit a command regarding power on/off, channel change, volume change, etc. to the image display device 100 through the IR module 423 as needed.

The user input unit 435 may be composed of a keypad, a button, a touch pad, or a touch screen. A user may input a command related to the image display device 100 to the remote control device 200 by manipulating the user input unit 435. When the user input unit 435 includes a hard key button, the user can input a command related to the image display device 100 to the remote control device 200 through a push operation of the hard key button. When the user input unit 435 includes a touch screen, the user may input a command related to the image display device 100 to the remote control device 200 by touching a soft key on the touch screen. In addition, the user input unit 435 may include various types of input means that a user can manipulate, such as a scroll key or a jog key, and the present embodiment does not limit the scope of the present invention.

The sensor unit 440 may include a gyro sensor 441 or an acceleration sensor 443. The gyro sensor 441 may sense information about the movement of the remote control device 200.

For example, the gyro sensor 441 may sense information about the operation of the remote control device 200 based on the x, y, and z axes. The acceleration sensor 443 may sense information about a moving speed of the remote control device 200. Meanwhile, a distance measurement sensor may be further provided, thereby sensing a distance to the display 180.

The output unit 450 may output an image or audio signal corresponding to an operation of the user input unit 435 or a signal transmitted from the image display apparatus 100. Through the output unit 450, the user may recognize whether the user input unit 435 is manipulated or whether the image display device 100 is controlled.

As an example, the output unit 450 includes an LED module 451 that lights up when a user input unit 435 is manipulated or a signal is transmitted and received with the image display device 100 through the wireless communication unit 425, and a vibration module that generates vibration ( 453), a sound output module 455 that outputs sound, or a display module 457 that outputs an image.

The power supply unit 460 supplies power to the remote control device 200. The power supply unit 460 may reduce power waste by stopping power supply when the remote control device 200 is not moved for a predetermined period of time. The power supply unit 460 may resume power supply when a predetermined key provided in the remote control device 200 is operated.

The storage unit 470 may store various types of programs and application data necessary for controlling or operating the remote control device 200. If the remote control device 200 wirelessly transmits and receives signals through the image display device 100 and the RF module 421, the remote control device 200 and the image display device 100 transmit signals through a predetermined frequency band. Send and receive. The control unit 480 of the remote control device 200 stores information on the image display device 100 paired with the remote control device 200 and a frequency band through which signals can be transmitted and received wirelessly, in the storage unit 470, and You can refer to it.

The controller 480 controls all matters related to the control of the remote control device 200. The control unit 480 transmits a signal corresponding to a predetermined key operation of the user input unit 435 or a signal corresponding to the movement of the remote control device 200 sensed by the sensor unit 440 through the wireless communication unit 425. Can be transmitted to (100).

The user input interface unit 150 of the image display device 100 includes a wireless communication unit 151 capable of transmitting and receiving signals wirelessly with the remote control device 200, and a pointer corresponding to the operation of the remote control device 200. A coordinate value calculator 415 capable of calculating the coordinate value of may be provided.

The user input interface unit 150 may wirelessly transmit and receive signals with the remote control device 200 through the RF module 412. In addition, through the IR module 413, the remote control device 200 may receive a signal transmitted according to the IR communication standard.

The coordinate value calculation unit 415 corrects the hand shake or error from the signal corresponding to the operation of the remote control device 200 received through the wireless communication unit 151 and displays the coordinate value of the pointer 205 to be displayed on the display 170. (x,y) can be calculated.

The transmission signal of the remote control device 200 input to the image display device 100 through the user input interface unit 150 is transmitted to the signal processing unit 170 of the image display device 100. The signal processing unit 170 may determine information on an operation of the remote control device 200 and key manipulation from a signal transmitted from the remote control device 200 and control the image display device 100 in response thereto.

As another example, the remote control device 200 may calculate a pointer coordinate value corresponding to the operation and output it to the user input interface unit 150 of the image display device 100. In this case, the user input interface unit 150 of the image display apparatus 100 may transmit information on the received pointer coordinate value to the signal processing unit 170 without a separate hand shake or error correction process.

In addition, as another example, the coordinate value calculation unit 415 may be provided inside the signal processing unit 170 instead of the user input interface unit 150 unlike the drawing.

5 is an internal block diagram of the display of FIG. 2.

Referring to the drawings, an organic light-emitting panel-based display 180 includes an organic light-emitting panel 210, a first interface unit 230, a second interface unit 231, a timing controller 232, and a gate driver 234. , A data driver 236, a memory 240, a processor 270, a power supply unit 290, a current detection unit 510, and the like.

The display 180 may receive an image signal Vd, a first DC power supply V1 and a second DC power supply V2, and display a predetermined image based on the image signal Vd.

Meanwhile, the first interface unit 230 in the display 180 may receive an image signal Vd and a first DC power V1 from the signal processing unit 170.

Here, the first DC power V1 may be used for the operation of the power supply unit 290 and the timing controller 232 in the display 180.

Next, the second interface unit 231 may receive the second DC power V2 from the external power supply unit 190. Meanwhile, the second DC power V2 may be input to the data driver 236 in the display 180.

The timing controller 232 may output a data driving signal Sda and a gate driving signal Sga based on the image signal Vd.

For example, when the first interface unit 230 converts the input video signal Vd and outputs the converted video signal va1, the timing controller 232 is based on the converted video signal va1. Thus, the data driving signal Sda and the gate driving signal Sga may be output.

The timing controller 232 may further receive a control signal, a vertical synchronization signal Vsync, and the like in addition to the video signal Vd from the signal processing unit 170.

In addition, the timing controller 232 includes a gate driving signal Sga and data for the operation of the gate driver 234 based on a control signal, a vertical synchronization signal Vsync, and the like in addition to the video signal Vd. A data driving signal Sda for the operation of the driver 236 may be output.

In this case, the data driving signal Sda may be a data driving signal for driving an RGBW subpixel when the panel 210 includes an RGBW subpixel.

Meanwhile, the timing controller 232 may further output a control signal Cs to the gate driver 234.

The gate driving unit 234 and the data driving unit 236 are respectively provided through a gate line GL and a data line DL according to a gate driving signal Sga and a data driving signal Sda from the timing controller 232. , A scanning signal and an image signal are supplied to the organic light-emitting panel 210. Accordingly, the organic light emitting panel 210 displays a predetermined image.

Meanwhile, the organic light-emitting panel 210 may include an organic light-emitting layer, and in order to display an image, a plurality of gate lines GL and data lines DL are provided in a matrix form in each pixel corresponding to the organic light-emitting layer. Can be placed crosswise.

Meanwhile, the data driver 236 may output a data signal to the organic light emitting panel 210 based on the second DC power V2 from the second interface unit 231.

The power supply unit 290 may supply various types of power to the gate driver 234, the data driver 236, the timing controller 232, and the like.

The current detector 510 may detect a current flowing through the subpixels of the organic light emitting panel 210. The detected current may be input to the processor 270 or the like for calculating the accumulated current.

The processor 270 may perform various controls within the display 180. For example, the gate driver 234, the data driver 236, and the timing controller 232 may be controlled.

Meanwhile, the processor 270 may receive current information flowing through the subpixels of the organic light emitting panel 210 from the current detector 510.

Further, the processor 270 may calculate an accumulated current of the subpixels of each organic light emitting panel 210 based on current information flowing through the subpixels of the organic light emitting panel 210. The calculated accumulated current may be stored in the memory 240.

Meanwhile, when the accumulated current of the subpixels of each organic light emitting panel 210 is greater than or equal to the allowable value, the processor 270 may determine as burn-in.

For example, when the cumulative current of the subpixels of each organic light emitting panel 210 is 300000 A or more, the processor 270 may determine that the subpixel is burned-in.

Meanwhile, when the cumulative current of some of the subpixels of each organic light emitting panel 210 is close to an allowable value, the processor 270 may determine the corresponding subpixel as a subpixel for which burn-in is predicted.

Meanwhile, the processor 270 may determine the subpixel having the largest accumulated current as the burn-in prediction subpixel based on the current detected by the current detector 510.

6A to 6B are views referenced for explanation of the organic light emitting panel of FIG. 5.

First, FIG. 6A is a diagram illustrating a pixel in the organic light emitting panel 210.

Referring to the drawings, the organic light emitting panel 210 includes a plurality of scan lines (Scan 1 to Scan n) and a plurality of data lines (R1, G1, B1, W1 to Rm, Gm, Bm, Wm) intersecting them. It can be provided.

Meanwhile, a pixel (subpixel) is defined in an area at the intersection of the scan line and the data line in the OLED panel 210. In the drawing, a pixel Pixel including subpixels SR1, SG1, SB1, and SW1 of RGBW is shown.

6B illustrates a circuit of any one sub-pixel in the pixel of the organic light emitting panel of FIG. 6A.

Referring to the drawings, an organic light emitting sub-pixel circuit (CRTm) is an active type, and includes a scan switching element (SW1), a storage capacitor (Cst), a driving switching element (SW2), and an organic light emitting layer (OLED). I can.

The scan switching element SW1 has a scan line connected to a gate terminal and is turned on according to an input scan signal Vdscan. When turned on, the input data signal Vdata is transmitted to the gate terminal of the driving switching element SW2 or one end of the storage capacitor Cst.

The storage capacitor Cst is formed between the gate terminal and the source terminal of the driving switching element SW2, the data signal level transmitted to one end of the storage capacitor Cst, and a direct current transmitted to the other end of the storage capacitor Cst. Stores a predetermined difference in the power supply (VDD) level.

For example, when the data signal has different levels according to the Pluse Amplitude Modulation (PAM) method, the power level stored in the storage capacitor Cst varies according to the level difference of the data signal Vdata.

As another example, when the data signal has different lengths according to the PWM (Pluse Width Modulation) method, the power level stored in the storage capacitor Cst varies according to the difference in length of the data signal Vdata.

The driving switching element SW2 is turned on according to the power level stored in the storage capacitor Cst. When the driving switching element SW2 is turned on, a driving current IOLED, proportional to the stored power level, flows through the organic light emitting layer OLED. Accordingly, the organic light emitting layer OLED performs a light emission operation.

The organic light emitting layer (OLED) includes a light emitting layer (EML) of RGBW corresponding to a subpixel, and at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL) It may include, and may also include a hole blocking layer in addition.

Meanwhile, the sub-pixels all output white light from the organic light-emitting layer OLED, but in the case of green, red, and blue sub-pixels, a separate color filter is provided for color realization. That is, in the case of green, red, and blue subpixels, each further includes green, red, and blue color filters. On the other hand, in the case of a white subpixel, since white light is output, a separate color filter is not required.

Meanwhile, in the drawing, as the scan switching element SW1 and the driving switching element SW2, a case of a p-type MOSFET is exemplified, but an n-type MOSFET or other switching elements such as JFET, IGBT, or SIC are illustrated. It is also possible to be used.

Meanwhile, the pixel is a hold-type device that continuously emits light in the organic light emitting layer OLED during a unit display period, specifically during a unit frame, after a scan signal is applied.

Meanwhile, with the development of cameras and broadcasting technologies, the resolution and vertical synchronization frequency of an input video signal are increasing. In particular, there is a need for signal processing for an image signal having a resolution of 4K or higher and a vertical resolution of 120 Hz or higher. This will be described with reference to FIG. 7A below.

7A is a simplified block diagram of an image display device related to the present invention, and FIG. 7B is a front view and a side view of the image display device of FIG. 7A.

Referring to the drawings, an image display apparatus 100x according to the present invention includes a signal processing apparatus 170a and a display 180x.

The signal processing apparatus 170a processes the input video signal and outputs a signal-processed video (Img).

The display 180x includes a timing controller 232X and a panel 210, and the timing controller 232X receives the image Img from the signal processing device 170a, processes it, and displays it on the panel. Supply.

In particular, when the signal processing apparatus 170a outputs the image Img at the first time point, at the second time point, the timing controller 232X receives the image Img, and stores it in the internal memory MEM. It can be saved and output to the panel 210 at a third time point. Here, the first to the third viewpoint may be a viewpoint in units of frames.

That is, when the timing controller 232X in the display 180x has a memory MEM, after storing the image IMG related data in the memory MEM, after performing signal processing, the image data, for example, is For example, RGB data or RGBW data may be output to the panel 210.

As described above, when the timing controller 232X includes the memory MEM, the thickness of the timing controller 232X is Dax, as shown in FIG. 7B(b), and the thickness of the entire image display device 100x is , Dbx, it may become difficult to implement a slim image display device.

Accordingly, in the present invention, the operation of the signal processing apparatus 170 when the timing controller 232X does not include the memory MEM will be described. This will be described with reference to Fig. 9A or less.

8A to 8C are views referenced for explaining the operation of the image display device of FIG. 7A.

First, (a) of FIG. 8A shows an n-frame image (Imga) output from the signal processing apparatus 170a in the Pa1 period between the Ta1 and Ta2 points, and the signal processing in the Pb1 period between the Tb1 and Tb2 times. An example of outputting an n+1 frame image (Imgb) from the device 170a is illustrated.

Next, (b) of FIG. 8A shows an n-frame image Imga is stored in the memory MEM in the timing controller 232X in the Pa2 period between the time Ta3 and the time Ta4, and the Pb2 period between the time Tb3 and the time Tb4. In the example, the n+1 frame image Imgb is stored in the memory MEM in the timing controller 232X.

Next, (c) of FIG. 8A shows an n-frame image Imga is output from the memory MEM in the timing controller 232X to the panel 210 in the Pa3 period between the time Ta5 and the time Ta6, and the time Tb5 and the time Tb6. In the Pb3 period between time points, an n+1 frame image Imgb is output to the panel 210 from the memory MEM in the timing controller 232X.

8B, similarly to FIG. 8A, the signal processing apparatus 170a outputs a frame image, stores the frame image in a memory MEM in the timing controller 232X, and stores a memory MEM in the timing controller 232X. In this example, the frame image is output to the panel 210.

However, it is exemplified that the size of the frame image of FIG. 8B is larger than that of the frame image of FIG. 8A. Accordingly, there is a difference in that the output period, the storage period, and the like of FIG. 8B take more time than that of FIG. 8A.

That is, (a) of FIG. 8B shows an n-frame image (Imgc) output from the signal processing apparatus 170c in the Pc1 period between the Tc1 and Tc2 points, and in the Pd1 period between the Td1 and Td2 times, signal processing. An example of outputting an n+1 frame image (Imgd) from the device 170c is illustrated.

Next, (b) of FIG. 8B shows an n-frame image (Imgc) is stored in the memory (MEM) in the timing controller 232X in the Pc2 period between the time point Tc3 and the time point Tc4, and the Pd2 period between the time point Td3 and the time Td4. In the example, the n+1 frame image Imgd is stored in the memory MEM in the timing controller 232X.

Next, (c) of FIG. 8B shows an n-frame image Imgc is output to the panel 210 from the memory MEM in the timing controller 232X to the panel 210 in the Pc3 period between the time Tc5 and the time Tc6, and the time Td5 and Td6. In the Pd3 period between the viewpoints, an n+1 frame image Imgd is output from the memory MEM in the timing controller 232X to the panel 210.

That is, as shown in FIG. 8B, when the resolution of the image increases and the size of the image increases, a considerable amount of time is consumed when the frame image is stored in the memory MEM in the timing controller 232X and then output. .

8C illustrates the data enable signal FLx in the signal processing apparatus 170a when there is no memory MEM in the timing controller 232X.

As shown in the figure, the frame image ImgL is transmitted in the active period HAx among the active period HAx and the blank period HBx in the data enable signal FLx. Unlike FIG. 7A, the timing controller 232X When there is no memory MEM, the timing controller 232X has to process the received frame data in real time without storing, so that the amount of calculation of signal processing increases.

Accordingly, in the present invention, when the timing controller 232X does not include the memory MEM, the signal processing apparatus 170 outputs the first image frame data and the scaled-down second image frame data. present. This will be described with reference to Fig. 9A or less.

9A is a simplified block diagram of an image display device according to an embodiment of the present invention, and FIG. 9B is a front view and a side view of the image display device of FIG. 9A.

Referring to the drawings, an image display device 100 according to an embodiment of the present invention includes a signal processing device 170 and a display 180.

The signal processing apparatus 170 according to an exemplary embodiment of the present invention performs a new processing of an image signal from the outside, scales down the first image frame data ImgL and the first image frame data ImgL, The second image frame data ImgS is output.

In particular, the first image frame data ImgL and the second image frame data ImgS are output so that the transmission completion time of the second image frame data ImgS precedes the transmission completion time of the first image frame data ImgL. do.

Specifically, the first image frame data ImgL for the n-1 image frame and the second image frame data ImgS for the n image frames may be output together.

Meanwhile, the display 180 includes a timing controller 232 and a panel 210, and the timing controller 232 receives an image from the signal processing device 170, processes it, and supplies it to the panel. do.

In particular, the timing controller 232 does not include a memory MEM and does not store frame image data in the memory MEM.

Accordingly, the timing controller 232 according to an embodiment of the present invention uses the second image frame data data of the first image frame data data and the second image frame data data received from the signal processing device 170, The first image frame data is recognized, and signal processing is performed on the first image frame data.

In addition, the timing controller 232 may output the signal-processed first image frame data data, for example, RGB data or RGBW data to the panel 210.

As described above, when the timing controller 232X does not include the memory MEM, the thickness of the timing controller 232 is Da thinner than Dax of FIG. 7B, as shown in FIG. 9B (b), and the entire image is displayed. The thickness of the device 100x is Db, which is thinner than Dbx of FIG. 7B, and thus a slim image display device can be implemented.

On the other hand, the timing controller 232 receives the first image frame data ImgL and the second image frame data ImgS from the signal processing device 170, and in particular, the second image frame data ImgS. 1 Received before video frame data (ImgL).

For example, the timing controller 232 may receive first image frame data ImgL for n-1 image frames and second image frame data ImgS for n image frames at a first time point. In addition, at a second view point, first image frame data ImgL for n image frames and second image frame data ImgS for n+1 image frames may be received.

Accordingly, the timing controller 232 extracts and extracts information on the first image frame data (ImgL) of n image frames using the second image frame data (ImgS) for n image frames previously received. Based on the obtained information, after the second point in time, the first image frame data ImgL is signal-processed, and a signal for the signal-processed first image frame data ImgL may be output to the panel 210.

Accordingly, the timing controller 232 from which the memory has been removed can accurately and quickly perform signal processing for the panel 210. In addition, it is possible to prevent damage to the panel 210.

On the other hand, the timing controller 232 extracts information on the first image frame data ImgL based on the second image frame data ImgS from the signal processing device 170, and luminance information in the extracted information When the power information based on is greater than the reference value, the luminance level of the first image frame data ImgL is lowered from the first level to the second level so that the power level consumed by the panel 210 is less than or equal to the allowable value, A signal for the first image frame data ImgL whose luminance has been varied to the second level may be output to the panel 210. Accordingly, the timing controller 232 can accurately and quickly perform signal processing for the panel 210. In particular, the timing controller 232 can accurately and quickly perform signal processing for reducing power consumption. In addition, the memory 540 can be removed from the timing controller 232.

Meanwhile, the timing controller 232 may control the power level consumed by the panel 210 to be less than or equal to an allowable value based on the luminance information in the extracted information. Accordingly, power consumption of the image display device 100 can be reduced.

For example, when the luminance information in the extracted information exceeds the luminance reference value or the current reference value, the timing controller 232 may control the power level consumed by the panel 210 to be less than or equal to an allowable value. Accordingly, the timing controller 232 can accurately and quickly perform signal processing for reducing power consumption.

Meanwhile, when the luminance information in the extracted information exceeds the luminance reference value or the current reference value, the timing controller 232 lowers the luminance level of the first image frame data ImgL from the first level to the second level, A signal for the first image frame data ImgL whose luminance has been changed to the second level may be output to the panel 210. Accordingly, the timing controller 232 can accurately and quickly perform signal processing for reducing power consumption.

On the other hand, the timing controller 232, based on the extracted information, when the luminance information of the video frame of the first video frame data ImgL exceeds the luminance reference value or the current reference value, the first video frame data ImgL The luminance level of the image frame may be lowered from the first level to the second level, and a signal for the image frame of the first image frame data ImgL whose luminance is changed to the second level may be output to the panel 210. Accordingly, the timing controller 232 can accurately and quickly perform signal processing for reducing power consumption.

On the other hand, the timing controller 232, when the power information based on the luminance information for a partial region of the first image frame data ImgL based on the extracted information exceeds the reference value, the first image frame data ImgL The luminance level of a partial region of is lowered from the first level to the second level, and a signal for a partial region of the first image frame data ImgL whose luminance is changed to the second level may be output to the panel 210. Accordingly, the timing controller 232 can accurately and quickly perform signal processing for reducing power consumption.

Meanwhile, when the image output mode of the signal processing apparatus 170 is the first mode, the timing controller 232 receives the first image frame data ImgL and the second image frame data ImgS, and Based on the frame data ImgS, the first image frame data ImgL is signal-processed to control the signal-processed first image frame data ImgL to be displayed on the panel 210, and When the image output mode is the second mode, the received first image frame data (ImgL) is signal-processed without information on the second image frame data (ImgS), and the signal-processed first image frame data (ImgL) is It can be controlled to be displayed on the panel 210. Accordingly, the timing controller 232 can accurately and quickly perform signal processing for the panel 210.

10 is a detailed block diagram of an image display device according to an exemplary embodiment of the present invention.

Referring to the drawings, an image display device 100 according to an embodiment of the present invention includes a signal processing device 170 and a display 180.

The signal processing apparatus 170 according to an embodiment of the present invention includes an input interface (IIP) for receiving an external image signal, and a first image processing unit for generating first image frame data ImgL based on the image signal. (1010), a second image processing unit 1020 that generates second image frame data ImgS based on the image signal, first image frame data ImgL from the first image processing unit 1010, An output interface (OIP) for receiving the second image frame data ImgS from the second image processing unit 1020 and outputting the first image frame data ImgL and the second image frame data ImgS may be included. have.

Meanwhile, it is preferable that the first image frame data ImgL output from the output interface OIP is output after being delayed from the second image frame data ImgS.

Accordingly, the timing controller 232 extracts information from the first output second image frame data ImgS, and processes a signal on the received first image frame data ImgL based on the extracted information. Can be performed accurately and quickly. In particular, the timing controller 232 can accurately and quickly perform signal processing for reducing power consumption.

On the other hand, the output interface OIP includes the first image frame data ImgL and the second image so that the transmission completion time of the second image frame data ImgS precedes the transmission completion time of the first image frame data ImgL. Outputs frame data (ImgS). Accordingly, the timing controller 232 can accurately and quickly perform signal processing for the panel 210.

Meanwhile, the second image processing unit 1020 may output data having the same resolution as the first image frame data ImgL.

Alternatively, the second image processing unit 1020 may output data having a resolution smaller than that of the first image frame data ImgL.

To this end, the second image processing unit 1020 may generate and output second image frame data ImgS that is scaled down from the first image frame data ImgL.

Meanwhile, the input interface (IIP) may receive an image signal from a computer (PC), a mobile terminal (600), a set-top box (STB), a game console (GSB), a server (SVR), and the like of FIG. 1.

For example, when receiving an image signal encoded according to a transmission standard, the input interface (IIP) may perform decoding in accordance with a transmission standard.

Meanwhile, the signal processing apparatus 170 according to an embodiment of the present invention includes a preprocessor 515 that performs signal processing such as noise reduction, noise removal, and HDR signal processing on an image signal from an input interface (IIP). It may further include.

Meanwhile, the preprocessor 515 performs signal processing on the image signal from the input interface (IIP).

For example, when the received image signal is a decoded image signal, the preprocessor 515 may perform signal processing such as noise removal without a separate decoding process.

As another example, when the received image signal is an image signal encoded according to a video compression standard, the preprocessor 515 may perform decoding in accordance with the video compression standard after signal processing such as noise removal.

Meanwhile, the preprocessor 515 may perform HDR signal processing when the received image signal is an HDR image signal. To this end, the preprocessor 515 may include an HDR processing unit 705.

Meanwhile, the HDR processing unit 705 may receive an image signal and perform high dynamic range (HDR) processing on the input image signal.

For example, the HDR processing unit 705 may convert a standard dynamic range (SDR) image signal into an HDR image signal.

As another example, the HDR processing unit 705 may receive an image signal and perform grayscale processing for a high dynamic range on the input image signal.

Meanwhile, when the input image signal is an SDR image signal, the HDR processing unit 705 may bypass grayscale conversion, and when the input image signal is an HDR image signal, the HDR processing unit 705 may perform grayscale conversion. Accordingly, the timing controller can accurately and quickly perform signal processing for the panel.

On the other hand, the HDR processing unit 705 is a first grayscale conversion mode that emphasizes low grayscale among low grayscale and high grayscale and saturates high grayscale, or a second grayscale that is somewhat uniformly converted to the overall low grayscale and high grayscale. Based on the conversion mode, grayscale conversion processing can be performed.

Meanwhile, the signal processing apparatus 170 according to an embodiment of the present invention may further include a memory 540 for storing frame data for image processing by the first image processing unit 1010.

Alternatively, the memory 540 may be provided in the first image processing unit 1010 as shown in the drawing. That is, the first image processing unit 1010 in the signal processing apparatus 170 according to an embodiment of the present invention may include a memory 540 that stores frame data for image processing.

Meanwhile, since the frame data is stored in the memory 540 and then read, the first image frame data ImgL is output after being delayed from the second image frame data ImgS. Accordingly, the timing controller 232 can accurately and quickly perform signal processing for the panel 210.

Meanwhile, the second image processing unit 1020 may not include a memory for storing frame data.

Also, since the second image processing unit 1020 does not perform an operation related to storing the second frame data, the memory may not be used.

Accordingly, after outputting the second image frame data ImgS, the memory 540 may output the first image frame data ImgL.

Alternatively, the first image processing unit 1010 may output the first image frame data ImgL after outputting the second image frame data ImgS.

The first image processing unit 1010 may generate and output first image frame data ImgL based on the image signal processed by the preprocessor 515.

To this end, the first image processing unit 1010 includes a scaler 335 that scales an image signal to match the resolution of a panel, a frame rate converter 350 that operates to change a frame rate, and performs image quality processing. A first image quality processor 635a may be included.

Meanwhile, the first image processing unit 1010 may further include a memory 540 for storing frame data to vary the frame rate in the frame rate converter 350.

The second image processing unit 1020 may include a scaler 535 for scaling down an input image signal and a second image quality processing unit 635b for performing image quality processing.

Meanwhile, the scaler 535 may generate second image frame data ImgS that is scaled down from the first image frame data ImgL based on the image signal.

Meanwhile, the scaler 535 generates at least one super pixel 714 or a super block 724 based on some of the image blocks of the image signal, and includes a super pixel 714 or a super block 724 The scaled-down second image frame data ImgS may be output. Accordingly, compared to the first image frame data ImgL, the scaled-down second image frame data ImgS with reduced errors can be generated.

Meanwhile, the scaler 535 may change the size of the super pixel 714 or the super block 724 according to the resolution or image size of the image signal. Accordingly, compared to the first image frame data ImgL, the scaled-down second image frame data ImgS with reduced errors can be generated.

Meanwhile, the first image quality processing unit 635a performs image quality processing on the first image frame data ImgL, and the second image quality processing unit 635b performs image quality processing on the second image frame data ImgS. can do.

For example, the first image quality processing unit 635a and the second image quality processing unit 635b may perform signal processing such as noise reduction, 3D enhancement signal processing, luminance amplification, luminance expansion, and the like.

Meanwhile, the output interface OIP may receive first image frame data ImgL and second image frame data ImgS from the first image quality processor 635a and the second image quality processor 635b, respectively. have.

Meanwhile, the output interface OIP may output the first image frame data ImgL by delaying the second image frame data ImgS. Accordingly, the timing controller 232 can accurately and quickly perform signal processing for the panel 210.

Meanwhile, when the output first image frame data ImgL is n frame data, the output interface OIP may output frame data after n frame data as second image frame data ImgS. Accordingly, the timing controller 232 can accurately and quickly perform signal processing for the panel 210.

Meanwhile, the output interface OIP may simultaneously output first image frame data ImgL for n-1 image frames and second image frame data ImgS for n image frames. Accordingly, the timing controller 232 can accurately and quickly perform signal processing for the panel 210.

Meanwhile, the output interface (OIP) transmits a first output terminal (PNa) for transmission of a vertical synchronization signal (Vsync), a second output terminal (PNb) for transmission of a horizontal synchronization signal (Hsync), and an image data signal (Vdata). It may include a third output terminal PNc for and a fourth output terminal PNd for transmitting the data enable signal DE.

Meanwhile, the output interface OIP may transmit the first image frame data ImgL and the second image frame data ImgS through the third output terminal PNc. That is, the first image frame data ImgL and the second image frame data ImgS can be output through the same transmission line.

Meanwhile, the data enable signal DE may be divided into an active period HA and a blank period HB.

The timing controller 232 may receive the image data signal Vdata output from the third output terminal PNc in response to the active period HA of the data enable signal DE.

In particular, the timing controller 232 applies the video data for the first video frame data and the second video frame data in the video data signal Vdata, corresponding to the active period HA of the data enable signal DE. You can receive data about it.

On the other hand, the output interface (OIP) is compared to the first active period of the first data enable signal when only the first image frame data (ImgL) is output, the first image frame data (ImgL) and the second image frame data ( ImgS) is set so that the second active period of the second data enable signal is larger.

That is, the output interface OIP is the first image frame data ImgL and the second image frame than the length of the first active period of the first data enable signal when only the first image frame data ImgL is output. When the data ImgS is output, the length of the second active period of the second data enable signal is set to be larger.

Accordingly, it is possible to output the first image frame data ImgL and the second image frame data ImgS through the same transmission line.

On the other hand, the output interface (OIP) is compared to the first blank period of the first data enable signal when only the first image frame data (ImgL) is output, the first image frame data (ImgL) and the second image frame data ( When ImgS) is output, the second blank section of the second data enable signal is set to be smaller. Accordingly, it is possible to output the first image frame data ImgL and the second image frame data ImgS through the same transmission line. Then, the first image frame data ImgL is output after being delayed from the second image frame data ImgS.

Meanwhile, the output interface OIP may set the length of the active period HA of the data enable signal DE based on the resolution information of the panel 210 and the driving frequency of the panel 210. Accordingly, it is possible to output the first image frame data ImgL and the second image frame data ImgS through the same transmission line. Then, the first image frame data ImgL is output after being delayed from the second image frame data ImgS.

For example, the output interface OIP may control the length of the active period HA to decrease as the driving frequency of the panel 210 increases. Accordingly, it is possible to output the first image frame data ImgL and the second image frame data ImgS through the same transmission line.

As another example, the output interface OIP may control the length of the active period HA to decrease as the resolution information of the panel 210 increases. Accordingly, it is possible to output the first image frame data ImgL and the second image frame data ImgS through the same transmission line.

Meanwhile, when the resolution of the panel 210 is the first resolution and the driving frequency of the panel 210 is the first frequency, the output interface OIP sets an active period of the first length Wa, and the first When the image frame data ImgL and the second image frame data ImgS are output, an active period having a second length Wb greater than the first length Wa may be set. Accordingly, it is possible to output the first image frame data ImgL and the second image frame data ImgS through the same transmission line.

Meanwhile, the output interface OIP may set the active period of the second length by summing the period for transmitting the second image frame data ImgS to the active period of the first length Wa. Accordingly, it is possible to output the first image frame data ImgL and the second image frame data ImgS through the same transmission line.

On the other hand, in the output interface (OIP), when the resolution of the panel 210 is the first resolution and the driving frequency of the panel 210 is the first frequency, the active period of the first length Wa and the second length Wb ), and when outputting the first image frame data ImgL and the second image frame data ImgS, at least of the first image frame data ImgL during the active period of the first length Wa A part of the second image frame data ImgS may be transmitted during a part of the blank period of the second length Wb. Accordingly, it is possible to output the first image frame data ImgL and the second image frame data ImgS through the same transmission line.

On the other hand, the output interface (OIP), when the image output mode is the first mode, the first image frame data (ImgL) for the n-1 image frame and the second image frame data (ImgS) for the n image frames. When the image output mode is the second mode, the first image frame data (ImgL) for n image frames and the second image frame data (ImgS) for n image frames are output together, or the second Image frame data (ImgS) may not be output. Accordingly, the amount of signal processing of the timing controller 232 in the first mode and the second mode is different. In addition, the display timing of the panel 210 may be shorter in the second mode than in the first mode.

Here, the second mode is a low-delay mode, and may be a mode for reducing a delay of an image display point on the panel compared to an input image signal.

Meanwhile, all of the first modes are normal modes and may indicate a mode other than a low delay mode.

Meanwhile, the second mode or the low delay mode may include at least one of a game mode and a mirroring mode. Accordingly, the display timing of the panel 210 may be shorter in the second mode than in the first mode.

Meanwhile, the signal processing apparatus 170 according to another embodiment of the present invention includes an input interface (IIP) for receiving an external image signal and a first image frame data ImgL that generates first image frame data ImgL based on the image signal. 1 An image processing unit 1010, a second image processing unit 1020 that generates image frame data based on an image signal, and a data enable signal DE divided into an active period HA and a blank period HB And an output interface (OIP) for outputting a data signal of the first image frame data ImgL and a data signal of the second image frame data ImgS.

And, the output interface (OIP) in the signal processing apparatus 170 according to another embodiment of the present invention, when only the data signal of the first image frame data (ImgL) is output, the first data enable signal (DE) When the active period HA is set to the first length Wa and the data signal of the first image frame data ImgL and the data signal of the second image frame data ImgS are output together, the second data is The active period HA of the enable signal DE is set to a second length Wb that is greater than the first length Wa. Accordingly, it is possible to output a signal to enable accurate and rapid signal processing in the timing controller 232.

Meanwhile, the timing controller 232 can accurately and quickly perform signal processing on the delayed output first image frame data ImgL based on the second image frame data ImgS. In particular, the timing controller 232 can accurately and quickly perform signal processing for reducing power consumption.

11 is an example of an internal block diagram of a first image quality processor of FIG. 10.

Referring to the drawing, the first image quality processing unit 635a may include a first reduction unit 610, an enhancement unit 650, and a second reduction unit 690.

The first reduction unit 610 may perform noise removal on the image signal processed by the preprocessor 515.

For example, the first reduction unit 610 may perform the multi-stage noise removal process and the first-stage grayscale expansion process on the image processed by the preprocessor 515.

As another example, the first reduction unit 610 performs the multi-step noise removal processing and the first step gradation expansion processing for the HDR image processed by the HDR processing unit 705 in the preprocessor 515. can do.

To this end, the first reduction unit 610 may include a plurality of noise removing units 615 and 620 for removing noise in multiple stages, and a gray level expanding unit 625 for expanding gray levels.

Next, the enhancement unit 650 may perform multi-level image resolution enhancement processing on the image from the first reduction unit 610.

In addition, the enhancement unit 650 can perform an object three-dimensional effect improvement process. Further, the enhancement unit 650 can perform color or contrast enhancement processing.

To this end, the enhancement unit 650 includes a plurality of resolution enhancement units 635,638,642 for improving the image resolution in multiple steps, an object 3D enhancement unit 645 for improving the 3D effect of an object, and a color contrast enhancement unit for improving color or contrast (649) can be provided.

Next, the second reduction unit 690 may perform a second step gray scale expansion process based on the noise-removed image signal input from the first reduction unit 610.

Meanwhile, the second reduction unit 690 may amplify an upper limit level of a gray scale of an input signal and extend a resolution of a gray scale of the input signal. Accordingly, the timing controller can accurately and quickly perform signal processing for the panel.

For example, it is possible to uniformly perform gray scale expansion on the entire gray scale area of the input signal. Accordingly, it is possible to increase the expressive power of high gradation while uniform gradation expansion is performed on the region of the input image.

Meanwhile, the second reduction unit 690 may include a second gradation expansion unit 629 that performs gradation amplification and expansion based on an input signal from the first gradation expansion unit 625. Accordingly, the timing controller can accurately and quickly perform signal processing for the panel.

Meanwhile, the second reduction unit 690 may vary the degree of amplification when the input image signal is an SDR image signal based on a user input signal. Accordingly, it is possible to increase the expressive power of high gradations in response to user settings.

Meanwhile, when the input image signal is an HDR image signal, the second reduction unit 690 may perform amplification according to a set value. Accordingly, the timing controller can accurately and quickly perform signal processing for the panel.

Meanwhile, the second reduction unit 690 may vary the degree of amplification when the input image signal is an HDR image signal based on a user input signal. Accordingly, it is possible to increase the expressive power of high gradations in response to user settings.

On the other hand, the second reduction unit 690 may change the degree of gray scale expansion when the gray scale is expanded based on a user input signal. Accordingly, it is possible to increase the expressive power of high gradations in response to user settings.

Meanwhile, the second reduction unit 690 may amplify the upper limit level of the gradation according to the gradation conversion mode in the HDR processing unit 705. Accordingly, the timing controller can accurately and quickly perform signal processing for the panel.

Meanwhile, as shown in FIG. 11, the first image quality processing unit 635a in the signal processing apparatus 170 of the present invention is characterized in that it performs 4 steps of reduction processing and 4 steps of image enhancement processing.

Here, the fourth step reduction processing may include a second step of noise removal processing and a second step of gradation expansion processing.

Here, the noise removal processing in the second step is performed by the first and second noise removal units 615 and 620 in the first reduction unit 610, and the gray scale expansion processing in the second step is performed by the first reduction unit 610. The first grayscale expansion unit 625 and the second grayscale expansion unit 629 in the second reduction unit 690 may perform this operation.

On the other hand, the fourth step image enhancement processing may include a third step image resolution enhancement processing and an object three-dimensional effect enhancement processing.

Here, the image resolution enhancement processing of the third step is processed by the first to third resolution enhancement units 635,638, and 642, and the object 3D effect enhancement processing may be processed by the object 3D effect enhancement unit 645.

12 is a flowchart illustrating a method of operating a signal processing apparatus according to an exemplary embodiment of the present invention, and FIGS. 13A to 14B are views referenced for explanation of the operation method of FIG.

First, referring to FIG. 12, an input interface (IIP) in the signal processing apparatus 170 according to an embodiment of the present invention receives an image signal from the outside (S710).

The input interface (IIP) may receive an image signal from a computer (PC), mobile terminal 600, set-top box (STB), game console (GSB), server (SVR), and the like of FIG. 1.

For example, when receiving an image signal encoded according to a transmission standard, the input interface (IIP) may perform decoding according to the transmission standard.

Next, the first image processing unit 1010 generates first image frame data ImgL based on the image signal from the input interface IIP (S720).

Next, the scaler 535 in the second image processing unit 1020 generates the scaled-down second image frame data ImgS based on the image signal from the input interface IIP (S730).

For example, the scaler 535 generates at least one super pixel 714 or super block 724 based on some of the image blocks of the image signal, and the super pixel 714 or the super block 724 The scaled-down second image frame data ImgS may be output. Accordingly, compared to the first image frame data ImgL, it is possible to generate the scaled-down second image frame data ImgS with a reduced error.

Next, the output interface OIP outputs the first image frame data ImgL and the second image frame data ImgS (S740).

For example, the first image frame data ImgL output from the output interface OIP is output after being delayed from the second image frame data ImgS. Accordingly, it is possible to output a signal to enable accurate and rapid signal processing in the timing controller 232.

Meanwhile, the timing controller 232 can accurately and quickly perform signal processing on the delayed output first image frame data ImgL based on the second image frame data ImgS. In particular, the timing controller 232 can accurately and quickly perform signal processing for reducing power consumption.

On the other hand, the output interface OIP includes the first image frame data ImgL and the second image so that the transmission completion time of the second image frame data ImgS precedes the transmission completion time of the first image frame data ImgL. Outputs frame data (ImgS). Accordingly, the timing controller 232 can accurately and quickly perform signal processing for the panel 210.

13A illustrates a data enable signal Flam when the output interface OIP outputs only the first image frame data ImgL.

Referring to the drawing, the data enable signal Flam may be divided into an active period HA and a blank period HB.

The output interface OIP may set the length of the active period HA based on the resolution information of the panel 210 and the driving frequency of the panel 210.

For example, the output interface OIP may control the length of the active period HA to decrease as the driving frequency of the panel 210 increases. Accordingly, it is possible to output the first image frame data ImgL and the second image frame data ImgS through the same transmission line.

Meanwhile, the output interface OIP may control the length of the active period HA to decrease as the resolution information of the panel 210 increases. Accordingly, it is possible to output the first image frame data ImgL and the second image frame data ImgS through the same transmission line.

The output interface OIP outputs some data Sgla of the first image frame data ImgL to the first active period HA, and other partial data of the first image frame data ImgL, as shown in FIG. 13A. (Sglb) may be output in the second active period HA.

That is, the output interface OIP may divide and output the image data of the first image frame data ImgL during a plurality of active periods, as shown in FIG. 13A.

13B illustrates a data enable signal Flana when the output interface OIP outputs first image frame data ImgL and second image frame data ImgS.

Referring to the drawing, the data enable signal Flana may be divided into an active period HAa and a blank period HBa.

Referring to the drawing, the output interface (OIP) is, by summing the section (HSs) for transmitting the second image frame data (ImgS) to the active section (HSI) of the first length (Wa), the second length (Wb) The active period HAa of) can be set.

On the other hand, the output interface OIP may set a blank section HBa of a fourth length Wd that is reduced than the third length Wc according to an increase in the active section HAa.

In this case, the section HSs for transmitting the second image frame data ImgS may be disposed after the active section HSI of the first length Wa.

On the other hand, comparing FIGS. 13A and 13B, the first image frame data ImgL is compared to the first active period HA of the first data enable signal FLam when only the first image frame data ImgL is output. The second active period HAa of the second data enable signal FLana when) and the second image frame data ImgS are output may be larger.

Accordingly, it is possible to output the first image frame data ImgL and the second image frame data ImgS through the same transmission line. In this case, it is preferable that the first image frame data ImgL is output after being delayed than the second image frame data ImgS.

On the other hand, comparing FIGS. 13A and 13B, the first image frame data ImgL is compared to the first blank period HB of the first data enable signal FLam when only the first image frame data ImgL is output. ) And the second image frame data ImgS may have a smaller second blank period HBa of the second data enable signal FLana. Accordingly, it is possible to output the first image frame data ImgL and the second image frame data ImgS through the same transmission line.

13C illustrates a data enable signal Flab when the output interface OIP outputs first image frame data ImgL and second image frame data ImgS.

Referring to the drawing, the data enable signal Flab may be divided into an active period HAa and a blank period HBa.

Referring to the drawing, the output interface (OIP) is, by summing the section (HSs) for transmitting the second image frame data (ImgS) to the active section (HSI) of the first length (Wa), the second length (Wb) The active period HAa of) can be set.

On the other hand, the output interface OIP may set a blank section HBa of a fourth length Wd that is reduced than the third length Wc according to an increase in the active section HAa.

In this case, the section HSs for transmitting the second image frame data ImgS may be disposed before the active section HSI of the first length Wa.

13D illustrates a data enable signal Flanc when the output interface OIP outputs first image frame data ImgL and second image frame data ImgS.

Referring to the drawing, the data enable signal Planc may be divided into an active period HA and a blank period HB.

Referring to the drawing, the output interface OIP outputs some data Sgla of the first image frame data ImgL in a first active period HA of a first length Wa, and a third length ( During the first blank period HB of Wc), some data Sgsa of the second image frame data ImgS is output.

In the drawing, it is exemplified that some data Sgsa of the second image frame data ImgS is output during the HSs period set during the first blank period HB.

Thereafter, in the second active period HA of the first length Wa, some other data Sglb of the first image frame data ImgL is output, and the second blank period ( HB), other partial data Sgsb of the second image frame data ImgS is output. Accordingly, accordingly, the first image frame data ImgL and the second image frame data ImgS can be output through the same transmission line.

13E is a diagram illustrating various data enable signals FLana, FLanb, and FLanc output from the signal processing apparatus 170.

Referring to the drawing, the data enable signal FLana of FIG. 13E(a) is divided into an active period HAa and a blank period HBa, and at the front end of the active period HAa, the first image frame data An example of outputting data and outputting the second image frame data data at a later stage in the active period HAa is illustrated.

When the outputted second image frame data data is added during the plurality of active periods HAa, LNSa data as shown in the figure is generated.

Referring to the drawing, the data enable signal FLanb of FIG. 13E(b) is divided into an active period HAa and a blank period HBa, and at the rear end of the active period HAa, first image frame data An example of outputting the data and outputting the second image frame data data to the front end in the active period HAa is illustrated.

Referring to the drawing, the data enable signal FLanc of FIG. 13E(c) is divided into an active period HA and a blank period HB, and the first image frame data data is output in the active period HA. And, it exemplifies outputting the second image frame data data in the middle of the blank section HB.

14A is a diagram illustrating various data enable signals (TCam, TCbm, TCcm) output from the signal processing apparatus 170 when the resolution of the panel 210 is 8K and the panel driving frequency is 120 Hz.

Referring to the drawing, when the resolution of the panel 210 is 8K and the panel driving frequency is 120 Hz, the output interface OIP has an active period HAm of the data enable signal TCam of approximately 125 ms, and a blank period. (HBm) is approximately 15 ms, and the output section of the second image frame data data may be set to approximately 3 ms.

As shown in the figure, part of the first image frame data data (ImgLa) is transmitted to the front end in the active period (HAm), and part of the second image frame data data (ImgSa) is transmitted to the rear end in the active period (HAm). Can be.

14B is a diagram illustrating various data enable signals TCan, TCbn, and TCcn output from the signal processing apparatus 170 when the resolution of the panel 210 is 4K and the panel driving frequency is 120 Hz.

Referring to the drawing, when the resolution of the panel 210 is 4K and the panel driving frequency is 120 Hz, the output interface OIP has an active period HAn of the data enable signal TCan of approximately 250 ms, and a blank period. (HBn) is approximately 30 ms, and the output section of the second image frame data data may be set to approximately 5 ms.

As shown in the figure, a part of the first image frame data data (ImgL) is transmitted to the front end in the active period (HAn), and a part of the second image frame data data (ImgS) is transmitted to the rear end in the active period (HAn). Can be.

Comparing FIGS. 14A and 14B, as shown in FIG. 14A, as the panel resolution increases, the output interface OIP may be set to decrease the length of the active period. Also, the length of the blank section can be set to decrease. In addition, the output section of the second image frame data data may be set to decrease.

Similarly, as the driving frequency of the panel 210 increases, the output interface OIP may be set to decrease the length of the active period. Also, the length of the blank section can be set to decrease.

15A is a flowchart illustrating a method of operating a signal processing apparatus according to another embodiment of the present invention.

Referring to the drawings, the signal processing apparatus 170 determines whether the image output mode is a first mode (S810) and, if applicable, controls to perform step 840 (S840).

That is, when the image output mode is the first mode, the signal processing apparatus 170 outputs first image frame data of a first size and second image frame data of a second size (S840).

Here, the first mode may include modes other than the game mode and the mirroring mode.

When the image output mode is the first mode, the output interface (OIP) outputs the first image frame data (ImgL) for n-1 image frames and the second image frame data (ImgS) for n image frames together. can do.

Meanwhile, when the image output mode is not the first mode, the signal processing apparatus 170 determines whether the image output mode is the second mode (S820), and, if applicable, outputs the first image frame data of the first size. (S830).

Here, the second mode may include a game mode and a mirroring mode. That is, the second mode may be a mode for displaying an image by real-time signal processing.

For example, when receiving a game video signal from an external device, a streaming game video signal from an external server, or displaying a mobile terminal screen as it is by a mirroring mode such as an external mobile terminal, the signal processing device 170 ) Causes the scaler 535 to be bypassed so that the scaled-down image is not generated.

Meanwhile, when the image output mode is the second mode, the signal processing apparatus 170 stores first image frame data ImgL for n image frames and second image frame data ImgS for n image frames. Together, the second image frame data ImgS may not be output.

Accordingly, the amount of signal processing of the timing controller 232 in the first mode and the second mode is different. In addition, when the same image is displayed in the second mode than in the first mode, the display time of the panel 210 may be shorter.

15B is a flowchart illustrating a method of operating a signal processing apparatus according to another embodiment of the present invention.

Referring to the drawings, the signal processing apparatus 170 determines whether the image output mode is a first mode (S810) and, if applicable, controls to perform step 845 (S845).

That is, when the image output mode is the first mode, the signal processing apparatus 170 includes an active section HAa having a second length Wb greater than the first length Wa, as shown in FIG. 13B or 13C, and A second signal FLana including a blank section HBa having a fourth length Wd smaller than the third length Wc is output (S845).

For example, when the image output mode is the first mode, the output interface OIP includes first image frame data ImgL for n-1 image frames and second image frame data ImgS for n image frames. ) Can be printed together. Accordingly, it is possible to output the first image frame data ImgL and the second image frame data ImgS through the same transmission line.

Meanwhile, when the image output mode is not the first mode, the signal processing apparatus 170 determines whether the image output mode is the second mode (S820), and if applicable, the first length Wa as shown in FIG. 13A. The first signal FLam including the active period HA and the blank period HB of the third length Wc is output (S835).

16A to 16B are views referenced for describing the operation method of FIG. 15A or 15B.

16A illustrates that the signal processing apparatus 170 outputs only the first image frame data ImgL according to the second mode.

Referring to the drawings, the second image processing unit 1020 in the signal processing apparatus 170 does not generate or output second image frame data, and the first image frame data generated by the first image processing unit 1010 is 1 It is output to the outside through path1 of the image processing unit 1010 and the output interface OIP.

In this case, the scaler 335 of the first image processing unit 1010, the frame rate converter 350, and the first image quality processing unit 635a may be passed through.

16B illustrates that the signal processing apparatus 170 outputs first image frame data ImgL and second image frame data ImgS according to the first mode.

Referring to the drawings, a second image processing unit 1020 in the signal processing apparatus 170 generates second image frame data.

Accordingly, the first image frame data generated by the preprocessor 515 is output to the outside through path1 of the first image processing unit 1010 and the output interface (OIP), and is generated by the second image processing unit 1020. The second image frame data is output to the outside through path2 of the second image processing unit 1020 and the output interface OIP.

17 is a detailed block diagram of an image display device according to another exemplary embodiment of the present invention, and FIGS. 18A to 19D are views referenced for explanation of the operation of FIG. 17.

Referring to the drawings, the image display device 100b according to another embodiment of the present invention of FIG. 17 is similar to the image display device 100 of FIG. 10, but the output interface OIPb in the signal processing device 170b is , Compared to FIG. 10, there is a difference in having more output terminals. Hereinafter, the difference will be mainly described.

The signal processing apparatus 170b according to another embodiment of the present invention includes an input interface (IIP) for receiving an external image signal, and a first image for generating first image frame data ImgL based on the image signal. The processing unit 1010, a second image processing unit 1020 that generates second image frame data ImgS based on the image signal, the first image frame data ImgL from the first image processing unit 1010, and , An output interface (OIP) for receiving the second image frame data ImgS from the second image processing unit 1020 and outputting the first image frame data ImgL and the second image frame data ImgS. I can.

Meanwhile, the output interface OIPb includes a first output terminal (PNa) for transmitting a vertical synchronization signal (Vsync), a second output terminal (PNb) for transmitting a horizontal synchronization signal (Hsync), and a first image frame data (ImgL). ), a third output terminal (PNc) for transmitting the data signal (Vdata), a fourth output terminal (PNd) for transmitting the data enable signal (DE) of the first image frame data (ImgL), and the second image frame data It may include a fifth output terminal PMe for transmitting the data signal Sdata of (ImgS), and a sixth output terminal PMf for transmitting the data enable signal DEb of the second image frame data ImgS. have.

Accordingly, the first image frame data ImgL is output through the third output terminal PNc based on the first data enable signal DE, and the second image frame data ImgS is Based on the data enable signal DEb, it is possible to output through the fifth output terminal PMe.

That is, the output interface OIPb may output the first image frame data ImgL and the second image frame data ImgS using different output terminals.

Meanwhile, since the first image frame data ImgL and the second image frame data ImgS are output through different output terminals, the second image frame data ImgS is not limited to scaling down frame data.

That is, the second image processing unit 1020 in the signal processing apparatus 170b according to another embodiment of the present invention of FIG. 17 may output second image frame data that is not scaled down. Hereinafter, for convenience of description, it is assumed that the scaled-down second image frame data is output.

18A illustrates that the signal processing apparatus 170b outputs only the first image frame data ImgL according to the second mode.

Referring to the drawing, the second image processing unit 1020 in the signal processing apparatus 170b does not generate or output the second image frame data, and the first image frame data (ImgL) generated by the first image processing unit 1010 ) Is output to the outside through path1 of the first image processing unit 1010 and the output interface OIPb.

18B illustrates that the signal processing apparatus 170b outputs first image frame data ImgL and second image frame data ImgS according to the first mode.

Referring to the drawing, the second image processing unit 1020 in the signal processing apparatus 170b generates second image frame data ImgS.

Accordingly, the first image frame data ImgL generated by the first image processing unit 1010 is output to the outside through path1 of the first image processing unit 1010 and the output interface OIPb, and the second image processing unit The second image frame data ImgS generated at 1020 is output to the outside through path2 of the second image processing unit 1020 and the output interface OIPb. Accordingly, the first image frame data ImgL and the second image frame data ImgS can be output through different transmission lines.

19A illustrates a data enable signal FLana output from the fourth output terminal PNd of the signal processing apparatus 170b according to the second mode.

Referring to the drawing, some data (Sgla, Sglb) of the first image frame data (ImgL) in synchronization with the active period (HA) of the active period (HA) and the blank period (HB) of the data enable signal (FLana) Is displayed.

19B is a data enable signal FLana output from the fourth output terminal PNd of the signal processing apparatus 170b and a second data enable signal output from the sixth output terminal PNf according to the first mode ( FLanb) is illustrated.

Referring to the drawing, some data (Sgla, Sglb) of the first image frame data (ImgL) in synchronization with the active period (HA) of the active period (HA) and the blank period (HB) of the data enable signal (FLana) Is output, and some data Sgsa and Sgsb of the second image frame data ImgS are output in synchronization with the active period Hak of the second data enable signal FLanb.

In particular, the second data enable signal FLanb has an active period Hak, corresponding to a rear end of the data enable signal FLana, and then has a blank period HBk.

According to the second data enable signal FLanb, the blank period HBk appears longer than the active period Hak.

19C is a data enable signal FLana output from the fourth output terminal PNd of the signal processing apparatus 170b and a second data enable signal output from the sixth output terminal PNf according to the first mode ( FLanb2) is illustrated.

Referring to the drawing, the second data enable signal FLanb2 is similar to the second data enable signal FLanb of FIG. 19B, but corresponds to the front end in the data enable signal FLana, and the active period Hak And, after that, has a blank section HBk.

Accordingly, in synchronization with the active period Hak of the second data enable signal FLanb2, some data Sgsa and SGSb of the second image frame data ImgS are output.

19D is a data enable signal FLana output from the fourth output terminal PNd of the signal processing apparatus 170b and a second data enable signal output from the sixth output terminal PNf according to the first mode ( FLanb3) is illustrated.

Referring to the drawing, the second data enable signal FLanb3 has an active period Hak, corresponding to a part of the blank period HB of the data enable signal FLana, and thereafter, the blank period HBk ).

Accordingly, in synchronization with the active period Hak of the second data enable signal FLanb3, some data Sgsa and SGSb of the second image frame data ImgS are output.

20 is a flowchart illustrating a method of operating a signal processing apparatus according to another embodiment of the present invention, and FIGS. 21A to 23C are views referenced for explanation of the operation method of FIG. 20.

First, referring to FIG. 20, the second image processing unit 1020 in the signal processing apparatus 170 according to another embodiment of the present invention receives an image signal from an input interface (IIP) or a preprocessor 515. (S732).

In addition, the scaler 535 in the second image processing unit 1020 extracts some of the image blocks of the input image signal (S734). In this case, the image signal may correspond to the first image frame data.

Next, the scaler 535 generates at least one adaptive super pixel 714 or an adaptive super block 722 based on the extracted partial blocks (S735).

21A shows a 1*1 sized super pixel 714 representing block characteristics is generated from an axb block 712 in the first image frame data 710, and based on the super pixel 714, a second image frame It illustrates generating data 715.

21B shows a c*d-sized super block 724 representing block characteristics in the axb block 722 in the first image frame data 720, and based on the super block 724, a second image frame Creating data 728 is illustrated.

FIG. 21C shows that a super pixel 734 having a size of 1*1 representing a block characteristic is generated from a 4×4 block 732 in the first image frame data 730, and based on the super pixel 734, a second The generation of the image frame data 736 is illustrated.

21D shows a 4*4 sized super block 744 representing block characteristics from a 16×16 block 742 in the first image frame data 740, and based on the super block 744, a second block 744 is generated. The generation of the image frame data 746 is illustrated.

When the second image frame data is generated using such a super pixel or a super block, there is an advantage in that a prediction error for the first image frame data information is minimized.

FIG. 23A illustrates that 1K second image frame data 912,922,932 is generated by downscaling various first image frame data 910,920,930 of 4K using a filtering technique such as Bilinear or PolyPhase.

As shown in FIG. 23A, when downscaling the first image frame data of various patterns using a filtering technique, second image frame data in which the pattern is not clearly revealed is generated as shown in FIGS. 23A(d) and (e). Can be.

FIG. 23B illustrates that 1K of second image frame data 942 and 952 is generated by down-scaling various first image frame data 940 and 950 of 4K using an adaptive super pixel.

As shown in FIG. 23B, when downscaling the first image frame data of various patterns using adaptive super pixels, the pattern is clearly revealed in FIG. 23B(d), but as shown in FIG. 23B(c), the pattern This may not be obvious.

FIG. 23C exemplifies the creation of 1K second image frame data 962,972 by downscaling various first image frame data 960 and 970 of 4K using an adaptive super block.

As shown in FIG. 23C, when downscaling the first image frame data of various patterns using an adaptive super block, the pattern is clearly revealed as in (c) and (d) of FIG. 23C.

Therefore, it is preferable that the scaler 535 generates second image frame data using an adaptive super block. Accordingly, it is possible to generate the scaled-down second image frame data with reduced errors.

Meanwhile, the scaler 535 may generate second image frame data using an adaptive super pixel.

In addition, although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the technical field to which the present invention belongs without departing from the gist of the present invention claimed in the claims. In addition, various modifications are possible by those of ordinary skill in the art, and these modifications should not be understood individually from the technical spirit or prospect of the present invention.

Claims (27)

An input interface for receiving an image signal from the outside;
A first image processing unit generating first image frame data based on the image signal;
A second image processing unit configured to generate second image frame data scaled down from the first image frame data based on the image signal;
An output interface for receiving the first image frame data from the first image processing unit and the second image frame data from the second image processing unit, and outputting the first image frame data and the second image frame data Including ;,
The signal processing apparatus, wherein the first image frame data output from the output interface is output after being delayed from the second image frame data. The method of claim 1,
The signal processing apparatus, characterized in that the first image frame data output from the first image processing unit is output after being delayed than the second image frame data output from the second image processing unit. The method of claim 1,
The output interface,
And outputting the first image frame data with a delay from that of the second image frame data. The method of claim 1,
The output interface,
When the first image frame data to be output is n frame data, the signal processing apparatus outputs frame data after the n frame data as the second image frame data. The method of claim 1,
And a memory for storing frame data for image processing by the first image processing unit. The method of claim 1,
The output interface,
A signal processing apparatus comprising: outputting the first image frame data for the n-1 image frame and the second image frame data for the n image frames together. The method of claim 1,
The output interface,
A first output terminal for transmitting a vertical synchronization signal, a second output terminal for transmitting a horizontal synchronization signal, a third output terminal for transmitting an image data signal, and a fourth output terminal for transmitting a data enable signal,
And transmitting the first image frame data and the second image frame data through the third output terminal. The method of claim 1,
The output interface,
Outputs a data enable signal divided into an active section and a blank section,
Than the first active period of the first data enable signal when only the first image frame data is output,
And a second active period of the second data enable signal when the first image frame data and the second image frame data are output is larger. The method of claim 1,
The output interface,
Outputs a data enable signal divided into an active section and a blank section,
Than the first blank period of the first data enable signal when only the first image frame data is output,
And a second blank section of the second data enable signal when the first image frame data and the second image frame data are output is smaller. The method of claim 1,
The output interface,
Outputs a data enable signal divided into an active section and a blank section,
And setting the length of the active section based on the resolution information of the panel and the driving frequency of the panel. The method of claim 1,
The output interface,
By summing a section for transmitting the second video frame data to a section for transmitting the first video frame data having a first length,
And setting an active section having a second length greater than the first length. The method of claim 1,
The output interface,
Outputs a data enable signal divided into an active section and a blank section,
When the resolution of the panel is the first resolution and the driving frequency of the panel is the first frequency, the active section of the first length and the blank section of the second length are set,
When outputting the first image frame data and the second image frame data, at least a part of the first image frame data is transmitted during the active period of the first length, and a partial period of the blank period of the second length During the signal processing apparatus, at least part of the second image frame data is transmitted. The method of claim 1,
The output interface,
The first output terminal for transmitting the vertical synchronization signal, the second output terminal for transmitting the horizontal synchronization signal, the third output terminal for transmitting the data signal of the first image frame data, and the data enable signal transmission of the first image frame data. And a fourth output terminal for transmitting a data signal of the second image frame data, a fifth output terminal for transmitting a data signal of the second image frame data, and a sixth output terminal for transmitting a data enable signal of the second image frame data. The method of claim 13,
The output interface,
And outputting the first image frame data and the second image frame data using different output terminals. The method of claim 1,
The output interface,
When the image output mode is a low delay mode, outputting the first image frame data for n image frames and the second image frame data for n image frames together, or not outputting the second image frame data Signal processing device characterized by. The method of claim 15,
And the low delay mode includes at least one of a game mode and a mirroring mode. The method of claim 1,
The second image processing unit,
A scaler for generating second image frame data scaled down from the first image frame data based on the image signal,
The scaler,
Generating at least one super pixel or super block based on some of the image blocks of the image signal, and outputting the scaled-down second image frame data including the super pixel or super block Signal processing device. The method of claim 17,
The scaler,
The signal processing apparatus, characterized in that the size of the super pixel or super block is varied according to the resolution or the image size of the image signal. An input interface for receiving an image signal from the outside;
A first image processing unit generating first image frame data based on the image signal;
A second image processing unit generating second image frame data based on the image signal;
And an output interface configured to output a data enable signal divided into an active period and a blank period, a data signal of the first image frame data, and a data signal of the second image frame data,
The output interface,
When only the data signal of the first image frame data is output, an active section of the first data enable signal is set as a first length,
When outputting the data signal of the first image frame data and the data signal of the second image frame data together, setting an active section of the second data enable signal to a second length greater than the first length Signal processing device characterized by. The method of claim 19,
The output interface,
When only the data signal of the first image frame data is output, a blank section of the first data enable signal is set to a third length,
When outputting the data signal of the first image frame data and the data signal of the second image frame data together, setting a blank section of the second data enable signal to a fourth length smaller than the third length Signal processing device characterized by. The method of claim 19,
The output interface,
The signal processing apparatus according to claim 1, wherein the length of the active section of the second data enable signal is varied based on the resolution information of the panel and the driving frequency of the panel. The signal processing device according to any one of claims 1 to 21;
A timing controller that performs signal processing based on the image signal output from the signal processing device;
And a panel that displays an image based on a signal from the timing controller. The method of claim 22,
The timing controller,
Extracting information on the first image frame data based on the second image frame data from the signal processing device,
And performing signal processing on the first image frame data based on the extracted information, and outputting a signal for the signal-processed first image frame data to the panel. The method of claim 22,
The timing controller,
Extracting information on the first image frame data based on the second image frame data from the signal processing device,
When the power information based on the luminance information in the extracted information exceeds the reference value, the luminance level of the first image frame data is changed from the first level to the second level so that the power level consumed by the panel is less than the allowable value And outputting, to the panel, a signal for the first image frame data whose luminance is changed to the second level and whose luminance is changed to the second level. The method of claim 22,
The timing controller,
An image display apparatus, characterized in that, based on the luminance information in the extracted information, the power level consumed by the panel is controlled to be less than or equal to an allowable value. The method of claim 22,
The timing controller,
When power information based on the luminance information for a partial region of the first image frame data exceeds a reference value based on the extracted information, the luminance level of the partial region of the first image frame data is reduced from the first level. And outputting, to the panel, a signal for a partial region of the first image frame data whose luminance is lowered to a second level and luminance is varied to the second level. The method of claim 22,
The timing controller,
When the image output mode of the signal processing apparatus is the first mode, the first image frame data and the second image frame data are received,
Based on the second image frame data, signal-processing the first image frame data to control the signal-processed first image frame data to be displayed on the panel,
When the image output mode of the signal processing apparatus is the second mode, the received first image frame data is signal-processed without information on the second image frame data, and the signal-processed first image frame data An image display device, characterized in that controlling to display on a panel.

Images