KR20200079735A - Display Device Having Mirror Function - Google Patents

Abstract

A display device having a mirror function according to an embodiment of the present invention includes: a display panel including a plurality of pixels of which each has an emission and a non-emission area, wherein a driving transistor that generates a driving current according to a data voltage is positioned in the non-emission area; a light control panel disposed on one surface of the display panel. The light control panel includes: an image transmitting unit positioned to correspond to the emission area of each pixel and driven according to the data voltage to emit internal light generated in the emission area to the outside; and a mirror unit positioned to correspond to the non-emission area of each pixel and driven according to a mirror power source to reflect or block external light.

Description

Display device having mirror function

The present invention relates to a mirror combined display device.

Various display devices have been developed and marketed. Among them, the organic light emitting display device is a self-emission device that emits light by itself, and has an advantage of high response speed, high luminous efficiency, brightness, and viewing angle. In particular, the organic light emitting display device can be formed on a flexible flexible substrate as well as can be driven at a lower voltage than a plasma display panel or an inorganic electroluminescent (EL) display and consumes less power. It has the advantage of excellent color.

A technique for realizing a mirror function on a display surface of an organic light emitting display device is known. However, the conventional mirror combined display device has a problem that the reflectivity is high and the contrast ratio of the image is low, thereby deteriorating the image quality.

Accordingly, the present invention provides a mirror combined display device capable of improving image quality while maintaining a mirror function.

A mirror combined display device according to an exemplary embodiment of the present invention includes a plurality of pixels, each pixel has a light emitting area and a non-light emitting area, and a driving transistor generating a driving current according to a data voltage is located in the non-light emitting area Display panel; And a light control panel disposed on one surface of the display panel. The light control panel is positioned to correspond to the light emitting area of each pixel, and is driven according to the data voltage to transmit an internal light generated in the light emitting area to the outside and a non-light emitting area of each pixel. It is located and has a mirror part that is driven according to the power of the mirror to reflect or block external light.

A mirror combined display device according to an embodiment of the present invention uses a light control panel including an image transmitting unit operating in a light transmitting/shielding mode according to a data voltage and a mirror unit operating in a light transmitting/shielding mode according to a mirror power source, thereby providing a mirror function. While maintaining, it is possible to dramatically improve the display quality by increasing the contrast ratio of the display image.

The display device for a mirror according to an embodiment of the present invention can realize a high-quality image by operating the mirror unit in a light-shielding mode when the contrast ratio needs to be increased, and is easy to expand to various applications.

In the mirror combined display device according to an exemplary embodiment of the present invention, by connecting the gate electrode of the driving transistor of each pixel to one electrode of the image transmission unit, the image transmission unit can be easily controlled in units of pixels according to the data voltage for image display.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a schematic block diagram of a display device for a mirror according to an embodiment of the present invention.
2 is an equivalent circuit diagram of one pixel of a mirror combined display device according to an embodiment of the present invention and an optical control panel connected thereto.
3 is a diagram illustrating an electrode configuration of an optical control panel according to an embodiment of the present invention.
4 is a plan view showing a pixel and a first electrode of a light control panel connected thereto according to an embodiment of the present invention.
5 is a cross-sectional view taken along the cutting line AB in FIG. 4.
6A to 6C are diagrams for describing an operation of a pixel and a light control panel connected thereto according to an embodiment of the present invention.
7 is a plan view showing a pixel and a first electrode of a light control panel connected thereto according to another embodiment of the present invention.
8 is a cross-sectional view along the cutting line AB in FIG. 7.
9A to 9C are diagrams for describing an operation of a pixel and a light control panel connected thereto according to another embodiment of the present invention.

Advantages and features of the present specification, and a method of achieving them will be apparent with reference to embodiments described below in detail together with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present specification to be complete, and common knowledge in the art to which this specification belongs It is provided to fully inform the person having the scope of the invention, and this specification is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present specification are exemplary, and the present specification is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. When'include','have','consist of', etc. mentioned in this specification are used, other parts may be added unless'~ only' is used. When a component is expressed as a singular number, the plural number is included unless otherwise specified.

In interpreting the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, when the positional relationship of the two parts is described as'~ on','~ on top','~ on the bottom','~ next to', etc.,'right' Alternatively, one or more other parts may be located between the two parts unless'direct' is used.

The first, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below may be the second component within the technical spirit of the present specification.

Hereinafter, embodiments of the present specification will be described in detail with reference to the accompanying drawings. In the following description, when it is determined that a detailed description of known functions or configurations related to the present specification may unnecessarily obscure the subject matter of the present specification, the detailed description is omitted.

In the mirror combined display device according to the present invention, a light emitting element is formed on a glass substrate or a flexible substrate. The light emitting device may be implemented as an organic light emitting diode, but is not limited thereto, and various modifications are possible. In an embodiment of the present invention, a light emitting device is illustrated as an organic light emitting diode for convenience. The organic light emitting diode includes an organic compound layer made of an organic material between the anode electrode and the cathode electrode. In the organic light emitting diode, holes supplied from the anode electrode and electrons supplied from the cathode electrode are combined in an organic compound layer to form excitons, which are hole-electron pairs, and emit light by energy generated when the excitons return to the ground state. .

1 is a schematic block diagram of a display device for a mirror according to an embodiment of the present invention. 2 is an equivalent circuit diagram of one pixel of a mirror combined display device according to an embodiment of the present invention and an optical control panel connected thereto. And, Figure 3 is an electrode configuration of the light control panel according to an embodiment of the present invention.

Referring to FIG. 1, the mirror combined display device 100 according to an exemplary embodiment of the present invention includes an image processing unit 110, a timing control unit 120, a data driving unit 130, a scan driving unit 140, and a display panel 150. , And a light control panel 200.

The image processing unit 110 outputs a data enable signal DE as a timing signal as well as a data signal DATA as an image source. In addition to the data enable signal DE, the image processing unit 110 may further output at least one timing signal among a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

The timing controller 120 receives a data signal DATA in addition to a timing signal from the image processor 110. The timing controller 120 may include a gate timing control signal GDC for controlling the operation timing of the scan driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 130 based on the timing signal. Output

The data driver 130 converts the data signal DATA supplied from the timing controller 120 to an analog data voltage in response to the data timing control signal DDC supplied from the timing controller 120. The data driver 130 outputs the data voltage through the data lines DL of the display panel 150. After the data driver 130 is formed in the form of an integrated circuit (IC), it may be bonded to the data lines DL through a conductive film.

The scan driver 140 generates a scan signal in response to the gate timing control signal GDC supplied from the timing controller 120 and then outputs a scan signal through the gate lines GL of the display panel 150. . After the scan driver 140 is formed in the form of an IC, the scan driver 140 may be bonded to the gate lines GL through a conductive film. Also, the scan driver 140 may be directly formed in a non-display area (bezel area) of the display panel 150 in a gate-in-panel method.

The display panel 150 displays an image corresponding to the data signal DATA and the scan signal supplied from the data driver 130 and the scan driver 140. A plurality of data lines DL and a plurality of gate lines GL are crossed on the display panel 150, and pixels SP are arranged in a matrix form for each intersection area. The pixels SP may include R pixels including an R color filter, G pixels including a G color filter, and B pixels including a B color filter. The pixels SP may further include W pixels without a color filter. The R pixel, the G pixel, the B pixel, and the W pixel may constitute one unit pixel. At least one light emitting region of the R pixel, the G pixel, the B pixel, and the W pixel may be different according to light emission characteristics.

Each of the pixels SP receives the high potential pixel voltage EVDD and the low potential pixel voltage EVSS from the power generator, and emits light with a brightness proportional to the data voltage. To this end, each pixel SP includes a driving element that generates a driving current corresponding to the data voltage Vdata, and a light emitting element that emits light with a brightness proportional to the driving current. The pixel SP of the present invention has a light emitting area and a non-light emitting area. The light-emitting region is a region in which the anode electrode, the cathode electrode, and the organic compound layer constituting the light-emitting element are contacted, and is the region in which internal light is emitted through a color filter. Areas other than the light emitting area are non-light emitting areas. A circuit unit including a driving element, a switching element, and a storage element is positioned in the non-emission area.

Meanwhile, the pixel SP of the present invention may have a circuit structure suitable for sensing deterioration of a driving element and/or a light emitting element according to environmental conditions such as driving time lapse and/or panel temperature. The configuration of the pixel (SP) circuit can be variously modified. For example, the pixel SP may include a plurality of switching elements and at least one storage element in addition to the light emitting element and the driving element.

The light control panel 200 may be disposed on one surface of the display panel 150, specifically, on a screen of the display panel 150. The light control panel 200 includes an image transmission unit 210 positioned to correspond to the light emitting area of each pixel SP and a mirror unit 220 positioned to correspond to the non-light emitting area of each pixel SP. The image transmitting unit 210 is driven according to the data voltage to emit internal light generated in the light emitting region to the outside. Since the operation of the image transmitting unit 210 is interlocked with the data voltage, a separate driving power source is not required. The mirror unit 220 is driven according to a mirror power source to reflect or block external light. When the contrast ratio of the image needs to be increased, the mirror power is deactivated to block external light, so the image quality can be improved.

The configuration of each pixel SP and the configuration of the light control panel 200 connected thereto will be described with reference to FIG. 2 as follows.

Each pixel SP may include a switching transistor ST, a driving transistor DT, a storage capacitor Cst, and an organic light emitting diode OLED, but is not limited thereto.

The switching transistor ST is turned on according to the scan signal SCAN supplied through the gate line GL, and is a switching element that applies the data voltage Vdata on the data line DL to the gate electrode of the driving transistor DT. to be. The gate electrode of the switching transistor ST is connected to the gate line GL, the drain electrode of the switching transistor ST is connected to the data line DL, and the source electrode of the switching transistor ST is the driving transistor DT. It is connected to the gate electrode.

The driving transistor DT is a driving element that generates a driving current proportional to the data voltage Vdata. The gate electrode of the driving transistor DT is connected to the source electrode of the switching transistor ST, and the drain electrode of the driving transistor DT is connected to the power line PL to which the high potential pixel voltage EVDD is applied, and is driven. The source electrode of the transistor DT is connected to the anode electrode of the organic light emitting diode (OLED).

The organic light emitting diode (OLED) is a light emitting device that emits light at a brightness corresponding to a driving current. The anode electrode of the organic light emitting diode (OLED) is connected to the source electrode of the driving transistor DT, and the cathode electrode of the organic light emitting diode (OLED) is connected to the input terminal of the low potential pixel voltage (EVSS).

The storage capacitor Cst is a storage element connected to the gate electrode and the source electrode of the driving transistor DT to store the data voltage Vdata for a predetermined time. The storage capacitor Cst includes a storage upper electrode and a storage lower electrode, and at least one insulating film sandwiched between them.

One of the first capacitors PCAP included in the light control panel 200 is connected to each pixel SP. The first capacitor PCAP is in contact with the gate electrode of the driving transistor DT, the first electrode EC1 receiving the data voltage Vdata, and the second electrode EC2 receiving the common voltage COM, And a first electrical behavior material EBM1 sandwiched between the first and second electrodes EC1 and EC2. The first and second electrodes EC1 and EC2 overlap the emission area of each pixel SP. The first and second electrodes EC1 and EC2 may be patterned in units of each pixel SP as shown in FIG. 3. The first electrodes EC1 constituting the first capacitors PCAP are individually supplied with the data voltage Vdata, while the second electrodes EC2 are commonly supplied with the common voltage COM. The common voltage COM may be a ground voltage (ground voltage), but is not limited thereto.

The second capacitors RCAP are further included in the light control panel 200. The second capacitor RCAP includes a first mirror electrode EP1 connected to a high voltage terminal (+) of the mirror power supply Vdrv, and a second mirror electrode EP2 connected to a low voltage terminal (-) of the mirror power supply Vdrv. And a second electrical behavior material EBM2 sandwiched between the first and second mirror electrodes EP1 and EP2. The first and second mirror electrodes EP1 and EP2 overlap the non-emission area of each pixel SP. The first and second mirror electrodes EP1 and EP2 may be patterned in units of pixels as shown in FIG. 3 to have a stripe shape.

4 is a plan view showing a pixel and a first electrode of a light control panel connected thereto according to an embodiment of the present invention. And, Fig. 5 is a cross-sectional view taken along line A-B of Fig. 4.

4 and 5, the pixel SP according to an embodiment of the present invention includes transistors implemented in a coplanar structure. In the pixel SP of the coplanar structure, each of the driving transistor DT and the switching transistor ST has a gate electrode located on the active layer.

The coplanar structure pixel SP includes a light emitting area and a non-light emitting area.

In the emission region, the anode electrode (AND), the cathode electrode (CAT), and the organic compound layer (EL) constituting the organic light emitting diode (OLED) are contacted. The data line DL, the gate line GL, the power line PL, the driving transistor DT, the storage capacitor Cst, and the switching transistor ST are disposed in the non-emission area.

When the configuration of the pixel SP is described in detail, the first semiconductor layer ACT1 of the switching transistor ST and the second semiconductor layer ACT2 of the driving transistor DT are positioned on the second substrate GLS2. The first and second semiconductor layers ACT1 and ACT2 may be made of a silicon semiconductor or an oxide semiconductor. The silicon semiconductor may include amorphous silicon or crystallized polycrystalline silicon. Here, polycrystalline silicon has a high mobility (100 cm 2 /Vs or more), has low energy consumption, and has excellent reliability, and thus may be applied to the driving transistor DT, but is not limited thereto. Meanwhile, since the oxide semiconductor has a low off-current, it may be applied to a switching transistor ST having a short on time and a long off time, but is not limited thereto. The first and second semiconductor layers ACT1 and ACT2 include a drain region and a source region including p-type or n-type impurities, and a channel formed therebetween.

The gate insulating layer GI is positioned on the first and second semiconductor layers ACT1 and ACT2. The gate insulating layer GI may be silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof. The gate insulating layer GI may be formed on the entire substrate, but may also be formed by patterning only a portion of the semiconductor layers ACT1 and ACT2.

The gate electrode SG of the switching transistor ST and the gate electrode DG of the driving transistor DT are positioned on the gate insulating layer GI to correspond to the channels of the semiconductor layers ACT1 and ACT2. The gate electrodes SG and DG are connected to the gate line GL. The lower electrode of the storage capacitor Cst is positioned on the same layer as the gate line GL. The gate metal pattern including the gate line GL and the lower electrodes of the gate electrodes SG and DG and the storage capacitor Cst are molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), and titanium. (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). In addition, the lower electrodes of the gate lines GL, the gate electrodes SG, DG, and the storage capacitor Cst are molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), and titanium (Ti). , Nickel (Ni), neodymium (Nd), and copper (Cu).

An interlayer insulating layer (ILD) is positioned on the gate metal pattern. The interlayer insulating film ILD may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or multiple layers thereof.

Data line DL, power line PL, drain electrode SD and source electrode SS of switching transistor ST, drain electrode DD and source of driving transistor DT on interlayer insulating film ILD A data metal pattern including an electrode DS and an upper electrode of the storage capacitor Cst is positioned. The data metal pattern may be formed of a single layer or multiple layers. In the case of a single layer, the data metal pattern is from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). It can be made of any one selected or alloys thereof. In addition, in the case of a multi-layer, the data metal pattern may consist of a double layer of molybdenum/aluminum-neodymium, a triple layer of titanium/aluminum/titanium, molybdenum/aluminum/molybdenum or molybdenum/aluminum-neodymium/molybdenum.

The drain electrode SD and the source electrode SS of the switching transistor ST respectively pass through the first contact hole CH1 and the second contact hole CH2 penetrating the interlayer insulating layer ILD, respectively. ). The drain electrode DD and the source electrode DS of the driving transistor DT are respectively formed through the second semiconductor layer ACT2 through the fourth contact hole CH4 and the fifth contact hole CH5 passing through the interlayer insulating layer ILD. ). The source electrode SS of the switching transistor ST and the gate electrode DG of the driving transistor DT are connected through a third contact hole CH3 passing through the interlayer insulating layer ILD.

A passivation film (PAS) is positioned on the data metal pattern. The passivation film PAS is an insulating film protecting the lower transistors ST and DT, and may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or multiple layers thereof.

The color filter CF is positioned on the passivation film PAS. The color filter CF converts the color of white light generated in the light emitting layer and is located in the light emitting area. The color filter CF may be any one of an R color filter, a G color filter, and a B color filter.

The planarization film OC is positioned on the color filter CF. The planarization film (OC) is for alleviating the step difference of the lower structure, and is made of organic materials such as polyimide, benzocyclobutene series resin, and acrylate. The planarization film (OC) may be formed by a method such as spin on glass (SOG) for coating the organic material in a liquid form and then curing. A sixth contact hole CH6 exposing the source electrode DS of the driving transistor DT through the passivation film PAS is positioned in a portion of the planarization film OC.

The anode electrode AND serving as a pixel electrode is positioned on the planarization film OC. The anode electrode AND is connected to the source electrode DS of the driving transistor DT through the sixth contact hole CH6. The anode electrode (AND) may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

On the anode electrode AND, a bank pattern BNK partitioning a light emitting region of each pixel is positioned. The bank pattern (BNK) is made of organic materials such as polyimide, benzocyclobutene series resin, and acrylate. The bank pattern BNK exposes the anode electrode AND in the emission region.

The organic compound layer EL is positioned on the bank pattern BNK. The organic compound layer EL includes a light emitting layer in which electrons and holes are combined to emit light, and may further include at least one of a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer. The organic compound layer EL is in contact with the anode electrode AND exposed by the bank pattern BNK in the emission region.

The cathode electrode CAT is positioned on the organic compound layer EL. The cathode electrode CAT may be formed of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof having a low work function.

An encapsulation layer SUS is positioned on the cathode electrode CAT. The encapsulation layer ENC is provided to cover the pixel array to block moisture or oxygen that may be introduced into the pixel. The encapsulation layer ENC may include a metal material. In this case, the encapsulation layer ENC may be made of iron (Fe), a nickel (Ni) alloy, invar, or steel use stainless (SUS), but is not limited thereto. In addition, the encapsulation layer ENC may include an organic material and an inorganic material. In this case, the encapsulation layer ENC may be a multi-layer in which organic materials and inorganic materials are alternately stacked, but is not limited thereto.

A flattening adhesive (AHS) may be positioned between the cathode electrode CAT and the encapsulation layer ENC.

4 and 5, the light control panel 200 is positioned in front of the pixel SP of the above-described coplanar structure (internal light emission direction).

The light control panel 200 includes an image transmission unit 210 positioned to correspond to the emission area of the pixel SP and a mirror unit 220 positioned to correspond to the non-emission area of the pixel SP.

When the configuration of the light control panel 200 is described in detail, the second electrode EC2 of the image transmission unit 210 and the second mirror electrode EP2 of the mirror unit 220 are positioned on the first substrate GLS1. . The second electrode EC2 and the second mirror electrode EP2 may include transparent metal oxide. For example, the second electrode EC2 and the second mirror electrode EP2 may be implemented with indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

The first electrical behavior material EBM1 of the image transmission part 210 and the second electrical behavior material EBM2 of the mirror part 220 may be positioned on the second electrode EC2 and the second mirror electrode EP2. . The first electrical behavior material EBM1 and the second electrical behavior material EBM2 may be configured identically. The first electrophoretic material (EBM1) and the second electrophoretic material (EBM2) are polymer-dispersed liquid crystals, electro-phoretic materials, electrochromic materials, and floating particles. It may be made of any one of a device (Suspended Particle Device). The polymer dispersed thin film liquid crystal implements a light transmission mode and a light blocking mode due to a difference in refractive index according to voltage. The electrophoretic material implements a light-transmission mode and a light-shielding mode including black particles and white particles moved by an electric field. The electrochromic material reversibly causes a color change when an electrochemical oxidation or reduction reaction occurs in the electrode material, thereby realizing a light transmission mode and a light blocking mode. The floating particle device implements a light transmission mode and a light blocking mode by adjusting the arrangement or direction of the floating particles according to the voltage.

The first electrode EC1 of the image transmission unit 210 and the first mirror electrode EP1 of the mirror unit 220 are positioned on the first electrical behavior material EBM1 and the second electrical behavior material EBM2. The first electrode EC1 may include a transparent metal oxide. The first mirror electrode EP1 may include a metal material having high reflectance. For example, the first mirror electrode EP1 may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof having high reflectance.

The second substrate GLS2 is positioned between the first electrode EC1 of the image transmission unit 210 and the driving transistor DT of the pixel SP. The gate electrode DG of the driving transistor DT contacts the first electrode EC1 of the image transmission unit 210 through the substrate through hole GCH formed in the second substrate GLS2. Therefore, the first electrode EC1 of the image transmission unit 210 may be driven according to the data voltage Vdata applied to the gate electrode DG of the driving transistor DT.

Referring to FIGS. 6A to 6C, the operation of the pixel and the optical control panel connected thereto according to an embodiment of the present invention will be described as follows. 6A to 6C, the connection part refers to an area in which the first electrode EC1 of the image transmission part 210 contacts the gate electrode DG of the driving transistor DT through the substrate through hole GCH.

6A shows a case in which only the mirror state is operated without displaying the image. Referring to FIG. 6A, when the data voltage Vdata is smaller than a preset reference value (that is, when the display image is close to black), the image transmission unit 220 blocks internal light in the emission region from being emitted to the outside. The first electrical behavior material EBM1 is driven in the light blocking mode by the data voltage Vdata applied to the first electrode EC1 and the common voltage COM applied to the second electrode EC2.

At this time, the mirror unit 220 reflects external light according to the activated mirror power Vdrv to implement a mirror function. The second electrical behavior material EBM2 is driven in a transmissive mode by an active mirror power source Vdrv applied to the first and second mirror electrodes EP1 and EP2, and the first mirror electrode EP1 acts as a reflective electrode Do it.

6B shows an operation for increasing the contrast ratio of the display image by turning off the mirror function. Referring to FIG. 6B, when the data voltage Vdata is equal to or greater than a preset reference value (that is, when the display image is close to white), the image transmission unit 220 emits internal light in the emission area to the outside. The first electrical behavior material EBM1 is driven in the light transmission mode by the data voltage Vdata applied to the first electrode EC1 and the common voltage COM applied to the second electrode EC2.

In this case, the mirror unit 220 may increase the contrast ratio of the display image (ie, an image represented by internal light emitted from the image transmission unit 220) by blocking external light according to the deactivated mirror power Vdrv. . The second electrical behavior material EBM2 is driven in the light blocking mode by the inactive mirror power Vdrv applied to the first and second mirror electrodes EP1 and EP2. The external light incident on the mirror unit 220 is not reflected outside by the second electrical behavior material EBM2.

6C shows an operation of simultaneously implementing an image display and a mirror function. Referring to FIG. 6C, when the data voltage Vdata is equal to or greater than a preset reference value (that is, when the display image is close to white), the image transmission unit 220 emits internal light in the emission area to the outside. The first electrical behavior material EBM1 is driven in the light transmission mode by the data voltage Vdata applied to the first electrode EC1 and the common voltage COM applied to the second electrode EC2.

In this case, the mirror unit 220 may reflect external light according to the activated mirror power Vdrv to implement a mirror function. The second electrical behavior material EBM2 is driven in a transmissive mode by an active mirror power source Vdrv applied to the first and second mirror electrodes EP1 and EP2, and the first mirror electrode EP1 acts as a reflective electrode Do it.

7 is a plan view showing a pixel and a first electrode of a light control panel connected thereto according to another embodiment of the present invention. And, Fig. 8 is a cross-sectional view taken along line A-B of Fig. 7.

7 and 8, a pixel SP according to another embodiment of the present invention includes transistors implemented in an etch stopper structure. In the pixel SP of the etch stopper structure, each of the driving transistor DT and the switching transistor ST has a gate electrode located under the active layer.

The pixel SP of the etch stopper structure includes a light emitting area and a non-light emitting area.

In the emission region, the anode electrode (AND), the cathode electrode (CAT), and the organic compound layer (EL) constituting the organic light emitting diode (OLED) are contacted. The data line DL, the gate line GL, the power line PL, the driving transistor DT, the storage capacitor Cst, and the switching transistor ST are disposed in the non-emission area.

When the configuration of the pixel SP is described in detail, the gate electrode SG of the switching transistor ST and the gate electrode DG of the driving transistor DT and the gate line GL and storage on the second substrate GLS2. The gate metal pattern including the lower electrode of the capacitor Cst is positioned.

The gate insulating layer GI is positioned on the gate metal pattern.

The first semiconductor layer ACT1 of the switching transistor ST and the second semiconductor layer ACT2 of the driving transistor DT are positioned on the gate insulating layer GI.

The etch stopper pattern ESL is positioned on the first and second semiconductor layers ACT1 and ACT2. The etch stopper pattern ESL overlaps the gate electrode DG of the driving transistor DT and may be positioned with a larger area.

On the etch stopper pattern ESL, the data line DL, the power line PL, the drain electrode SD and the source electrode SS of the switching transistor ST, and the drain electrode DD of the driving transistor DT, A data metal pattern including a source electrode DS and an upper electrode of the storage capacitor Cst is positioned.

The drain electrode SD and the source electrode SS of the switching transistor ST are directly connected to the first semiconductor layer ACT1. The drain electrode DD and the source electrode DS of the driving transistor DT are directly connected to the second semiconductor layer ACT2. The source electrode SS of the switching transistor ST and the gate electrode DG of the driving transistor DT are connected through a third contact hole CH3 passing through the gate insulating layer GI.

The first passivation film PAS1 is positioned on the data metal pattern. The first passivation film PAS1 protects the lower transistors ST and DT.

The color filter CF is positioned on the first passivation film PAS1. The color filter CF converts the color of white light generated in the light emitting layer and is located in the light emitting area. The color filter CF may be any one of an R color filter, a G color filter, and a B color filter.

The planarization film OC is positioned on the color filter CF. The planarization film (OC) alleviates the step difference of the underlying structure. Then, the second passivation film PAS2 is positioned on the planarization film OC. A sixth contact hole CH6 exposing the source electrode DS of the driving transistor DT is positioned through the second passivation film PAS2, the planarization film OC, and the first passivation film PAS1.

An anode electrode AND serving as a pixel electrode is positioned on the second passivation film PAS2. The anode electrode AND is connected to the source electrode DS of the driving transistor DT through the sixth contact hole CH6.

On the anode electrode AND, a bank pattern BNK partitioning a light emitting region of each pixel is positioned. The bank pattern BNK exposes the anode electrode AND in the emission region.

The organic compound layer EL is positioned on the bank pattern BNK. The organic compound layer EL includes a light emitting layer in which electrons and holes are combined to emit light, and may further include at least one of a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer. The organic compound layer EL is in contact with the anode electrode AND exposed by the bank pattern BNK in the emission region.

The cathode electrode CAT is positioned on the organic compound layer EL. The cathode electrode CAT may be a reflective electrode capable of reflecting light.

The encapsulation layer SUS is positioned on the cathode electrode CAT. The encapsulation layer ENC is provided to cover the pixel array to block moisture or oxygen that may be introduced into the pixel.

A capping layer CPL and an adhesive for planarization (AHS) may be further disposed between the cathode electrode CAT and the encapsulation layer ENC. The capping layer CPL is positioned on the cathode electrode CAT to protect the cathode electrode CAT and improve external light efficiency. The capping layer CPL may be formed of an organic layer or an inorganic layer.

Referring to FIGS. 7 and 8, the light control panel 200 is positioned in front of the pixel SP of the above-described etch stopper structure (internal light emission direction).

The light control panel 200 includes an image transmission unit 220 positioned to correspond to the light emitting area of the pixel SP and a mirror unit 220 positioned to correspond to the non-light emitting area of the pixel SP.

When the configuration of the light control panel 200 is described in detail, the second electrode EC2 of the image transmission unit 210 and the second mirror electrode EP2 of the mirror unit 220 are positioned on the first substrate GLS1. . The second electrode EC2 and the second mirror electrode EP2 may include transparent metal oxide. For example, the second electrode EC2 and the second mirror electrode EP2 may be implemented with indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

The first electrical behavior material EBM1 of the image transmission part 210 and the second electrical behavior material EBM2 of the mirror part 220 may be positioned on the second electrode EC2 and the second mirror electrode EP2. . The first electrical behavior material EBM1 and the second electrical behavior material EBM2 may be configured identically. The first electrophoretic material (EBM1) and the second electrophoretic material (EBM2) are polymer-dispersed liquid crystals, electro-phoretic materials, electrochromic materials, and floating particles. It may be made of any one of a device (Suspended Particle Device). The polymer dispersed thin film liquid crystal implements a light transmission mode and a light blocking mode due to a difference in refractive index according to voltage. The electrophoretic material implements a light-transmission mode and a light-shielding mode including black particles and white particles moved by an electric field. The electrochromic material reversibly causes a color change when an oxidation or reduction reaction occurs electrochemically in the electrode material, thereby realizing a light transmission mode and a light blocking mode. The floating particle device implements a light transmission mode and a light blocking mode by adjusting the arrangement or direction of the floating particles according to the voltage.

The first electrode EC1 of the image transmission unit 210 and the first mirror electrode EP1 of the mirror unit 220 are positioned on the first electrical behavior material EBM1 and the second electrical behavior material EBM2. The first electrode EC1 may include a transparent metal oxide. The first mirror electrode EP1 may include a metal material having high reflectance. For example, the first mirror electrode EP1 may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof having high reflectance.

The second substrate GLS2 is positioned between the first electrode EC1 of the image transmission unit 210 and the driving transistor DT of the pixel SP. The gate electrode DG of the driving transistor DT contacts the first electrode EC1 of the image transmission unit 210 through the substrate through hole GCH formed in the second substrate GLS2. Therefore, the first electrode EC1 of the image transmission unit 210 may be driven according to the data voltage Vdata applied to the gate electrode DG of the driving transistor DT.

Referring to FIGS. 9A to 9C, an operation of a pixel and a light control panel connected thereto according to another embodiment of the present invention will be described as follows.

9A shows a case where only the mirror state is operated without displaying the image. Referring to FIG. 9A, when the data voltage Vdata is smaller than a preset reference value (that is, when the display image is close to black), the image transmission unit 220 blocks internal light in the emission region from being emitted to the outside. The first electrical behavior material EBM1 is driven in the light blocking mode by the data voltage Vdata applied to the first electrode EC1 and the common voltage COM applied to the second electrode EC2.

At this time, the mirror unit 220 reflects external light according to the activated mirror power Vdrv to implement a mirror function. The second electrical behavior material EBM2 is driven in a transmissive mode by an active mirror power source Vdrv applied to the first and second mirror electrodes EP1 and EP2, and the first mirror electrode EP1 acts as a reflective electrode Do it.

9B shows an operation for increasing the contrast ratio of the display image by turning off the mirror function. Referring to FIG. 9B, when the data voltage Vdata is equal to or greater than a preset reference value (that is, when the display image is close to white), the image transmission unit 220 emits internal light in the emission area to the outside. The first electrical behavior material EBM1 is driven in the light transmission mode by the data voltage Vdata applied to the first electrode EC1 and the common voltage COM applied to the second electrode EC2.

In this case, the mirror unit 220 may increase the contrast ratio of the display image (ie, an image represented by internal light emitted from the image transmission unit 220) by blocking external light according to the deactivated mirror power Vdrv. . The second electrical behavior material EBM2 is driven in the light blocking mode by the inactive mirror power Vdrv applied to the first and second mirror electrodes EP1 and EP2. The external light incident on the mirror unit 220 is not reflected outside by the second electrical behavior material EBM2.

9C shows an operation of simultaneously implementing an image display and a mirror function. Referring to FIG. 9C, when the data voltage Vdata is equal to or greater than a preset reference value (that is, when the display image is close to white), the image transmission unit 220 emits internal light in the emission area to the outside. The first electrical behavior material EBM1 is driven in the light transmission mode by the data voltage Vdata applied to the first electrode EC1 and the common voltage COM applied to the second electrode EC2.

In this case, the mirror unit 220 may reflect external light according to the activated mirror power Vdrv to implement a mirror function. The second electrical behavior material EBM2 is driven in a transmissive mode by an active mirror power source Vdrv applied to the first and second mirror electrodes EP1 and EP2, and the first mirror electrode EP1 acts as a reflective electrode Do it.

Through the above description, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical idea of the present specification. Therefore, the technical scope of the present specification is not limited to the contents described in the detailed description of the specification, but should be determined by the scope of the claims.

150: display panel 200: optical control panel

Claims (14)

A display panel in which a plurality of pixels are provided, each pixel has a light emitting area and a non-light emitting area, and a driving transistor generating a driving current according to a data voltage is located in the non-light emitting area; And
It includes a light control panel disposed on one surface of the display panel,
The light control panel,
An image transmissive unit positioned to correspond to the emission region of each pixel and driven according to the data voltage to emit internal light generated in the emission region to the outside;
A display device for a mirror positioned to correspond to the non-emission area of each pixel and driven by a mirror power source to have a mirror unit that reflects or blocks external light. According to claim 1,
The image transmission unit,
A first electrode overlapping the emission region and partially protruding into the non-emission region to contact a gate electrode of the driving transistor to which the data voltage is applied;
A second electrode overlapping the emission region and to which a common voltage is applied; And
A mirror combined display device comprising a first electrical behavior material positioned between the first electrode and the second electrode. According to claim 2,
A substrate is positioned between the first electrode and the driving transistor,
The gate electrode of the driving transistor is a display device for a mirror that penetrates the substrate and contacts the first electrode. According to claim 2,
The first electrode and the second electrode are mirrored display devices patterned in units of pixels. According to claim 2,
The first electrode and the second electrode are mirrored display devices including a transparent metal oxide. According to claim 2,
The first electrical behavior material
When the data voltage is greater than or equal to a preset reference value, the display device is a mirror display that is driven in a light emitting mode and emits internal light in the light emitting area to the outside. According to claim 2,
The first electrical behavior material
When the data voltage is smaller than a preset reference value, the display device is a mirror and is driven in a light blocking mode to block the emission of the internal light in the light emitting area to the outside. According to claim 1,
The mirror portion,
A first mirror electrode overlapping the non-emission region and connected to a high voltage terminal of the mirror power source;
A second mirror electrode overlapping the non-emission region and connected to a low voltage terminal of the mirror power source; And
A display device for a mirror including a second electrical behavior material positioned between the first mirror electrode and the second mirror electrode. The method of claim 8,
The first mirror electrode and the second mirror electrode are a mirror combined display device patterned in units of a plurality of pixels. The method of claim 8,
The first mirror electrode includes a metal material having high reflectance,
The second mirror electrode is a mirror combined display device including a transparent metal oxide. The method of claim 8,
The second electrical behavior material
When the mirror power is activated, it is driven in a transmissive mode to pass the external light,
A mirror combined display device driven in a blocking mode when the mirror power is deactivated to block the external light. The method of claim 2 or 8,
The first electrical behavior material and the second electrical behavior material,
A mirror combined display device made of any one of Polymer Dispersed Liquid Crystal, Electro-Phoretic Material, Electrochromic Material, and Suspended Particle Device. According to claim 1,
Each pixel,
And a switching transistor for applying the data voltage to the driving transistor and the gate electrode of the driving transistor,
Each of the driving transistor and the switching transistor is a mirror combined display device implemented with a coplanar structure in which a gate electrode is positioned on an active layer. According to claim 1,
Each pixel,
And a switching transistor for applying the data voltage to the driving transistor and the gate electrode of the driving transistor,
Each of the driving transistor and the switching transistor is a mirror combined display device implemented with an etch stopper structure in which a gate electrode is positioned under the active layer.

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