KR20190096728A - Apparatus and Method for Synchronization and Alignment Using Scrambler and Descrambler - Google Patents

Abstract

Disclosed are a method and apparatus for synchronization and data alignment using a scrambler and a descrambler. According to an embodiment of the present invention, a transmitter receives a SYNC2 signal which is activated by corresponding to a width of data, receives SYNC1 signal which is activated before the SYNC2 signal is activated and activated before the SYNC2 signal is inactivated, and scrambles a predetermined pattern based on the SYNC1 signal and the SYNC2 signal, thereby generating and transmitting an output signal including synchronization information.

Description

Apparatus and Method for Synchronization and Alignment Using Scrambler and Descrambler}

The following embodiments are directed to a method and apparatus for data bit synchronization and data alignment in multiple channels using scrambler and descrambler.

Increasingly, data transmission for each channel of an optical transceiver constituting an optical or electrical network is increasing. For example, in 100G Ethernet or 400G Ethernet, approximately 25 Gbps and 50 Gbps of data must be transmitted over multiple channels per channel. In addition, processing capacity must increase gradually to handle hundreds of gigabytes per second (Gbps) of data per single device, such as an FPGA. In order to transfer high-speed and large-capacity data in such a system, it is basically called a serial-to-parallel converter (or parallel-to-serial converter) that recovers clocks and data from high-speed data, and converts and converts parallel data into high-speed serial data. SerDes (Serializer / Deserializer) should be provided. First, SerDes performs the function of converting parallel data and serial data. The transmitter converts parallel data to serial, and the receiver converts serial data to parallel data. In this case, if the transmitter and the receiver are identically reset and data transmission and reception do not proceed, bit synchronization must be provided since the clock phases are different from each other. In addition, in a multi-channel system using multiple SerDes, there is a difference in the delay time for transmitting data for each channel (or lane) due to various factors. In order to solve the skew of the delay time for each channel, Word alignment of multiple channels is also an essential feature.

In order to provide such a function, the conventional technology transmits a fixed pattern of data for bit synchronization between a transceiver and the receiver to convert the serial data of the receiver so that a known pattern is converted from serial data to parallel data and synchronized. Perform bit synchronization by shifting bit by bit at the input FIFO. In the case of word-by-word alignment, a specific bit string is formed in every lane to know the starting point of the data string, and data is simultaneously read from the elastic FIFO stored for each channel when a specific bit string is received from all data received for each channel. By performing the word-by-word alignment for multiple channels.

Another conventional technique is the 64B / 66B encoding and decoding technique. This adds two bits of overhead bits to 64-bit data to provide control bits that are separate from the data. The control bit corresponds to a header bit for synchronization, and the reception block uses a method of searching for a sync header bit from received data and performing bit synchronization and word alignment on a 64-bit basis. However, this has a problem in that an overhead occurs for data as a control signal for data transmission and the speed must be increased to maintain the same data transmission amount. In addition, if a continuous value of '0' or '1' of data to be transmitted is maintained continuously, the DC balance is not corrected, which causes a problem that the clock phase for clock and data recovery is shifted, and thus scrambled data is generally transmitted. . In the 64B / 66B scheme, the scrambler and the descrambler are used to scramble data, and the DC balance problem is solved by adding and transmitting the two-bit synchronization bit described above. However, in the case of the scrambler of the prior art, when an error bit occurs in the input data, an error of the data input to the de-scrambler is propagated to the polynomial forming the descrambler, thereby generating a plurality of errors.

Embodiments to be described below provide a technique for performing bit synchronization of multiple channels using a modified scrambler and a modified descrambler on multiple channels.

Embodiments also provide a technique for performing word alignment using a modified scrambler and a modified descrambler on multiple channels.

In one embodiment, a method of operating a transmitter includes: receiving a predetermined pattern; Receiving a SYNC2 signal, which is a control signal that is activated for bit strings corresponding to the width of data and is inactive for the remaining bit strings; Receiving a SYNC1 signal, which is a control signal that is activated for a predetermined number of bit strings before the SYNC2 signal is activated, is activated for a predetermined number of bit strings before the SYNC2 signal is inactivated, and is inactivated for the remaining bit strings. ; Scrambled the pattern based on the SYNC1 signal and the SYNC2 signal to generate an output signal comprising synchronization information; And transmitting the output signal.

In addition, the synchronization information may include first information on the timing of synchronization and second information on the width of the data.

The generating of the output signal may include selecting, based on the SYNC2 signal, an output of the polynomial module for scramble, or a temporary output signal obtained by calculating the pattern and the output signal as an input of the polynomial module. can do.

The generating of the output signal may include: generating a temporary output signal based on the output of the polynomial module for scramble and the pattern; And generating the output signal based on the temporary output signal and the SYNC1 signal.

In addition, a method of operating a transmitter according to an embodiment may include receiving transmission data; Scrambled the transmission data; And after the SYNC2 signal transitions from an active state to an inactive state, transmitting the scrambled transmission data.

In addition, the predetermined pattern may include a pseudorandom binary sequence (PRBS) pattern.

According to an exemplary embodiment, a method of operating a receiver includes: descrambling a signal received from a transmitter, thereby generating an output signal including synchronization information; Extracting the synchronization information by determining whether the bit strings included in the output signal are in error; Generating a first control signal based on the synchronization information, the first control signal being deactivated in response to a normal bit string and activated in response to an error bit string; Generating a second control signal that is activated during bit strings between a next bit string and a next error bit string of the error bit string; Receiving transmission data from the transmitter; And processing the transmission data based on the first control signal and the second control signal.

In addition, the synchronization information may include first information on the timing of synchronization and second information on the width of data.

The generating of the output signal may include selecting an output of the polynomial module for the signal or the descramble as a temporary output signal based on the second control signal; And generating an input signal of the polynomial module based on the temporary output signal and the first control signal.

The generating of the output signal may include generating the output signal based on the signal and an output of the polynomial module for the descramble.

The processing of the transmission data may further include descrambling the transmission data; And after the second control signal transitions from an active state to an inactive state, receiving the descrambled transmission data according to a length of the second control signal.

In one embodiment, a transmitter includes a pattern generator for generating a predetermined pattern; Before the SYNC2 signal and the SYNC2 signal, which are control signals that are activated for bit strings corresponding to the width of the data, and are deactivated for the remaining bit strings, are activated for a predetermined number of bit strings, and before the SYNC2 signal is deactivated. A signal generator that is activated for a predetermined number of bit strings and generates a SYNC1 signal that is a control signal that is inactive for the remaining bit strings; And a scrambler that scrambles the pattern based on the SYNC1 signal and the SYNC2 signal to generate an output signal including synchronization information.

In addition, the synchronization information may include first information on the timing of synchronization and second information on the width of the data.

The scrambler may include a selector for selecting an output of the polynomial module for scramble or a temporary output signal for calculating the pattern and the output signal as an input of the polynomial module based on the SYNC2 signal.

The scrambler may include an XOR gate for performing an XOR operation on the output of the polynomial module for the pattern and scramble, and an XOR gate for performing the XOR operation on the temporary output signal and the SYNC1 signal.

The transmitter further includes a data generator for generating transmission data, wherein the scrambler scrambles the transmission data, and after the SYNC2 signal transitions from an active state to an inactive state, the scrambled transmission data Can be transmitted.

In addition, the transmitter according to an embodiment may further include a selector for selecting the transmission data or the pattern as an input of the scrambler.

In addition, the transmitter according to an embodiment may further include a parallel-serial conversion transmitter that receives the scrambled transmission data and converts it into serial data when the scrambled transmission data is parallel data.

In addition, the predetermined pattern may include a pseudorandom binary sequence (PRBS) pattern.

In an embodiment, a receiver may include a descrambler configured to generate an output signal including synchronization information by descrambled a signal received from a transmitter; Determining the error bit string included in the output signal, extracting the synchronization information, the first control signal and the error bit string of the first control signal is deactivated in response to a normal bit string based on the synchronization information, and is activated in response to an error bit string. A pattern checker for generating a second control signal that is activated during bit strings between a next bit string and a next error bit string; And a synchronizer and a data aligner for processing the transmission data based on the first control signal and the second control signal.

In addition, the receiver according to an embodiment, the descrambler includes a selector for selecting any one of the signal or the output of the polynomial module for descrambling as a temporary output signal based on the second control signal, the temporary An input signal of the polynomial module may be generated based on an output signal and the first control signal.

The descrambler may include an XOR gate that calculates an output signal and a first control signal of the selector, and an XOR gate that performs an XOR operation on the output of the polynomial module and the signal.

The synchronization and data aligner may receive, synchronize and align the descrambled transmission data to the length of the second control signal after the second control signal transitions from an active state to an inactive state.

In addition, the receiver according to an embodiment may further include a serial-to-parallel conversion receiver for converting the signal into parallel data and transmitting it to the descrambler when the signal is serial data.

The pattern checker may include a pseudorandom binary sequence (PRBS) pattern checker.

A method and apparatus for synchronizing and aligning bits using a scrambler and a descrambler according to embodiments may transmit a scrambled pattern for synchronization and check whether an error of the descrambled pattern occurs. In addition, the scrambler and the descrambler according to the embodiments perform data alignment for multiple channels, thereby enabling easy bit-by-bit synchronization and data alignment for multiple channels without overhead bits for synchronization.

1 is a flowchart illustrating a synchronization and data alignment method using a scrambler and a descrambler according to an embodiment.
2 is an operation flowchart illustrating a method of operating a transmitter according to an embodiment.
3 is a flowchart illustrating a method of operating a receiver according to an exemplary embodiment.
4 illustrates a scrambler according to an embodiment.
5 illustrates a descrambler according to an embodiment.
6A is a timing diagram of input and output signals and respective control signals of a scrambler according to one embodiment.
6B is a timing diagram of input and output signals and respective control signals of a descrambler according to one embodiment.
7 illustrates a synchronization method using a second control signal according to an embodiment.
8 illustrates a data alignment method using a second control signal according to an embodiment.

Specific structural or functional descriptions disclosed herein are illustrated for the purpose of describing embodiments only in accordance with a technical concept, and the embodiments may be embodied in various other forms and limited to the embodiments described herein. It doesn't work.

Terms such as first or second may be used to describe various components, but these terms should be understood only for the purpose of distinguishing one component from another. For example, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Expressions describing the relationship between the components, such as "between liver" and "immediately between" or "neighboring to" and "direct neighboring to" should be interpreted as well.

Singular expressions include plural expressions unless the context clearly indicates otherwise. As used herein, the terms "comprise" or "have" are intended to designate that the stated feature, number, step, action, component, part, or combination thereof is present, but one or more other features or numbers, It is to be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined herein. Do not.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

1 is a flowchart illustrating a synchronization and data alignment method using a scrambler and a descrambler according to an embodiment. Referring to FIG. 1, a system according to an embodiment includes a transmitter 100, a receiver 150, and a data channel 140. The transmitter 100 and the receiver 150 may communicate with each other via the data channel 140.

The transmitter 100 generates an output signal including synchronization information by using a predetermined pattern and transmits the generated output signal to the receiver 150. The transmitter 100 transmits transmission data to the receiver 150 based on the synchronization information.

According to an embodiment, the synchronization information may include first information about a timing of synchronization and second information about a width of data. For example, the synchronization information may include a first bit string indicating a time point of synchronization. The synchronization information may further include a second bit string indicating the width of data in combination with the first bit string. The first bit string and the second bit string may be generated based on a predetermined pattern. As will be described below, the receiver 150 may determine whether an error occurs in the bit string based on a predetermined pattern. The transmitter 100 may modify a predetermined pattern to indicate the first bit string and the second bit string. The transmitter 100 may transmit the transmission data to the receiver 150 after a time point corresponding to the second bit string.

The receiver 150 receives a signal from the transmitter 100 and extracts synchronization information from the received signal. The receiver 150 receives transmission data from the transmitter 100 based on the synchronization information.

For example, the receiver 150 may extract synchronization information by determining whether the bit strings included in the received signal are in error. The receiver 150 may determine whether the predetermined pattern is deformed, and may determine that an error occurs in the corresponding bit string when the predetermined pattern is deformed. The receiver 150 may extract the first bit string and the second bit string from the received signal, and extract synchronization information based on the first bit string and the second bit string. The receiver 150 may determine a signal received after a time point corresponding to the second bit string as transmission data and receive the transmission data.

The transmitter 100 includes a pattern generator 110, a signal generator 120, and a scrambler 125. In addition, the transmitter 100 may further include a selector 115, a data generator 115, a serializer / deserializer (SerDes) transmitter 130, or a combination thereof. Receiver 150 includes descrambler 160, pattern checker 165, bit sync and data aligner 170. In addition, the receiver 150 may further include a SerDes receiver 155.

The predetermined pattern may include a pseudorandom binary sequence (PRBS) pattern. The PRBS pattern is a bit string having a pseudorandomly generated pattern, and the PRBS generator may generate data in which data of length L repeats a pattern corresponding to a maximum sequence of 2 ^L −1. The PRBS pattern can be expressed using a predetermined polynomial, and can be generally implemented as a linear feedback shifter register (LFSR), and L values of 7, 9, 15, 23, 31, etc. are used, respectively, PRBS7, PRBS9, PRBS15, PRBS23, PRBS31 can be represented.

For example, the PRBS pattern using the corresponding polynomial is represented by the following polynomial.

PRBS7: G (x) = 1 + X ^ 6 + X ^ 7

PRBS9: G (x) = 1 + X ^ 5 + X ^ 9

PRBS15: G (x) = 1 + X ^ 14 + X ^ 15

PRBS23: G (x) = 1 + X ^ 18 + X ^ 23

PRBS31: G (x) = 1 + X ^ 28 + X ^ 31

However, in the above, G (x) means the generated PRBS pattern output.

2 is an operation flowchart illustrating a method of operating the transmitter 100 according to an embodiment. Referring to FIG. 2, the transmitter 100 receives 210 a pattern and transmission data and receives 230 a SYNC1, 2 signal, which is a control signal. The received pattern is scrambled 220 based on the received control signal to generate an output signal including the synchronization information, and is transmitted to the receiver 150.

3 is an operation flowchart illustrating a method of operating the receiver 150 according to an embodiment. Referring to FIG. 3, the receiver 150 receives 310 a signal and transmission data from a transmitter. The received signal is descrambled 320 to generate an output signal including the synchronization information, and the synchronization information is extracted 330. Based on the synchronization information, a first control signal and a second control signal, which are control signals, are generated 340. The descrambled transmission data is processed 350 based on the control signal.

Each component is described as follows. The pattern generator 110 generates a predetermined pattern. For example, when the data width is L, a pattern in which 15 states are repeated may be generated using the PRBS generator. The pattern generated by the pattern generator 110 may be applied to the scrambler 125.

According to an embodiment, the signal generator 120 is activated for a predetermined number of bit strings before the SYNC2 signal, which is a control signal for selecting an input of the polynomial module of the scrambler 125, and the SYNC2 signal, is activated. Before the signal is deactivated, it is possible to generate a SYNC1 signal, which is a control signal that is activated for a predetermined number of bit strings and deactivated for the remaining bit strings.

According to an embodiment, the scrambler 125 may also be implemented with LFSR and may be configured with a polynomial similar to the PRBS generator. The scrambler 125 may generate an output signal including synchronization information by scrambled the pattern received from the pattern generator 110 based on the SYNC1 signal and the SYNC2 signal. When the output signal is a parallel signal, parallel data may be converted into serial data through the SerDes transmitter 130 and transmitted to the SerDes receiver 155 through the data channel 140, and the SerDes receiver 155 may receive the serial data. May be converted into parallel data and transmitted to the descrambler 160. At the terminal, for example, the data are processed in parallel. However, in order to send data through an optical transmitter, parallel data must be serially converted. Likewise, serial data must be converted to parallel data in order to receive data through the optical receiver. In this case, the SerDes transmitter 130 and the SerDes receiver 155 may be used.

According to an embodiment, the descrambler 160 may also be implemented as an LFSR, and may be implemented in the same manner using the polynomial used in the scrambler 125. The descrambler 160 descrambles the signal received from the transmitter 100, thereby generating an output signal including synchronization information.

The output signal of the descrambler is input to the pattern checker 165, and the pattern checker 165 may determine whether the bit strings included in the output signal of the descrambler are reversed. In one embodiment, the pattern checker 165 may recognize an error when the data is inverted. In addition, the pattern checker 165 may extract the synchronization information by determining whether an error is generated, and based on the synchronization information, the pattern checker 165 generates a first control signal that is a signal indicating a time point when an error bit string occurs. A second control signal may be generated that is activated during bit strings between the next bit string of the error bit string and the next error bit string. The descrambler 160 may be controlled using the second control signal.

After the synchronization and data alignment period ends, the control mode may be changed from the pattern generator 110 to the data generator 105 using the transmitter selector 115 to transmit the actual data to be transmitted. The data generated by the data generator 105 is scrambled, transmitted to the receiver after the SYNC2 signal transitions from the active state to the inactive state, and descrambled scrambled data at the receiver to the bit sync and data aligner 170. send. The bit synchronization and data aligner 170 may receive the data according to the length of the second control signal to perform synchronization and data alignment.

4 is a diagram illustrating a scrambler according to one embodiment.

Referring to FIG. 4, the scrambler 125 may be implemented using the LFSR similarly to the existing scrambler. However, the difference between the scrambler used in the existing 64B / 66B is that the scrambler selector 430 selects one of two paths to receive the input of the polynomial module of the scrambler. In one embodiment, the two paths are as follows. Can be. The first path (path 1) is a path having the input signal of the polynomial module of the scrambler, which is a signal obtained by arithmetic through a predetermined logic circuit that defines the input signal of the scrambler and the output of the polynomial module of the scrambler. In this case, the predetermined logic circuit may include an XOR gate. The second path (path 2) is a path that receives the output of the scrambler's polynomial module directly as an input to the scrambler's polynomial module. These two paths can be selected by the scrambler selector 430 controlled by the SYNC2 signal. When the result of calculating the output and pattern of the polynomial module through a predetermined logic circuit is called a temporary output signal of the transmitter 100, the output signal of the scrambler is a logic circuit that predetermines the temporary output signal of the transmitter and the SYNC1 signal. It is the value calculated through. In this case, the predetermined logic circuit may include an XOR gate. Referring to FIG. 4, the output signal of the scrambler is obtained by calculating a temporary output signal and a SYNC1 signal of the transmitter 100, which is a result of calculating the output and pattern of the polynomial module through the XOR gate 410, through the XOR gate 420. Value. Details of the SYNC1 and SYNC2 signals, which are control signals, will be described later.

5 illustrates a descrambler according to an embodiment.

Referring to FIG. 5, the descrambler 160 receives a signal including synchronization information from the transmitter 100 as an input, uses the same polynomial as the scrambler 125, and may be implemented as an LFSR. In this case, like the scrambler 125, the descrambler 160 may receive one of two paths as an input of the polynomial module of the descrambler using the descrambler selector 530. The descrambler selector 530 may be controlled by the second control signal. Based on the second control signal, a signal received from the transmitter or an output of the polynomial module for descramble may be selected as a temporary output signal. The two paths can be: The first path, path 3 (path3), selects a signal received from a transmitter as a temporary output signal and has a result of calculating the first control signal and a predetermined logic circuit as an input of the polynomial module of the descrambler 160. to be. Path 4 (path4), which is the second path, selects the output of the polynomial module of the descrambler 160 as a temporary output signal, and calculates the result of the operation through the first control signal and a predetermined logic circuit of the polynomial module of the descrambler 160. The path to take as input. The output signal of the descrambler may be a value obtained by calculating a signal received from a transmitter and an output of the polynomial module of the descrambler 160 through a predetermined logic circuit. In this case, the predetermined logic circuit may include an XOR gate. For example, referring to FIG. 5, the path 3 (path3), which is the first path, selects a signal received from a transmitter as a temporary output signal, and descrambles a result obtained through the first control signal and the XOR gate 510. The path to the input of the polynomial module. The second path, path 4, is a path having the output of the polynomial module of the descrambler as a temporary output signal and having the result of the operation through the first control signal and the XOR gate 510 as the input of the polynomial module of the descrambler. . A detailed description of the first control signal and the second control signal will be described later in the following paragraphs.

6A illustrates a timing diagram of input and output signals and respective control signals of a scrambler according to one embodiment.

Referring to FIG. 6A, when the scrambler input signal is a pattern generated by the pattern generator 110 and is, for example, a pattern generated by the PRBS generator, the scrambler input signal includes a polynomial such as general PRBS7, PRBS9, PRBS15, PRBS23, and PRBS31. It may be an output data value. P (1), p (2), ..., p (k), ..., p (k + w), ... in FIG. 6A correspond to 2 ^L -1 of the length L of the polynomial The sequence of bits can be repeated and output. The length L of the polynomial can be set as appropriate during the design phase of the PRBS generator. For example, ITU-T Rec. In standards such as O. 150 / O.151, PRBS7, PRBS15, PRBS31, etc. can be used as standard PRBS. The length of the polynomial of the aforementioned PRBS # (where # is a positive integer) may be #, for example, the length of the polynomial of PRBS7 is 7 and the length of the polynomial of PRBS23 may be 23.

According to one embodiment, the pattern is input as a scrambler input signal, the control signal of the scrambler 125 according to each input may operate as follows. The SYNC1 and SYNC2 signals may be generated at the signal generator 120. When the pattern generator generates a pattern and starts bit synchronization and data alignment, the signal generator can generate a SYNC2 signal. Referring to FIG. 6A, a point in time at which the scrambler input signal is p (k + 1) generates a pattern and starts a bit synchronization and data alignment, that is, a point in time at which the SYNC2 signal is generated. The SYNC2 signal is a signal that is activated during bit strings corresponding to the length W of the data width. For example, when 64 bits are transmitted to the SerDes transmitter 130 in parallel data units to convert parallel data into serial data, 64 corresponds to a W value. The SYNC1 signal is activated for a predetermined number of bit strings before the SYNC2 signal is activated (if it has a value of '1') and also deactivated (if it has a value of '0'), as shown in FIG. 6A. It can be activated for a previously predetermined number of bit strings.

According to an embodiment, considering the above-described signals as shown in the scrambler 125 shown in Figure 4 can be operated as follows. Initially, since the SYNC2 signal is inactivated, it can operate according to the path 1 (path1) described above. A signal obtained by calculating the output of the polynomial module of the pattern and the scrambler through the XOR gate 410 is received as an input of the polynomial module of the scrambler. Thereafter, the output and pattern of the polynomial module of the scrambler can be computed through the XOR gate 410. The calculated value and the SYNC1 signal are calculated through the XOR gate 420. At this time, the SYNC1 signal and the value before the SYNC1 signal and the SYNC1 signal are calculated even though the SYNC1 signal is inactivated. Can be. If this is expressed as a specific data value, the input signals of the scrambler are p (1), p (2), ..., p (k) which are patterns, and the output signals of the scrambler corresponding thereto are m (1) and m (2). ), ..., m (k). P (#), m (#), and a (#) mean a bit string having one or more numbers. At this time, since the value of the SYNC1 signal is activated (the value of '1' in FIG. 6A) at the output time corresponding to the m (k) value, when the pattern p (k) at that time is input to the scrambler input signal, The activated SYNC1 signal (the value of '1' in FIG. 6A) and the scrambler output signal that performs the XOR operation output m * (k), which is an inverted value of the m (k) data. The SYNC2 signal is then activated by the length of the bit string corresponding to the data width (a value of '1' in FIG. 6A), which means that the output of the scrambler's polynomial module is directly connected to the input of the scrambler's polynomial module. The pattern is not entered into the scrambler's polynomial module. In addition, a (1), a (2), ..., a (w) are output as scrambler output signals, at which point the SYNC1 signal is activated again at an output time corresponding to the a (w) value, which is the last output value (Fig. In case of 6a, a * (w), which is an inverted value of a (w) data, is output as a scrambler output signal. Thereafter, the SYNC2 signal is deactivated again (the value of '0' in FIG. 6A) to select the path 1. The transmitter 100 outputs by inverting the bits related to the start and end points to be synchronized using the SYNC1 and 2 signals and the scrambler 125 (m * (k) and a * (w) in FIG. 6A). The output including the synchronization information may be transmitted to the descrambler 160 of the receiver 150.

FIG. 6B illustrates a timing diagram of input and output signals and control signals of the descrambler 160 according to an exemplary embodiment. Referring to FIG. 6B, the descrambler 160 receiving the output signal of the transmitter including synchronization information through the data channel 140 may operate as follows. At the time when the signals received from the transmitter are m (1), m (2), ..., and m * (k), the second control signal, which is the control signal of the descrambler, is deactivated. Can work accordingly. Accordingly, the signal received from the transmitter is selected as the input of the descrambler selector 530 as it is, and the output of the descrambler polynomial module and the signal received from the transmitter are XORed and output as a descrambler output signal, which is a scrambler 125. P (1), p (2), ..., p * (k) values generated at Since the output value p * (k) of the descrambler is an inverted state of the normal p (k) value, the pattern checker 165 may recognize the error bit string as an error bit string and display the result as an error state. The control signal value indicating the error state of the pattern checker corresponds to the first control signal, and in the case of the error state, is activated during the corresponding bit string, and may be inactivated during the recognition of the normal pattern. In addition, the first control signal may be calculated through the output signal of the descrambler selector 530 and the XOR gate 520 to be input to the polynomial module of the descrambler. This is to invert a descrambler input signal that causes an error so that a normal value is input to the polynomial module of the descrambler. And in the pattern checker 165, generates a second control signal that is activated during bit strings between the next bit string of the error bit string and the next error bit string, and consequently remains active for the bit strings corresponding to the data width. can do. When the second control signal is activated, the path may be changed from path 3 (path 3) to path 4 (path 4) through the descrambler selector 530. When the path is changed to path 4, the input values a (1), a (2), ..., a * (w) generated through path 2 of path scrambler 125 are input. (k + 1), p (k + 2), ..., p * (k + w) can be output. The last output value p * (k + w) output through the path 4 again generates an error signal (change so that the first control signal is activated) through the pattern checker 165, which causes the second control signal to be deactivated. The path can be changed from 4 to path 3. In addition, in order to prevent the descrambler input signal in an error state from being input to the polynomial module of the descrambler, the output of the descrambler selector 530 and the first control signal are calculated through the XOR gate 520. Can be entered into the polynomial module of the descrambler.

Synchronization signal generation for specific bit synchronization is as follows.

In one embodiment, the PRBS pattern is generated in the PRBS generator 105 during the bit synchronization and word alignment period, and then after the bit synchronization and data alignment is completed (the time when the SYNC2 signal transitions from the active state to the inactive state). In the data generator 105, data to be actually sent may be generated and transmitted.

7 is a diagram illustrating a synchronization method using a second control signal according to an embodiment.

Referring to FIG. 7, the receiver generates a second control signal having bit strings corresponding to the length W of the data width, which converts serial data that is not bit-synchronized into parallel data by a random delay time. When used as a conversion signal for converting parallel data in units of data width length W, bit synchronization may be achieved. After the synchronization and data alignment period ends, i.e., after the SYNC2 signal transitions from the active state to the inactive state, the control mode is changed from the pattern generator 110 using the transmitter selector 115 to transmit the actual data to be transmitted. Can be changed with the data generator 105. D (1) in the data generator 105. d (2), ..., d (w) data can be generated. The generated data is scrambled by the transmitter 100 and transmitted to the receiver 150, and then descrambled by the receiver 150 and recovered. The data strings of p (k + 1), p (k + 2), ..., p (k + w) values corresponding to a section in which the second control signal is maintained active by the data width length W are parallel. Bit synchronization can be achieved by grouping data units. After that, the output of the descrambler is continuously bundled for each length (W) of the data width and converted into parallel data to maintain bit synchronization.

8 is a diagram illustrating a data sorting method using a second control signal, according to an exemplary embodiment. 8 illustrates a specific example of a method of word-aligning data for multiple channels. In a multi-channel, data having bit synchronization for each channel has a data width W and may be input and stored in each FIFO for each channel. The storage order is independent for each channel and can be stored as soon as valid data arrives. The read operation for data alignment refers to a second control signal, which reads FIFO data of all channels at this time with respect to the most recently activated channel of the second control signals of each channel. You can have output data sorted at the same time. More specifically, it is assumed that the transmitter 110 transmits a pattern simultaneously in the same order as W (1), W (2), W (3), and W (4) for all channels. In this case, as shown in FIG. 8, data may arrive at the receiver in order of W (1), W (2), W (3), and W (4) for each channel through a bit synchronization process. However, as described above, since the delay time is different for each channel due to various factors, the time points input to the reception FIFO may be different for the pattern string. As shown in FIG. 8, it can be seen that the bit string of channel 1 arrives first while the bit string of channel 2 arrives last. This can be known using the activation state time point of the second control signal. By comparing the activation time points of the second control signals corresponding to each channel, the FIFOs of all channels may be read at that time on the basis of the last activated channel. As shown in FIG. 8, when the read signals of all channels are activated on the basis of the second control signal of channel 2, which is the channel in which the second control signal is activated last, among the lanes from channel 0 to channel 3 The data of all channels stored in the FIFO can be read at the same time so that the output data can be aligned at the same time.

The embodiments described above may be implemented as hardware components, software components, or a combination of hardware components and software components. For example, the devices, methods, and components described in the embodiments may include, for example, processors, controllers, arithmetic logic units (ALUs), digital signal processors, microcomputers, field programmable gates (FPGAs). It may be implemented using one or more general purpose or special purpose computers, such as an array, a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to the execution of the software. For convenience of explanation, one processing device may be described as being used, but one of ordinary skill in the art will appreciate that the processing device includes a plurality of processing elements and / or a plurality of types of processing elements. It can be seen that it may include. For example, the processing device may include a plurality of processors or one processor and one controller. In addition, other processing configurations are possible, such as parallel processors.

The software may include a computer program, code, instructions, or a combination of one or more of the above, and configure the processing device to operate as desired, or process it independently or collectively. You can command the device. Software and / or data may be any type of machine, component, physical device, virtual equipment, computer storage medium or device in order to be interpreted by or to provide instructions or data to the processing device. Or may be permanently or temporarily embodied in a signal wave to be transmitted. The software may be distributed over networked computer systems so that they may be stored or executed in a distributed manner. Software and data may be stored on one or more computer readable recording media.

The method according to the embodiment may be embodied in the form of program instructions that can be executed by various computer means and recorded in a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the media may be those specially designed and constructed for the purposes of the embodiments, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Magneto-optical media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

Although the embodiments have been described with reference to the accompanying drawings, those skilled in the art may apply various technical modifications and variations based on the above. For example, the described techniques may be performed in a different order than the described method, and / or components of the described systems, structures, devices, circuits, etc. may be combined or combined in a different form than the described method, or other components. Or even if replaced or substituted by equivalents, an appropriate result can be achieved.

Claims (25)

Receiving a predetermined pattern;
Receiving a SYNC2 signal, which is a control signal that is activated for bit strings corresponding to the width of data and is inactive for the remaining bit strings;
Receiving a SYNC1 signal, which is a control signal that is activated for a predetermined number of bit strings before the SYNC2 signal is activated, is activated for a predetermined number of bit strings before the SYNC2 signal is inactivated, and is inactivated for the remaining bit strings. ;
Scrambled the pattern based on the SYNC1 signal and the SYNC2 signal to generate an output signal comprising synchronization information; And
Transmitting the output signal
Including, the method of operation of the transmitter.
The method of claim 1,
The synchronization information is
A first information for the timing of synchronization and a second information for the width of the data.
The method of claim 1,
Generating the output signal
Selecting, based on the SYNC2 signal, an output of the polynomial module for scramble, or a temporary output signal for computing the pattern and the output signal as an input of the polynomial module;
Including, the method of operation of the transmitter.
The method of claim 1,
Generating the output signal
Generating a temporary output signal based on the output of the polynomial module for scrambled with the pattern; And
Generating the output signal based on the temporary output signal and the SYNC1 signal
Including, the method of operation of the transmitter.
The method of claim 1,
Receiving transmission data;
Scrambled the transmission data; And
Transmitting the scrambled transmission data after the SYNC2 signal transitions from an active state to an inactive state
Further comprising a method of operating the transmitter.
The method of claim 1,
The predetermined pattern is
A method of operation of a transmitter comprising a pseudorandom binary sequence (PRBS) pattern.
Descrambling the signal received from the transmitter, thereby generating an output signal comprising synchronization information;
Extracting the synchronization information by determining whether the bit strings included in the output signal are in error;
Generating a first control signal based on the synchronization information, the first control signal being deactivated in response to a normal bit string and activated in response to an error bit string;
Generating a second control signal that is activated during bit strings between a next bit string and a next error bit string of the error bit string;
Receiving transmission data from the transmitter; And
Processing the transmission data based on the first control signal and the second control signal.
Including, the method of operation of the receiver.
The method of claim 7, wherein
The synchronization information is
A first information for the timing of synchronization and second information for the width of the data.
The method of claim 7, wherein
Generating the output signal
Selecting an output of the polynomial module for descrambling as a temporary output signal based on the second control signal; And
Generating an input signal of the polynomial module based on the temporary output signal and the first control signal;
Including, the method of operation of the receiver.
The method of claim 7, wherein
Generating the output signal
Generating the output signal based on the signal and an output of a polynomial module for the descramble
Including, the method of operation of the receiver.
The method of claim 7, wherein
Processing the transmission data
Descrambling the transmission data; And
After the second control signal transitions from an active state to an inactive state, receiving the descrambled transmission data according to a length of the second control signal
It comprises a method of operation of the receiver.
A pattern generator for generating a predetermined pattern;
Before the SYNC2 signal and the SYNC2 signal, which are control signals that are activated for bit strings corresponding to the width of the data, and are deactivated for the remaining bit strings, are activated for a predetermined number of bit strings, and before the SYNC2 signal is deactivated. A signal generator that is activated for a predetermined number of bit strings and generates a SYNC1 signal that is a control signal that is inactive for the remaining bit strings; And
A scrambler for generating an output signal including synchronization information by scrambled the pattern based on the SYNC1 signal and the SYNC2 signal;
Transmitter comprising a. The method of claim 12,
The synchronization information is
A first information for the timing of synchronization and a second information for the width of the data.
The method of claim 12,
The scrambler includes a selector for selecting, based on the SYNC2 signal, an output of the polynomial module for scramble or a temporary output signal that computes the pattern and the output signal as an input of the polynomial module.
The method of claim 12,
The scrambler includes an XOR gate for performing an XOR operation on the output of the polynomial module for the pattern and scramble, and an XOR gate for performing the XOR operation on the temporary output signal and the SYNC1 signal.
The method of claim 12,
Further comprising a data generator for generating transmission data,
And the scrambler scrambles the transmission data and transmits the scrambled transmission data after the SYNC2 signal transitions from an active state to an inactive state.
The method of claim 12,
And a selector for selecting the transmission data or the pattern as an input of the scrambler.
The method of claim 12,
And a parallel-serial conversion transmitter for receiving and converting the scrambled transmission data into serial data when the scrambled transmission data is parallel data.
The method of claim 12,
The predetermined pattern is
A transmitter comprising a pseudorandom binary sequence (PRBS) pattern.
A descrambler that descrambles a signal received from a transmitter, thereby generating an output signal comprising synchronization information;
Determining the error bit string included in the output signal, extracting the synchronization information, the first control signal and the error bit string of the first control signal is deactivated in response to a normal bit string based on the synchronization information, and is activated in response to an error bit string. A pattern checker for generating a second control signal that is activated during bit strings between a next bit string and a next error bit string; And
A synchronization and data sorter for processing the transmission data based on the first control signal and the second control signal
Including, the receiver.
The method of claim 20,
The descrambler includes a selector for selecting any one of the signal or the output of the polynomial module for descrambling as a temporary output signal based on the second control signal,
Generating an input signal of the polynomial module based on the temporary output signal and the first control signal
receiving set.
The method of claim 20,
The descrambler includes an XOR gate for calculating an output signal and a first control signal of the selector, and an XOR gate for XORing the output of the polynomial module and the signal.
The method of claim 20,
The sync and data sorter
And after the second control signal transitions from an activated state to an inactive state, descrambled transmission data is received according to a length of the second control signal to synchronize and data align.
The method of claim 20,
And if the signal is serial data, further comprising a serial-to-parallel conversion receiver for converting the signal into parallel data and transmitting the same to the descrambler.
The method of claim 20,
The pattern checker,
A receiver comprising a pseudorandom binary sequence (PRBS) pattern checker.

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