KR20190037749A - Level shifter device using serial interface and display device having the same - Google Patents

Abstract

The present invention relates to a display device having a level shifter unit, capable of minimizing the number of input signals regardless of the number of output signals and an operation mode using a serial interface. According to an embodiment of the present invention, a timing controller serializes a plurality of control data for determining an output level of a plurality of gate control signals output from a level shifter to a gate driver in a specific time unit and transmits the serialized control data to a level shifter unit in accordance with a clock for each specific time unit. The level shifter unit includes: a plurality of level shifters for individually outputting a plurality of gate control signals; and a decoder for receiving a plurality of control data serialized by a timing controller to latch the same, and controlling an output level of each of the level shifters for each specific time unit by using the latched control data.

Description

TECHNICAL FIELD [0001] The present invention relates to a display device having a level shifter section using a serial interface,

The present invention relates to a display device having a level shifter section which can minimize the number of input signals regardless of the number of output signals and the operation mode by using a serial interface.

Recently, display devices that display images using digital data include liquid crystal displays (LCDs) using liquid crystals, OLED displays using organic light emitting diodes, electrophoretic displays using electrophoretic particles ElectroPhoretic Display (EPD).

The display device includes a panel for displaying an image through a pixel array in which each pixel is independently driven by a thin film transistor (TFT), a gate driver and a data driver for driving the panel, a gate driver and a data driver And the like.

Recently, a gate driver is formed together with a TFT array of a pixel array, and a gate-in-panel (GIP) type built in a panel is applied. A level shifter is located between the timing controller and the GIP type internal gate driver.

The level shifter receives a clock and an off-clock from the timing controller, generates a plurality of gate clocks, and outputs the gate clocks to the gate driver. The level shifter further receives other gate control signals such as a start signal, a reset signal, and the like from the timing controller, level-shifts the logic level to a gate high / low voltage, and outputs the level shift to the gate driver.

However, in the conventional level shifter, as the number of output signals increases, the number of input signals supplied from the timing controller must increase.

For example, in order to improve the luminance non-uniformity due to the characteristic deviation between sub-pixels, the OLED display device uses an external compensation technique which senses the electrical characteristics of each sub-pixel and compensates for the characteristic deviation of each sub- .

In the OLED display, the gate driver supplies a scan pulse to the gate lines for scanning and a sense pulse to the gate lines for sensing. The level shifter supplies the scan clocks used in the generation of the scan pulse and the sense clocks used in the generation of the sense pulse to the gate driver, and further supplies the carry clocks used as the carry signal in the gate driver.

To this end, the level shifter unit must receive three pairs of on-clock and off-clock from the timing controller to generate scan clocks, carry clocks, and sense clocks. In addition, in the real-time sensing operation mode of the OLED display, the level shifter unit must further receive additional gate control signals from the timing controller necessary to select the horizontal line to be sensed in the gate driver.

As described above, the conventional level shifter has a disadvantage that the number of transmission signals between the timing controller and the level shifter increases as the number of output signals increases. This increases the number of output pins of the timing controller and the number of input pins of the level shifter and increases the number of routing wires and the routing area between the timing controller and the level shifter on the printed circuit board (PCB) There is a problem that reliability of a transmission signal is deteriorated due to increase of electromagnetic interference (EMI).

The present invention provides a display device having a level shifter capable of minimizing the number of input signals regardless of the number of output signals and the operation mode using a serial interface.

The present invention provides a display device capable of minimizing the number of wires between a timing controller and a level shifter unit using a serial interface.

The display device according to one embodiment includes a gate driver, a level shifter, and a timing controller. The timing controller serializes a plurality of control data for determining an output level of each of the plurality of gate control signals output from the level shifter to the gate driver in a specific time unit, and sets a plurality of serialized control data to a clock To the shifter section.

A level shifter according to an embodiment includes a plurality of level shifters for individually outputting a plurality of gate control signals, a plurality of control data serialized from the timing controller, and latches the latched control data, And a decoder for controlling the output level of each of the plurality of level shifters per unit.

The timing controller according to an embodiment further generates a latch enable signal for controlling the timing of outputting a plurality of control data latched every specific time unit. The timing controller transmits a clock, a plurality of serialized control data, and a latch enable signal to the level shifter through the first to third wirings.

The timing controller according to an exemplary embodiment generates a control bit stream by serializing a plurality of control bits indicating an output level of each of a plurality of gate control signals in 1 or 2 bits for each horizontal period, And transmits the control bit stream to the level shifter in synchronization with the clock. The level shifter samples and latches the control bit stream transmitted in each horizontal period according to the clock and determines the output level of each of the plurality of gate control signals in the next horizontal period using a plurality of control bits in accordance with the latch enable signal do.

The gate driver is embedded in a panel including a pixel array. Each sub-pixel constituting the pixel array includes a light-emitting element and a pixel circuit for independently driving the light-emitting element. The gate driver supplies a scan pulse to the scan gate line connected to each subpixel, and supplies a sense pulse to the sense gate line connected to each subpixel. The plurality of level shifters according to an embodiment may include a plurality of scan clocks, a plurality of sense clocks, a plurality of carry clocks, a start pulse, a reset pulse, an even frame drive voltage, A plurality of gate control signals including control signals necessary for the sensing operation of the pixel are individually generated and supplied to the gate driver.

Each subpixel constituting the pixel array includes a thin film transistor that independently drives a liquid crystal capacitor, and a gate driver supplies a scan pulse to a gate line connected to each subpixel. The plurality of level shifters according to an embodiment individually generates a plurality of gate control signals including a plurality of scan clocks, a start pulse, a reset pulse, an even frame drive voltage, and an odd frame drive voltage, and supplies the generated gate control signals to the gate driver.

The decoder of the level shifter unit outputs the output of the first gate control signal output from the first level shifter in the next horizontal period to the gate on voltage Vcc using the first control bit to which one bit is assigned in each horizontal period of the plurality of control bits Or a gate-off voltage.

The decoder of the level shifter unit outputs the output of the second gate control signal output from the second level shifter in the next horizontal period by using the second control bit assigned 1 bit or 2 bits in each horizontal period among the plurality of control bits Gate on voltage, gate off voltage, or GPM output.

A first bit with a second control bit may be assigned to indicate holding GPM output or previous horizontal period output.

The level shifter counts the number of supplied clocks in each horizontal period, recognizes it as an abnormal state if it is smaller than the set value, holds the latch operation, and maintains the output of the previous horizontal period.

The timing controller and the level shifter according to the embodiment transmit various gate control data using the serial interface so that the number of wires between the timing controller and the level shifter is minimized to three regardless of the number of output signals of the level shifter and the operation mode can do.

Accordingly, even if the number of output signals of the level shifter unit increases, the number of wirings between the timing controller and the level shifter unit is minimized to three, thereby reducing the number of output pins of the timing controller, the number of input pins of the level shifter unit, The number of routing wires and the routing area between the timing controller and the level shifter portion can be minimized, thereby reducing cost and EMI.

The level shifter unit and the display device according to an exemplary embodiment may be applied to all display devices such as an OLED display device, an LCD, and the like.

1 is a system block diagram schematically showing a configuration of an OLED display device according to an embodiment of the present invention.
2 is an equivalent circuit diagram illustrating the configuration of one subpixel shown in FIG.
3 is a block diagram schematically showing the configuration of a timing controller, a level shifter, and a gate driver according to an embodiment of the present invention.
4 is a waveform diagram illustrating input signals of a level shifter according to an exemplary embodiment of the present invention.
5 is a diagram illustrating a part of a level shifter according to an embodiment of the present invention.
6 is a waveform diagram illustrating a part of output signals of a level shifter according to an embodiment of the present invention.
7 is a waveform diagram illustrating a method of generating a gate pulse modulated waveform in a level shifter according to an embodiment of the present invention.
8 is a block diagram schematically illustrating an LCD configuration according to an embodiment of the present invention.
9 is a diagram illustrating transmission lines between the timing controller and the level shifter unit and the gate driver shown in FIG.
10 is a waveform diagram illustrating input signals of the level shifter shown in FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a circuit block diagram schematically showing a configuration of an OLED display device according to an embodiment of the present invention.

1, an OLED display device includes a panel 100, a gate driver 200, a data driver 300, a timing controller 400, a power supply unit 500, a level shifter unit 600, A memory 700, a memory 800, and the like. The timing controller 400, the power supply unit 500, the level shifter unit 600, the gamma voltage generator 700, and the like may be configured as individual integrated circuits (ICs) and mounted on the PCB.

The power supply unit 500 includes all the circuit configurations of the display device, that is, the panel 100, the gate driver 200, the data driver 300, the timing controller 400, the level shifter unit 600, the reference gamma voltage generator 700, the memory 800, and the like. For example, the power supply unit 500 may supply the digital driving voltage supplied to the timing controller 400, the data driver 300, the level shifter unit 600, and the like using the input voltage, A gate-on voltage VGH and a gate-off voltage VGL supplied to the gate driver 200 and the level shifter 600 and a plurality of drive voltages EVDD and EVSS necessary for driving the panel 100, , And generates a reference voltage and supplies it to the panel 100 through the data driver 300.

The panel 100 displays an image through a pixel array PA in which sub-pixels SP are arranged in a matrix form. The basic pixel can be composed of at least three subpixels capable of white representation by color mixing among white (W), red (R), green (G) and blue (B) subpixels. For example, the basic pixel may be subpixels of R / G / B combination, subpixels of W / R / G combination, subpixels of B / W / R combination, subpixels of G / Or a combination of W / R / G / B combinations of subpixels.

The gate driver 200 individually drives the gate lines of the panel 100 using a plurality of gate control signals supplied from the level shifter 600. The gate driver 200 supplies the gate-on voltage VGH (gate-on voltage) to the gate line during the driving period of the gate line, and the gate-off voltage VGL (gate-off voltage) during the non- And supplies it to the corresponding gate line. The gate driver 200 supplies a scan pulse to the scan gate line and a sense pulse to the sense gate line.

The gate driver 200 may be formed on the substrate together with the thin film transistor array constituting the pixel array PA of the panel 100 so that the gate driver 200 may be built in the GIP (Gate In Panel) type in the non- have. The GIP type gate driver 200 may be located on one side of the panel 100 or on both sides of the panel 100.

On the other hand, the gate driver 200 is composed of a plurality of gate ICs, and is individually mounted on a circuit film such as a COF (Chip On Film) or the like to be bonded to the panel 100 by TAB (Tape Automatic Bonding) On Glass) method on the panel 100.

The gamma voltage generator 700 generates a reference gamma voltage set including a plurality of reference gamma voltages having different voltage levels and supplies a reference gamma voltage set to the data driver 300. [

The data driver 300 converts the image data supplied from the timing controller 400 into an analog data signal according to a data control signal supplied from the timing controller 400 and supplies the analog data signal to the data lines of the panel 100. The data driver 300 subdivides the reference gamma voltage set supplied from the gamma voltage generator 700 into a plurality of gradation voltages corresponding to the gradation values of the data. The data driver 300 converts the digital data into analog data voltages using the subdivided gradation voltages and supplies the data voltages to the data lines of the panel 100. [ The data driver 300 supplies the reference voltage Vref supplied from the voltage supply unit 500 to the reference lines of the panel 100 under the control of the timing controller 400.

The data driver 300 supplies a sensing data voltage to a data line to drive each sub-pixel in a sensing mode under the control of the timing controller 400 and outputs a pixel current Through a reference line, converts the sensed data into digital sensing data, and provides the digital sensing data to the timing controller 400. [

The data driver 300 may include a plurality of data ICs, may be mounted on a circuit film such as a COF, and may be bonded to the panel 100 by a TAB method or may be mounted on the panel 100 by a COG method.

The timing controller 400 receives image data and input timing control signals from the host system. The host system can be any one of a system of a portable terminal such as a computer, a TV system, a set-top box, a tablet or a cellular phone. The input timing control signals may include a dot clock, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and the like.

The timing controller 400 controls the timing of driving the data driver 300 using the input timing control signals supplied from the system and the timing setting information (start timing, pulse width, etc.) And supplies the generated data to the data driver 300. For example, the plurality of data control signals may include a source start pulse used for controlling latch timing of data, a source sampling clock, a source output enable signal for controlling an output period of the data signal, and the like.

The timing controller 400 performs various image processes such as luminance correction for reducing power consumption, image quality correction, and the like, on the image data supplied from the system. The timing controller 400 compensates the image data by applying a compensation value for the characteristic deviation of each subpixel stored in the memory 500 and supplies the compensated image data to the data driver 300.

The timing controller 400 senses the electrical characteristics (Vth of the driving TFT, mobility, Vth of the OLED, etc.) of each sub-pixel of the panel 100 through the data driver 300, The compensation value of each sub pixel stored in the memory 500 is updated.

For example, the timing controller 400 uses the information obtained by sensing the linear section in which the source voltage increases by driving the driving TFT in each sub-pixel, and calculates the mobility variation amount of the driving TFT sensitive to the driving environment such as temperature and light And updates the mobility compensation value of each sub pixel stored in the memory 500 using the calculation result. Since the mobility sensing for updating the mobility compensation value operates in a fast mode in which the sensing time is relatively short, the on-sensing (ON RF) mode mainly allocated to the power-on period and the on- (RT) mode assigned to the vertical blanking period of < / RTI >

The timing controller 400 senses the Vth of the driving TFT by using information obtained by sensing a period in which the driving TFT is driven in each sub-pixel and the source voltage reaches the saturation state, The Vth compensation value of the subpixel is updated. The Vth compensation value compensates for the Vth deviation of the sub-pixel driving TFT and also compensates for the Vth shifted by the electrical stress while the driving time has elapsed. Since the Vth sensing for updating the Vth compensation value operates in a slow mode requiring a longer sensing time than the fast mode described above, the Vth sensing can be performed in an off-sensing (OFF RS) mode mainly allocated to a power-off period.

In particular, the timing controller 400 generates a plurality of gate control signals for determining the output level of each of the plurality of gate control signals generated by the level shifter 600, using input timing control signals supplied from the system and internal timing setting information And generates gate control data. The timing controller 400 serializes and converts a plurality of gate control data into transmission units every predetermined time at which the output level of any one of the gate control signals changes and outputs the serial control gate control data together with the clock signal to the level shifter unit 600). A detailed description thereof will be described later. The timing controller 400 supplies a latch enable signal for instructing the latch and output timing of the gate control data in the level shifter 600 for a predetermined time, for example, one horizontal period (1H) to the level shifter 600 ).

The level shifter 600 sequentially samples and latches the gate control data supplied from the timing controller 400 in accordance with the clock, simultaneously outputs the gate control data in response to the latch enable signal, And generates and outputs a plurality of gate control signals whose levels are determined. A detailed description thereof will be described later.

Thus, the transmission line between the timing controller 400 and the level shifter 600 is divided into a first wiring for transmitting a clock, regardless of the number of output signals of the level shifter 600, A third wiring for transmitting a latch enable signal, and a third wiring for transmitting a latch enable signal.

2 is an equivalent circuit diagram illustrating the configuration of one subpixel shown in FIG.

2, each subpixel SP is connected between a high potential driving voltage (first driving voltage: EVDD) line PW1 and a low potential driving voltage (second driving voltage: EVSS) line PW2 A pixel circuit including at least a first and a second switching TFTs ST1 and ST2 and a driving TFT DT and a storage capacitor Cst to independently drive the OLED element 10, Respectively. On the other hand, since the pixel circuit has various configurations other than the configuration of FIG. 2, various configurations can be applied.

The switching TFTs ST1 and ST2 and the driving TFT DT may be an amorphous silicon (a-Si) TFT, a poly-Si TFT, an oxide TFT, an organic TFT or the like have.

The OLED element 10 has an anode connected to the source node N2 of the driving TFT DT, a cathode connected to the EVSS line PW2, and an organic light emitting layer between the anode and the cathode. The anode is independent for each subpixel, but the cathode may be a common electrode shared by all the subpixels. When a driving current is supplied from the driving TFT DT, electrons from the cathode are injected into the organic light-emitting layer, holes from the anode are injected into the organic light-emitting layer, and electrons and holes recombine in the organic light- By emitting phosphors, light of brightness proportional to the current value of the drive current is generated.

The first switching TFT ST1 is driven by the scan pulse SCn supplied to the gate line Gn1 from the gate driver 200 and is driven by the data voltage Dm supplied from the data driver 300 to the data line Dm Vdata) to the gate node N1 of the driving TFT DT.

The second switching TFT ST2 is driven by the sense pulse SEn supplied from the gate driver 200 to the other gate line Gn2 and is driven by the reference voltage Vdd supplied from the data driver 300 to the reference line Rm Vref to the source node N2 of the driving TFT DT.

The storage capacitor Cst connected between the gate node N1 and the source node N2 of the driving TFT DT is connected to the gate node N1 and the source node N2 through the first and second switching TFTs ST1 and ST2. The first and second switching TFTs ST1 and ST2 are turned off when the difference voltage between the data voltage Vdata and the reference voltage Vref supplied to the first and second switching TFTs N1 and N2 is charged to the driving voltage Vgs of the driving TFT DT, And holds the charged driving voltage Vgs during the light emission period.

The driving TFT DT controls the current supplied from the EVDD line PW1 in accordance with the driving voltage Vgs supplied from the storage capacitor Cst to drive the driving current determined by the driving voltage Vgs to the OLED element 10 Thereby causing the OLED element 10 to emit light.

On the other hand, when the sub-pixel SP is in the sensing mode, the driving TFT DT supplies the sensing data voltage Vdata, which is supplied through the data line Dm and the first switching TFT ST1, And a reference voltage (Vref) supplied through the second switching TFT (ST2). The pixel current reflecting the electrical characteristic (Vth, mobility) of the driving TFT DT is charged to the line capacitor of the reference line Rm which is floating through the second switching TFT ST2. The data driver 300 samples the voltage charged in the reference line Rm and converts it into sensing data of each subpixel SP and outputs it to the timing controller 400. [

FIG. 3 is a block diagram schematically showing the configuration of a timing controller, a level shifter, and a gate driver according to an embodiment of the present invention. FIG. 4 is a circuit diagram showing a part of a level shifter according to an embodiment of the present invention FIG. 5 is a waveform diagram illustrating input / output signals of a level shifter according to an embodiment of the present invention, and FIG. 6 is a waveform diagram illustrating input / output signals of a gate driver according to an embodiment of the present invention.

Referring to FIG. 3, the timing controller 400 and the level shifter 600 are mounted on the control PCB, and the gate driver 200 may be embedded in the panel 100. The transmission path between the control PCB and the panel 100 can be via a FFC (Flat Flexible Cable), a source PCB, a COF on which a data IC is mounted, and the like.

A plurality of gate control signals output from the level shifter 600 to the gate driver 200 are supplied to the scan drivers 200 through the scan clocks SCCLK1 through SLCLKm, the sense clocks SECLK1 through SECLKm, the carry clocks CRCLK1 through CRCLKm, The gate driver 200 includes a reset pulse RST, a line selection pulse LSP, a clock shift stop pulse CSP, an even drive voltage GVDD_E and an odd drive voltage GVDD_O. And may further include other gate control signals indicating a forward or reverse scan order or the like.

Each of the plurality of scan clocks SCCLK1 to SCLKMm having different phases is used as a scan pulse SC in the gate driver 200. [ Each of the plurality of sense clocks SECLK1 to SECLKm having different phases is used as a sense pulse SE in the gate driver 200. [ A plurality of carry clocks (CRCLK1 to CRCLKm) having different phases are used as a carry signal for controlling the shift operation in the gate driver (200). The start pulse VSP indicates the point of time when the gate driver 200 is operated. The reset pulse RST indicates the reset timing of the gate driver 200. The even drive voltage GVDD_E and the odd drive voltage GVDD_O are alternately used as the drive voltage of the gate driver 200 in the even frame and the odd frame. The line selection pulse LSP is used by the gate driver 200 to select any one horizontal line to be sensed in the vertical blanking period of each frame. The clock shift stop pulse CSP is used to stop the clock shift in the gate driver 200 during the sensing operation period of each vertical blank period.

The timing controller 400 generates a plurality of control data for controlling the output level of each of the plurality of gate control signals output from the level shifter 600 on a predetermined time basis using the internal timing setting information. The timing controller 400 generates a control bit stream (CBS) by serializing a plurality of control data each of which determines an output level of each of a plurality of gate control signals at a constant time at which the output level of each gate control signal changes, (600).

5, the timing controller 400 generates a control bit stream (CBS) serialized in each horizontal period (1H) and transmits the generated control bit stream (CBS) to the level shifter 600 according to a clock (CLK) frequency, One control bit per frame. The control bit stream CBS transmitted in 1H units is either a 1-bit control bit [B0] or a 2-bit control bit [B0: B1] which determines the output level of each of the plurality of gate control signals in the 1H period And a plurality of control bits configured.

For example, the output level of the gate control signal including the GPM (Gate Pulse Modulation) section via the middle voltage (VDD) step at the rising edge and the polling edge, such as the scan clocks SCCLKs, [B0: B1] is assigned to define the output level of each of the scan clocks (SCCLKs) in 1H. The control bit [B0: B1] of 2 bits is set to the high level [00], the low level [01], the GPM section [11], and the dead time [10] (all off) of the corresponding scan clock SCCLK Can be defined.

The scan line driver circuit 70 receives the gate control signals other than the scan clocks SCCLKs, i.e., the sense clocks SECLKs, the carry clocks CRCLKs, the start pulse VST, the reset pulse RST, the line select pulse LSP, The output level of the stop pulse CSP, the even drive voltage GVDD_E and the od drive voltage GVDD_O is set to a high level [1], a high level [1] Low level [0] can be defined.

The timing controller 400 transmits the clock CLK through the first wire and the serialized control bit stream CBS through the second wire. The timing controller 400 supplies the latch enable signal LE for instructing the latch and the output timing of the control bit stream CBS in the level shifter 600 every unit time (1H) And further supplies it to the shifter unit 600.

The level shifter 600 sequentially samples and latches the control bit stream CBS transmitted in units of a predetermined time (1H) from the timing controller 400 according to the clock CLK, and controls the latch enable signal LE And outputs a plurality of gate control signals each having an output voltage level determined using a plurality of control bits.

The level shifter 600 counts the number of clocks CLK supplied in each horizontal period 1H from the timing controller 400 and recognizes the abnormal state as being smaller than the set value to hold the latch operation At this time, the output of the level shifter 600 maintains the previous output.

3 and 4, the level shifter 600 generates a plurality of gate control signals whose output voltage levels are determined according to the control of the decoder 610 and the decoder 610, and supplies them to the gate driver 200 individually And a plurality of level shifters 60-1 to 60-N for outputting the level shifters 60-1 to 60-N.

The decoder 610 sequentially samples and latches the control bit stream CBS transmitted in units of a predetermined time (1H) from the timing controller 400 according to the clock CLK, as shown in FIG. Subsequently, the decoder 610 generates a plurality of output control signals by using the plurality of control bits under the control of the latch enable signal LE, and outputs a plurality of level shifters 60-1 to 60-N during the next 1H, Respectively.

Each of the plurality of level shifters 60-1 to 60-N switches any one output voltage according to the corresponding output control signal supplied from the decoder 610 and supplies the output voltage to the output terminal so that the output voltage level And outputs the determined gate control signal. The plurality of level shifters 60-1 to 60-N output the scan clocks SCCLK1 to SLCLKm, the sense clocks SECLK1 to SECLKm, and the carry clocks CRCLK1 to CRCLKm ), The start pulse VST, the reset pulse RST, the line selection pulse LSP, the clock shift stop pulse CSP, the even drive voltage GVDD_E and the odd drive voltage GVDD_O, And outputs it to the driver 200.

4, each of the level shifters 60-1 to 60-N supplies the gate-on voltage VGH to the output terminal in response to the control of the output control signal CSk according to the control bit [B0] A first output switch SW1 and a second output switch SW2 for outputting the gate-off voltage VGL to the output terminal.

Particularly, the level shifter 60-1 for outputting the scan clock SCCLK including the GPM includes, in addition to the first and second output switches SW1 and SW2, a third output for outputting the intermediate voltage VDD to the output terminal And further includes a switch SW3. The first to third output switches SW1 to SW of the level shifter 60-1 for outputting the scan clock SCCLK are controlled according to the control of the output control signal CS1 according to the control bit [B0: B1] And is selectively turned on or off.

The first to third switching transistors SW1, SW2, and SW3 may be any one of an NMOS transistor and a PMOS transistor. For example, the first switching transistor SW1 may be a PMOS transistor, and the second and third switching transistors SW2 and SW3 may be an NMOS transistor.

3, the gate driver 200 incorporated in the panel 100 includes a plurality of scan stages SC_ST1 to SC_STn for individually supplying scan pulses SC1 to SCn to a plurality of scan gate lines, And a plurality of sense stages SE_ST1 to SE_STn for individually supplying sense pulses SE1 to SEn to a plurality of sense gate lines.

The gate driver 200 receives a plurality of gate control signals as described above from the level shifter 600. The gate driver 200 receives the gate control signals from the level shifter 600, The scan clocks SCCLK1 to SCCLKm are supplied with m-phase sense clocks SECLK1 to SECLKm having different phases from each other and partially overlapping the adjacent sense clocks and the high level interval.

The plurality of scan stages SC_ST1 to SC_STn starts the shift operation in response to the start pulse VST supplied from the level shifter 600 and sequentially selects the scan clocks SCCLK1 to SCCLKm alternately, And outputs the scan pulses SC1 to SCn to the gate lines.

The plurality of sense stages SC_ST1 to SC_STn start the shift operation in response to the start pulse VSP and alternately select the sense clocks SECLK1 to SECLKm sequentially to output the sense pulses SE1 to SEn .

On the other hand, in each frame, the driving voltage Vgs corresponding to the data signal is written in each subpixel in response to the scan pulse SCn and the sense pulse SEn, and data in which each subpixel emits light in accordance with the driving voltage Vgs And a vertical blank period for updating the compensation value of the corresponding subpixel by sensing the electrical characteristics of the subpixels included in one horizontal line.

In each vertical blanking period, any one of the scan stages SC_STn and one sense stage SE_STn selects the corresponding scan clock SCCLK1 and the sense pulse SECLK1, A scan pulse SCn and a sense pulse SEn are supplied to the gate lines, respectively.

6, each of the scan pulse SCn and the sense pulse SEn supplied in each vertical blanking period is supplied to a first pulse having a first pulse width included in the corresponding scan clock SCCLK1 and the sense pulse SECLK1, (P1) having a second pulse width smaller than the first pulse width, and second and third pulses (P2, P2) having a second pulse width smaller than the first pulse width.

Referring to FIGS. 2 and 6, a period during which the first pulse P1 of the scan pulse SCn and the sense pulse SEn is supplied during each vertical blank period indicates a sensing operation period for the corresponding subpixels. During this sensing operation period, the data driver 300 supplies the sensing data voltage Vdata and the reference voltage Vref to each of the subpixels SP of the corresponding horizontal line to drive each driving TFT DT. The pixel current reflecting the electrical characteristics (Vth, mobility) of each driving TFT DT is charged with the voltage to the line capacitor of the floating reference line Rm while the driving TFT DT is driven, (300) samples the voltage charged in the reference line (Rm), converts it into sensing data of each subpixel (SP), and outputs it to the timing controller (400). Accordingly, the timing controller 400 updates the mobility compensation value of the corresponding sub-pixel SP stored in the memory 500 using the sensing result of the corresponding sub-pixel SP.

While the second and third pulses P1 and P2 of the scan pulse SCn and the sense pulse SEn are supplied, the data driver 300 supplies the recovery data voltage and the reference voltage to the corresponding subpixels And restores the state of the sensing subpixels SP to a display operation state similar to other unselected subpixels.

7 is a waveform diagram illustrating a method of generating a scan clock including a GPM in a level shifter according to an exemplary embodiment of the present invention.

In the previously described FIG. 5, two control bits [B0: B1] are allocated to determine the output level of the scan clock including the GPM every 1H units, but one control bit [B0] may be allocated as shown in FIG. .

The decoder of the level shifter 600 applies a command indicated by each control bit [B0] supplied in units of 1H differently according to the voltage level outputted from the current level shifter 60-1, and supplies the level shifter 60-1 By controlling the first to third output switches SW1, SW2, and SW3 of the scan clock SCLK including the GPM in the rising edge and the falling edge as shown in FIG.

7, the high level [1] of the control bit [B0] indicates the output including the GPM in the next horizontal period, and the low level [0] indicates the output level of the current horizontal period in the next horizontal period You can tell. The scan clock (SCCLK) may include a rising GPM with the GPM output on the rising edge and a polling GPM with the GPM output on the falling edge. The scan clock (SCCLK) including the rising GPM and the polling GPM may have a pulse width of 3H period or 2H period.

When the control bit [B0] input in the current horizontal period which outputs the gate off voltage VGL indicates the GPM output, the level shifter 60-1 outputs the second output switch SW2 in the next horizontal period, And outputs the rising GPM by turning on the third output switch SW3 for a predetermined period of time and then turns off the third output switch SW3 during the remaining time of the horizontal period and turns off the first output switch On voltage VGH by turning on the switch SW1.

On the other hand, when the control bit [B0] input in the current horizontal period that outputs the gate-on voltage VGL indicates the GPM output, the level shifter 60-1 outputs the output of the first output switch SW1 And maintains the turn-on state to continuously output the gate-on voltage VGH, and then outputs the polling GPM by turning off the first output switch SW1 and turning on the third output switch SW3 at a preset remaining time .

When the control bit [B0] input in the current horizontal period of outputting the gate off voltage VGL indicates holding, the level shifter 60-1 turns on the second output switch SW2 in the next horizontal period, And maintains the output of the gate-off voltage VGL.

When the control bit [B0] input in the current horizontal period which is outputting the gate-on voltage VGH indicates holding, the level shifter 60-1 turns on the first output switch SW1 in the next horizontal period, To maintain the output of the gate-on voltage VGH.

When the control bit [B0] input in the current horizontal period for outputting the polling GPM indicates holding, the level shifter 60-1 maintains the turn-on of the second output switch SW2 in the next horizontal period, Off voltage VGL.

The rising GPM timing and polling GPM timing can be set to the option (capacitor or resistor) of the level shifter 60-1.

8 is a block diagram schematically showing an LCD configuration according to an embodiment of the present invention, FIG. 9 is a diagram illustrating signal lines between the timing controller and the level shifter unit and the gate driver shown in FIG. 8, and FIG. 8 is a waveform diagram illustrating input signals of the level shifter shown in FIG.

8, the LCD includes a panel 1100, a gate driver 1200, a data driver 1300, a timing controller 1400, a power supply unit 1500, a level shifter unit 1600, a gamma voltage generator 1100 ) And the like.

The power supply unit 1500 generates and outputs various driving voltages required for driving all the circuits of the LCD using the input voltage supplied from the outside.

Each of the subpixels SP constituting the pixel array PA of the panel 1100 includes a TFT connected to the gate line GL and the data line DL, a TFT connected to the common electrode Vcom, (Clc) and a storage capacitor (Cst). The liquid crystal capacitor Clc charges the difference voltage between the data signal supplied to the pixel electrode through the TFT and the common voltage Vcom supplied to the common electrode Vcom and drives the liquid crystal in accordance with the charged voltage to obtain the light transmission amount . The storage capacitor Cst stably maintains the voltage charged in the liquid crystal capacitor Clc during the turn-off period of the thin film transistor TFT.

The gate driver 200 incorporated in the panel 1100 individually drives the gate lines GL using a plurality of gate control signals supplied from the level shifter 1600. [

The data driver 1300 supplies the image data supplied from the timing controller 1400 to the positive polarity or negative polarity image data using the gamma voltages supplied from the gamma voltage generator 1700 according to the data control signal supplied from the timing controller 1400. [ Polarity analog data signals and supplies them to the data lines DL of the panel 1100.

The timing controller 1400 generates a plurality of data control signals, supplies the data control signals to the data driver 1300, performs various image processes on the image data, and supplies the image data to the data driver 1300.

In particular, the timing controller 1400 generates a plurality of control data for determining an output level of each of the plurality of gate control signals output from the level shifter unit 1600 using the internal timing setting information. As shown in FIG. 10, the timing controller 1400 generates a control bit stream (CBS) by serializing a plurality of control bits, each of which determines an output level of a plurality of gate control signals in units of a predetermined time (1H).

The output level of each of the scan clocks CLKs including the GPM is defined in units of 1H by allocating a 2-bit control bit [B0: B1], and the start pulse VST, the reset pulse RST, GVDD_E, and the odd driving voltage GVDD_O are assigned in units of 1H by assigning 1-bit control bits [B0]. On the other hand, as described with reference to FIG. 7, the output level of each scan clock CLKs including the GPM can be defined in units of 1H by assigning a 1-bit control bit [B0].

9, the timing controller 1400 outputs a clock CLK, a serialized control bit stream CBS, and a latch enable signal LE to the level shifter 600 through the first to third wires, respectively Supply.

The level shifter 1600 sequentially samples and latches the control bit stream CBS transmitted in units of a predetermined time (1H) from the timing controller 400 according to the clock CLK as shown in FIG. 10, And outputs a plurality of gate control signals each having an output voltage level determined using a plurality of control bits in accordance with an enable signal LE. The level shifter unit 1600 receives the scan clocks CLK1 to CLKm, the start pulse VST, the reset pulse RST, the even drive voltage GVDD_E, and the odd drive voltage GVDD_O), and the like, and outputs them to the gate driver 1200.

The gate driver 1200 incorporated in the panel 1100 receives the plurality of gate control signals from the level shifter 1600 and starts the shift operation in response to the start pulse VST and outputs the scan clocks CLK1 To CLKm sequentially in sequence to sequentially output scan pulses to the gate lines GL1 to GLn.

As described above, the timing controller and the level shifter unit according to the embodiment of the present invention transmit various gate control data using the serial interface, so that the number of output signals of the level shifter unit and the level shifter unit The number of wires can be minimized to three.

Accordingly, even if the number of output signals of the level shifter unit increases, the number of wirings between the timing controller and the level shifter unit is minimized to three, thereby reducing the number of output pins of the timing controller, the number of input pins of the level shifter unit, The number of routing wires and the routing area between the timing controller and the level shifter portion can be minimized, thereby reducing cost and EMI.

The level shifter unit and the display device according to an exemplary embodiment may be applied to all display devices such as an OLED display device, an LCD, and the like.

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. It is intended that the scope of the invention be interpreted by the claims appended hereto, and that all techniques within the scope of equivalents thereof should be construed as being included within the scope of the present invention.

100, 1100: panel 200, 1200: gate driver
300, 1300: Data driver 400, 1400: Timing controller
500, 1500: power supply unit, power supply unit 600, 1600: level shifter unit
700, 1700: gamma voltage generator 800: memory
610: Decoders 60-1 to 60-N: Level shifter

Claims (10)

A gate driver for driving gate lines of the panel;
A level shifter for outputting a plurality of gate control signals for controlling driving of the gate driver;
A timing controller for serializing a plurality of control data for determining an output level of each of the plurality of gate control signals in a specific time unit and transmitting the serialized control data to the level shifter unit in synchronization with the clock for each specific time unit Including,
The level shifter unit
A plurality of level shifters for individually outputting the plurality of gate control signals,
And a decoder for receiving and latching the plurality of serialized control data from the timing controller and controlling an output level of each of the plurality of level shifters for each specific time unit using a plurality of latched control data. The method according to claim 1,
The timing controller
Further generates a latch enable signal for controlling the timing of outputting the plurality of control data items latched in the specific time unit,
The clock is transferred to the level shifter through the first wiring,
And transmits the serialized plurality of control data to the level shifter through a second wire,
And transmits the latch enable signal to the level shifter unit via the third wiring. The method of claim 2,
Wherein the timing controller generates a control bit stream by serializing a plurality of control bits indicating an output level of each of the plurality of gate control signals in one or two bits in each horizontal period, The stream is transmitted according to the clock,
Wherein the level shifter samples and latches the control bit stream transmitted in each horizontal period according to the clock and outputs the plurality of gate control signals in the next horizontal period using the plurality of control bits in accordance with the latch enable signal, And determines the respective output levels. The method of claim 3,
Wherein the gate driver is embedded in a panel including a pixel array,
Wherein each sub-pixel constituting the pixel array includes a light-emitting element and a pixel circuit that independently drives the light-emitting element,
The gate driver supplies a scan pulse to a scan gate line connected to each subpixel, supplies a sense pulse to a sense gate line connected to each subpixel,
The plurality of level shifters included in the level shifter section
A plurality of scan clocks, a plurality of carry clocks, a start pulse, a reset pulse, an even frame drive voltage, an odd frame drive voltage, and control signals required for the sensing operation of each subpixel in the gate driver And supplies the plurality of gate control signals to the gate driver. The method of claim 3,
Wherein the gate driver is embedded in a panel including a pixel array,
Each subpixel constituting the pixel array includes a thin film transistor which independently drives a liquid crystal capacitor,
Wherein the gate driver supplies a scan pulse to a gate line connected to each sub-pixel,
The plurality of level shifters included in the level shifter section
Wherein the plurality of gate control signals including a plurality of scan clocks, a start pulse, a reset pulse, an even frame drive voltage, and an odd frame drive voltage are separately generated and supplied to the gate driver. The method according to claim 4 or 5,
The decoder of the level shifter unit
An output of a first gate control signal output from a first level shifter of the plurality of level shifters in a next horizontal period using a first control bit to which one bit is allocated in each horizontal period among the plurality of control bits; On voltage or a gate-off voltage,
And a second gate control unit which outputs a second gate control signal from the second level shifter of the plurality of level shifters in a next horizontal period, using a second control bit allocated to one or two bits in each horizontal period among the plurality of control bits, Wherein the output of the signal is determined as the gate-on voltage, the gate-off voltage, or the gate pulse modulation (GPM) output. The method of claim 6,
The first bit is assigned to the second control bit to indicate holding of the GPM output or previous horizontal period output,
When the second control bit supplied by the decoder in the first horizontal period in which the second level shifter outputs the gate off voltage indicates the GPM output, the second level shifter is in the second horizontal period for some time Outputs the gate-on voltage at the remaining time of the second horizontal period after outputting the rising GPM,
When the second control bit supplied by the decoder in the third horizontal period in which the second level shifter outputs the gate-on voltage indicates the GPM output, the second level shifter shifts the gate- Maintains the output of the voltage and outputs the polling GPM at the remaining time of the fourth horizontal period. The method of claim 6,
When the second level shifter indicates holding of the second control bit supplied from the decoder in a fifth horizontal period in which the gate-off voltage or the gate-on voltage is output, the second level shifter is in the sixth horizontal period And maintains the output of the fifth horizontal period. The method of claim 7,
When the second level shifter indicates holding of the second control bit supplied from the decoder in the seventh horizontal period in which the polling GPM is being output, the second level shifter shifts the gate- A display device for maintaining output. The method of claim 3,
The level shifter unit
Counts the number of clocks supplied for each horizontal period, recognizes an abnormal state when the counted number is smaller than the set value, holds the latch operation, and maintains the output of the previous horizontal period.

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