KR20180093545A - The fully-integrated asynchronous digital low drop-out regulator - Google Patents

Abstract

As an embodiment of the present invention, an integrated digital low drop-out regulator is provided. According to an embodiment of the present invention, the integrated digital low drop-out regulator comprises: a detection unit for detecting whether a coarse voltage is regulated and a fine voltage are regulated on the basis of a reference voltage and an output voltage for the regulator; a control unit including a self-oscillating bidirectional shift register unit connected to the detection unit and operable to have a minimized transient response time (T_TRAN) according to a load connected to the regulator; and a plurality of coarse switches and fine switches connected to the control unit, wherein the control unit is free of a clock input from the outside, and an external load capacitor is eliminated from the regulator.

Description

INTEGRATED ASYNCHRONOUS DIGITAL LOW DROP-OUT REGULATOR < RTI ID = 0.0 >

The present invention relates to an integrated digital low dropout regulator, and more particularly to an integrated digital low dropout regulator that includes a control unit including a coarse and fine detection unit, a self oscillating bidirectional shift register unit, and a plurality of coarse switches and a plurality And more particularly to an integrated digital low dropout regulator including a number of fine switches.

A regulator having a digital low dropout structure may include a digital controller, a shift register, a comparator, and the like. In other words, the regulator of the conventional D-LDO structure can consist of (i) a synchronous bidirectional shift register (S / R) based on a digital controller and a PMOS switch array and (ii) have. For example, Korean Patent No. 10-1551643 (2015.09.01) and the like may be used.

The comparator is used to detect the difference between output voltage V _OUT and the reference voltage V _REF, S / R synchronization controller adjusts the PMOS switch arrays by reducing the error difference between the reference voltage V _REF and the output voltage V _OUT to generate a V _OUT (tune up).

While this conventional design can achieve high DC-accuracy, there is a problem that the transient response time (T _TRAN ) is very slow. Since a single p-type power MOSFET is divided into a plurality of small power switches, S / R allows only one switch to change states in one clock cycle, even though the comparator has almost infinite bandwidth. I can do it. In other words, a bottleneck may occur during the transient response in the operation of the shift register.

Under these conventional architectures, it is one of the most feasible and feasible to directly increase the clock frequency in order to achieve fast modulation. Nonetheless, the high clock frequency has the disadvantage of large power loss and overall efficiency degradation. In addition, complex on-chip compensation, such as the externally applied clock frequency, may be required to change the clock input in SoC environments.

Korean Patent No. 10-1551643, (2015.09.01)

The above-described limitations of the external clock input, T _tran degradation and T _tran and Considering the trade-off problem between the current efficiency of the existing structure, a fully integrated (fully-integrated), fast transient (fast-transient as one embodiment of the invention the ), And a capacitor-free D-LDO.

As an embodiment of the present invention, an integrated digital low dropout regulator may be provided.

An integrated digital low dropout regulator according to an embodiment of the present invention includes a detector for detecting coarse and fine based on a reference voltage and an output voltage for a regulator, And a self-oscillating bidirectional shift register section that can be operated to have a minimized transient response time (T _TRAN ) according to the load connected to the control terminal, and a plurality of coalesce switches and a plurality of fine switches connected to the control section, And the external load capacitor may be removed from the regulator.

Further, the detecting section includes a lock range detecting section and a lock synchronizing section for detecting a lock range, and the lock synchronizing section is capable of switching from coarse to fine or from fine to coarse according to a load connectable to the regulator .

In addition, the regulator further includes a comparator (Logic-Threshold-Triggered-Comparator, LTTC), and the self-oscillating bidirectional shift registers of the control section can be activated or deactivated according to the output value of the LTTC.

The first register unit is a coarse 64-bit shift register unit, the second register unit is a fine 32-bit shift register, and the first register unit is a coarse 64-bit shift register unit. And each register section may have logic for generating and providing a continuous clock with a shift register.

A plurality of coarse switches and a plurality of fine switches according to an embodiment of the present invention may be PMOS switches.

A self-oscillating bidirectional shift register in accordance with an embodiment of the present invention does not require any external clock input from other frequency synthesizers, and does not require any external clock input of additional electrical circuitry having a clock- The circuitry may be removed from the mobile application processor. In other words, according to one embodiment of the present invention, a self-oscillating bi-directional shift register-based controller is a D-FF that can eliminate the need for an external clock input and compensation cost, Can be embedded in an LDO structure.

In addition, coarse-fine loop detection techniques can immediately activate or deactivate the required loop behavior depending on the load transient state, regardless of whether a fast _Ttran or high current efficiency is required.

In addition, coarse-fine loop detection can be designed with synching-control to improve load regulation performance and reduce voltage peaks during load transients.

According to one embodiment of the present invention, fine loop control using a fine-grained switch array can significantly reduce the inherent ripple of the D-LDO, eliminates the need for an external load capacitor, and allows the circuit structure to be fully integrated .

The dynamic detection of a coarse-fine loop operation according to an embodiment of the present invention can help achieve high current efficiency and effective load regulation through a high speed T _tran .

In addition, a coarse-loop controlled subdivided switch array can derive a large and infrequent load current of the mobile application processor.

1 shows a block diagram of a conventional regulator of a D-LDO structure.
2 is an exemplary block diagram of an integrated digital low dropout regulator in accordance with one embodiment of the present invention.
3A is an exemplary block diagram of a fine-32 bit self oscillating bidirectional shift register in accordance with an embodiment of the present invention.
FIG. 3B shows an operation waveform diagram of a fine-32-bit self oscillating bi-directional shift register according to an embodiment of the present invention.
4 shows a simulation result of an acquisition response of a D-LDO using coarse-fine loop switching according to an embodiment of the present invention.
5 shows a simulation result of the full response of a D-LDO using coarse-fine loop switching according to an embodiment of the present invention.
6 shows a simulation result of a load transient response of a D-LDO having a minimum transient response time of 23.45 ns according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

The terms used in this specification will be briefly described and the present invention will be described in detail.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. Also, in certain cases, there may be a term selected arbitrarily by the applicant, in which case the meaning thereof will be described in detail in the description of the corresponding invention. Therefore, the term used in the present invention should be defined based on the meaning of the term, not on the name of a simple term, but on the entire contents of the present invention.

When an element is referred to as "including" an element throughout the specification, it is to be understood that the element may include other elements as well, without departing from the spirit or scope of the present invention. Also, the terms "part," " module, "and the like described in the specification mean units for processing at least one function or operation, which may be implemented in hardware or software or a combination of hardware and software . In addition, when a part is referred to as being "connected" to another part throughout the specification, it includes not only "directly connected" but also "connected with other part in between".

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Figure 2 is an exemplary block diagram of an integrated digital low dropout regulator in accordance with one embodiment of the present invention and Figure 3a is an exemplary block diagram of a fine 32 bit self oscillating bidirectional shift register in accordance with an embodiment of the present invention. And FIG. 3B is an operation waveform diagram of a fine-32-bit self-oscillating bidirectional shift register according to an embodiment of the present invention. 4 is a simulation result of an acquisition response of a D-LDO using coarse-fine loop switching according to an embodiment of the present invention. FIG. 5 is a graph showing a result of simulation of a D-LDO using Doppler shift switching according to an embodiment of the present invention. Simulation results of the full response of the LDO and Figure 6 shows the simulation results of the load transient response of the D-LDO with a minimum transient response time of 23.45 ns according to an embodiment of the present invention.

An integrated digital low dropout regulator 1000 according to an embodiment of the present invention includes a detector for detecting coarse and fine based on a reference voltage and an output voltage for the regulator 1000 And a self-oscillating bidirectional shift register unit connected to the detecting unit 100 and having a minimized transient response time (T _TRAN ) according to a load connected to the regulator, and a control unit 200 The control unit 200 includes a plurality of coalescing switches 300 and a plurality of fine switches 400 connected to the control unit 200. The control unit 200 may be configured such that a clock input from the outside is removed and an external load capacitor is removed from the regulator 1000 have.

The detecting section 100 includes a lock range detecting section 110 and a lock synchronizing section 120 for detecting a lock range and the lock synchronizing section 120 is connected to a load connectable to the regulator 1000 Thus making it possible to transition from coarse to fine or from fine to coarse.

In addition, the regulator 1000 further includes a comparator (Logic-Threshold-Triggered-Comparator) 500. The self-oscillating bidirectional shift registers of the controller 200 are activated or deactivated according to the output value of the LTTC 500 .

Referring to FIG. 2, a regulator 1000 (e.g., a D-LDO) includes a logic-threshold-triggered-comparator (LTTC), a coarse / fine detector, A bidirectional shift register may be included. The self oscillating bidirectional shift register has 64-bit coarse-to-coarse (64-bit) separate loops with switches and fine with 32-bit fine- 32-bit) individual loops.

After all of the shift registers have been reset to turn off the power switches, the shift registers are shifted to turn on the power switches when the LTTC output is low (e.g., V _OUT < V _REF ) (DN) (shift right). Coarse / fine detection can simultaneously accomplish the same task using a pair of LTTCs 500 and activate the coarse 64-bit shift registers to quickly reach the target V _OUT . When the V _OUT level reaches the lock detector range, the lock signal produces a high transition and a fine 32 (zero) transition occurs while the coarse 64-bit shift registers are deactivated - Bit shift registers can be activated. The lock-synching part ensures smooth transitions from coarse to fine, from fine to coarse, and can improve load balancing.

Conversely, when the LTTC output is high (V _OUT > V _REF ) (UP), the shift register can be shifted left in the same way to reduce the number of switches on. In response to an arbitrary load transient, the coarse 64-bit shift registers are activated when the output voltage (V _OUT ) is bear under / overshoot (bear), and with 16 times larger power switches The V _OUT level is achieved with a high speed T _tran , and the loop can be hand-over to fine 32-bit shift registers to reduce steady state ripples and achieve much better current efficiency.

The control unit 200 includes a first register unit 210 and a second register unit 220 in the self oscillating bidirectional shift register unit and the first register unit 210 is a coarse 64-bit shift register unit And the second register unit 220 is a fine 32-bit shift register unit. Each register unit 210 and 220 has a built-in logic for generating and providing a continuous clock as a shift register Can be.

The plurality of coalescing switches 300 and the plurality of fine switches 400 may be PMOS switches according to an embodiment of the present invention.

FIGS. 3A and 3B show a block diagram of a fine 32-bit self-oscillating bidirectional shift register unit and its operation waveform according to an embodiment of the present invention. The coarse 64-bit is the same except for the number of bits.

Referring to Figure 3a, 32-Bit Shift system 1 (e.g., 1 ^st) of the register and the last 31 (for example, 31 ^st) block of the stage (stage) of the are embedded so as to synchronize with the asynchronous clock stage And can be expressed as a modified logic. In other words, the first and last stages of the shift register 32 bits may be pre-configured with logic for continuing the shift process to create a continuous shifting process. As shown in FIG. 3B, the logic stage 32-bit starts logic generation at the falling edge of RESET, the edge detector senses the dual edge of LOGIC_OUT, the shift register stage for right / Lt; RTI ID = 0.0 &gt; clocks &lt; / RTI &gt;

The simulation results according to an embodiment of the present invention are as follows.

The D-LDO according to an embodiment of the present invention can be operated to exhibit the following operation performance. For example, the D-LDO may have a V _DD = 1.2V and V _REF = V _TARGET = 1.16V, the D-LDO can be operated as shown in FIG. 4 to obtain the minimum drop-out characteristics that in turn improve the power-efficiency of the D-LDO.

Figure 4 shows the acquisition response of the D-LDO after the RESET signal is applied. The self-oscillating bidirectional shift registers start oscillating to perform a shifting process. During acquisition-time, the lock signal is still low and the loop is controlled by a 64-bit coarse-loop. During the steady-state of the D-LDO, the 32-bit fine-loop is activated after the V _TARGET = 1.16V acquisition.

A self-generated clock of two loops with lock and V _TARGET signals (e.g., a 64-bit coarse-loop and a 32-bit fine-loop) have. A complete response of a D-LDO with load-current variations may appear as shown in FIG.

When the negative terminal is connected, the lock signal is lowered and accordingly the coarse-loop is activated to achieve a fast T _TRAN , and when the V _TARGET level is reached, the loop is panned with a high state of the lock signal, It is switched back to the loop control operation. The dynamic and soft-switching of the two loops can help to achieve a fast T _TRAN with reduced steady-state ripples and maximum current efficiency at the same time.

T _TRAN A load current step of 37 mA with time can be shown in FIG.

The D-LDO according to one embodiment of the present invention has a minimum T _TRAN of 23.45 nanoseconds (ns) at a load current stage of about 33 mA Can be achieved. In addition, the D-LDO according to an embodiment of the present invention can achieve an effective load-regulation of 0.007 mV / mA.

The D-LDO according to an embodiment of the present invention can be utilized as a power management unit (PMU) of a mobile application processor (AP). These D-LDOs do not require any external load capacitors and can be suitable for use as an on-chip regulator through fast T- _tran , efficient load regulation, and high current drive characteristics.

In addition, the small active area of the D-LDO may be suitable for the operating environment where the PMU of the mobile application processor requires multiple on-chip regulators.

In addition, there is no need for an additional clock distribution network for the on-chip regulators inside the PMU because no external clock input is required.

With respect to the method of operation according to an embodiment of the present invention, the contents of the above-mentioned device (for example, an integrated digital low dropout regulator) can be applied. Therefore, the description of the same contents as those of the above-mentioned apparatus has been omitted in connection with the method.

One embodiment of the present invention may also be embodied in the form of a recording medium including instructions executable by a computer, such as program modules, being executed by a computer. Computer readable media can be any available media that can be accessed by a computer and includes both volatile and nonvolatile media, removable and non-removable media. In addition, the computer readable medium may include both computer storage media. Computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data.

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100:
110: Lock range detecting section
120: Lock synchronization section
200:
210:
220:
300: Coarse switch
400: Fine switch
500: Comparator (LTTC)
1000: Integrated Digital Low Dropout Regulator

Claims (5)

As an integrated digital low dropout regulator,
A detector for detecting coarse and fine based on a reference voltage and an output voltage for the regulator;
And a self-oscillating bidirectional shift register portion connected to the detecting portion and operable to have a minimized transient response time (T _TRAN ) according to a load connected to the regulator; And
A plurality of coarse switches and a plurality of fine switches connected to the control unit,
Wherein the control unit is in a state where a clock input from the outside is removed,
And an external load capacitor is removed from the regulator.
The method according to claim 1,
The detection unit includes a lock range detection unit for detecting a lock range; And a lock synchronization unit, wherein the lock synchronization unit enables transition from coarse to fine or fine to coarse according to a load connectable to the regulator, regulator.
The method according to claim 1,
The regulator further includes a comparator (Logic-Threshold-Triggered-Comparator, LTTC)
Wherein the self-oscillating bidirectional shift registers of the control unit are activated or deactivated according to the output value of the LTTC.
The method according to claim 1,
Wherein the self-oscillation bidirectional shift register unit of the control unit includes a first register unit and a second register unit,
The first register unit is a coarse 64-bit shift register unit,
The second register portion is a fine 32-bit shift register portion,
Wherein each register portion includes logic for generating and providing a continuous clock with a shift register. &Lt; Desc / Clms Page number 19 &gt;
The method according to claim 1,
Wherein the plurality of coarse switches and the plurality of fine switches are PMOS switches. &Lt; Desc / Clms Page number 13 &gt;

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