KR20180062585A - Real Time Compensation Circuit And Electroluminescent Display Device Including The Same - Google Patents

Abstract

The present invention relates to a real-time compensation circuit and an electroluminescent display device including the same. The real-time compensation circuit includes: a first memory for storing a plurality of compensation values set by a pixel block unit including M x N (M and N are positive integers of 2 or more, respectively) pixels; a second memory for receiving the plurality of compensation values by a pixel block from the first memory; a compensation unit for modulating the pixel data by adding the compensation value by a pixel block to the pixel data of an input image; and a data driving unit for converting the compensated pixel data, received from the compensation unit, into a data voltage. The compensation value by a pixel block is collectively applied to each pixel in the pixel block in at least one color. Accordingly, the present invention can reduce the memory capacity of the compensation circuit and a tact time.

Description

[0001] The present invention relates to a real-time compensation circuit and an electroluminescent display device including the same,

The present invention relates to a real-time compensation circuit and an electroluminescent display including the same.

An electroluminescent display device is classified into an inorganic light emitting display device and an organic light emitting display device depending on the material of the light emitting layer. An active matrix type organic light emitting display device includes an organic light emitting diode (OLED) which emits light by itself, and has a high response speed, a high luminous efficiency, a high brightness and a wide viewing angle There are advantages.

An OLED of an organic light emitting display includes an anode electrode and a cathode electrode, and an organic compound layer formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a power source voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons. As a result, the light emitting layer (EML) Thereby generating visible light.

Each of the pixels of the organic light emitting display includes a driving element for controlling a current flowing in the OLED. The driving element may be implemented as a transistor. Though the electrical characteristics of the driving device such as threshold voltage and mobility should be the same in all the pixels, the electrical characteristics of the driving device are not uniform due to process conditions, driving environment, and the like. The longer the driving time of the driving device, the more stress is applied to the driving device. In addition, the stress of the driving element varies depending on the data of the input image. The electrical characteristics of the driving device are affected by the stress. Therefore, the driving characteristics of the driving elements are different when the driving time elapses.

In order to improve the image quality and lifetime of the organic light emitting diode display, a compensation circuit for compensating a driving characteristic difference between pixels is applied to the OLED display.

In the high resolution and fast driving trend of organic light emitting display devices, the difference in driving characteristics of pixels can not be sufficiently compensated by the conventional compensation method. For example, the higher the resolution and the higher the driving frequency, the smaller the one horizontal period for writing data to one line of pixels in the display panel, so that the threshold voltage sampling period of the driving elements assigned within one horizontal period can be reduced There is nothing. If the time required for sampling the threshold voltage of the driving element is insufficient, the threshold voltage sampling value of the driving voltage becomes inaccurate, resulting in a driving characteristic difference between the pixels on the screen. The driving characteristic difference between the pixels causes a luminance difference even if data of the same gradation level is written in all the pixels, thereby appearing as a smear on the screen.

The present invention provides a real-time compensation circuit and an electroluminescent display device including the real-time compensation circuit that can sufficiently compensate a difference in driving characteristics between pixels in a high-resolution high-speed driving and reduce a memory capacity of a compensation circuit.

The real-time compensation circuit of the present invention includes: a first memory storing a plurality of compensation values for each pixel block set in units of pixel blocks including M x N (M and N are each a positive integer of 2 or more) pixels; A second memory for receiving the plurality of compensation values for each pixel block from the first memory; A compensation unit for adding the compensation value for each pixel block to the pixel data of the input image to modulate the pixel data; And a data driver for converting the compensated pixel data received from the compensator into a data voltage. The compensation value for each pixel block is collectively applied to each pixel in the pixel block in at least one color. The pixel data and the compensation value for each pixel block are added between data of the same color.

The compensation value for each pixel block compensates for the blur obtained through image shooting of the display panel.

Wherein the pixel block includes at least one first penta-pixel including sub-pixels of a first color and sub-pixels of a second color; And at least one second penta pixel including a subpixel of a third color and a subpixel of the second color.

Wherein the pixel block comprises at least one first real color pixel comprising a subpixel of a first color, a subpixel of a second color, and a subpixel of a third color; And at least one second real color pixel including a subpixel of the first color, a subpixel of the second color, and a subpixel of the fourth color.

The compensation unit is also applied to a display panel including the penta-pixels and a display panel including the real color pixels according to a register setting value.

The real-time compensation circuit further includes a real / penta converter. Wherein the real / penta converter converts first real pixel data including first-color data, second-color data, and third-color data into first real pixel data including first-color data and first- And second real pixel data including the data of the first color, the data of the second color, and the data of the third color is converted into the data of the third color and the data of the second color Into the second penta-pixel data including the second penta pixel data.

The compensation unit adds the compensation value for each pixel block to the pixel data of the input image received from the real / Penta conversion unit.

The compensation value for each pixel block includes a first compensation value to be applied to the first color subpixels collectively, a second compensation value to be collectively applied to the second color subpixels, Lt; / RTI > and the third compensation value applied collectively.

The pixel block includes a left half sub-block including the first and second penta-pixels located at the left half of the pixel block, and a second half pie block including the first and second penta pixels located on the right half of the pixel block .

The compensation value for each pixel block may include a first compensation value to be applied to the first color subpixels collectively, a second compensation value to be collectively applied to the second color subpixel in the left half subblock, A second compensation value applied collectively to the subpixels of the second color existing in the right half subblock, and a third compensation value applied to the subpixels of the third color collectively.

The pixel block includes 8 x 4 pixels. Each of the left half pixel block and the right half pixel block includes 4 x 4 pixels.

(X / M) x (Y / N) in a pixel array of a display panel having a resolution of XxY (X is larger than M and Y is a positive integer larger than N) x compensation value data size + checksum data size.

Wherein in the pixel array of the display panel having the resolution of X x Y (X is larger than M and Y is larger than N) resolution, the data size stored in the second memory is (X / M) x (Y / N ) x the compensation value data size.

The first compensation value, the second compensation value, the second compensation value, and the third compensation value are 8-bit data.

When the display panel operates in the partial mode, the compensation value for each pixel block is applied to the pixel data only for the pixels that are among all the pixels of the display panel.

The compensation unit adds the result of weighting the compensation value to pixel data of the input image.

The compensation unit includes at least one lookup table in which weights are individually set according to the luminance values received from the host system and the pixel data of the input image.

The compensation unit adds the result of weighting the compensation value to pixel data of the input image. When the display panel is driven in a high brightness mode (HBM) mode, a relatively large weight value among the weight values is added to the compensation value.

The first memory includes a flash memory, and the second memory includes a static RAM (SRAM).

The real-time compensation circuit of the present invention includes: a memory storing a plurality of compensation values for each pixel block set in units of pixel blocks including M x N (M and N are each a positive integer of 2 or more) pixels; A compensation unit for adding the compensation value for each pixel block to the pixel data of the input image to modulate the pixel data; And a data driver for converting the compensated pixel data received from the compensator into a data voltage.

An electroluminescent display of the present invention includes a display panel on which data lines, gate lines intersecting with the data lines, and pixels are arranged; A first memory storing a plurality of compensation values for each pixel block set in units of pixel blocks including M x N (M and N are each a positive integer of 2 or more) pixels; And a drive IC for applying compensated pixel data read from the first memory to the pixel data of the input image to generate compensated pixel data and converting the compensated pixel data to a data voltage to apply the compensated pixel data to the data lines. Respectively. The compensation value for each pixel block includes a compensation value to be applied collectively to each pixel in the pixel block in at least one color.

The present invention compensates the pixel data of the input image by compensating the mura on the screen by reflecting the result of the screen shooting using the camera, thereby sufficiently compensating the difference in driving characteristics between the pixels in the high resolution and high- The memory capacity of the circuit can be reduced.

Since the present invention compensates pixel data using only the gray level without calculating the threshold voltage (Vth) and mobility of the driving element, the logic circuit configuration for the operation can be reduced and the tact time ) Can be reduced.

According to the present invention, it is possible to realize the common use of the drive IC by compensating the pixel data of the input image by compensating the compensation value for each pixel block according to the penta-pixel arrangement and the real pixel arrangement according to the register setting, Drive mode can be supported.

FIG. 1 is a view schematically illustrating a method of determining a compensation value using a method for measuring a lightness of a camera in an electroluminescence display device according to an embodiment of the present invention. Referring to FIG.
2 is a flowchart illustrating a method of compensating an electroluminescent display according to an embodiment of the present invention.
3 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present invention.
4 is a diagram showing an example of a penta-pixel arrangement.
5 is a diagram showing an example of a real pixel arrangement.
6 is a circuit diagram showing an example of a pixel circuit.
7 is a waveform diagram showing a driving method of the pixel circuit shown in FIG.
8 is a diagram showing an example in which various image processing circuits and compensation units are connected.
9 is a view showing the compensation unit in detail.
10 is a diagram showing an example of an 8x4 pixel block applicable in a pentagonal pixel layout.
11 is a diagram showing an example of grouping pixels by dividing the pixels into 8x4 pixel blocks shown in FIG. 10 in the pentagonal pixel arrangement of WQXGA (1600x2560).
12 is a diagram showing subpixels for each color when the penta pixel arrangement of WQXGA (1600x2560) as shown in FIG. 11 is divided into 8x4 pixel blocks.
13 is a diagram illustrating an example in which compensation values are stored in the first memory in the order of scan directions defined by PID = 00 and SID = 00 when the WQXGA screen is divided into 8x4 pixel blocks in the same manner as in FIGS. 10 to 12 .
FIG. 14 is a diagram showing compensation values and checksum data stored in the first memory in the order shown in FIG.
15 is a diagram showing compensation values of 4 Bytes defined in one 8x4 pixel block.
16 is a diagram showing an example of an 8x4 pixel block applicable in a real pixel arrangement.
17 is a diagram showing an example in which pixels are grouped into 8x4 pixel blocks shown in Fig. 16 in a real pixel arrangement of resolution (1072x2560).
FIG. 18 is a diagram showing subpixels for each color when the real pixel arrangement of resolution (1072x2560) as shown in FIG. 17 is divided into 8x4 pixel blocks.
19 shows an example in which the compensation values are stored in the first memory in the order of scan directions defined by PID = 00 and SID = 00 when the screen of resolution (1072x2560) is divided into 8x4 pixel blocks by the method shown in Figs. It is a drawing.
FIG. 20 is a diagram showing compensation values and checksum data stored in the first memory in the order of FIG.
FIG. 21 is a diagram showing compensation values of 3 bytes defined in one 8x4 pixel block.
FIG. 22 is a diagram illustrating an example of applying the compensation value of the 8x4 pixel block shown in FIG. 10 to pixel data.
FIG. 23 is a diagram illustrating an example of applying the compensation value of the 8x4 pixel block shown in FIG. 16 to pixel data.
24 is a flowchart showing the overflow and underflow calculation processing of the arithmetic operation unit.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but is capable of many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the description of the embodiments, the first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other partially or wholly and technically various interlocking and driving are possible and that the embodiments may be practiced independently of each other, It is possible.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following embodiments, an electroluminescent display device will be described mainly with respect to an organic light emitting display device including an organic light emitting material. However, it should be noted that the technical idea of the present invention is not limited to the organic light emitting display, but can be applied to an inorganic light emitting display device including an inorganic light emitting material.

The real-time compensation circuit of the present invention includes a first memory storing a plurality of compensation values for each pixel block set in units of pixel blocks including M x N (M and N are each a positive integer of 2 or more) pixels, A compensator for modulating the pixel data by adding a compensation value for each pixel block to the pixel data of the input image, and a data driver for converting the compensated pixel data received from the compensator to a data voltage, Respectively.

The compensation value per pixel block includes a compensation value applied collectively to each pixel in the pixel block in at least one color. The pixel data and the compensation value for each pixel block are added between data of the same color.

The compensation value for each pixel block is set to a value for compensating for the smear obtained through image shooting of the display panel.

The compensation circuit for compensating the difference in driving characteristics of the pixels in the organic light emitting display may be divided into an internal compensation circuit and an external compensation circuit. The internal compensation circuit samples the threshold voltage of the driving element using an internal compensation circuit disposed in each of the pixels, adds a threshold voltage to the data voltage of the pixel data, drives the pixels, Automatically compensate. The external compensation circuit senses the electrical characteristics of the driving elements, and modulates the pixel data of the input image based on the sensed result, thereby compensating for the driving characteristic change of each of the pixels.

It should be noted that the compensation circuit of the present invention is described, but not limited to, the internal compensation circuit in the following embodiments.

In the electroluminescent display device of the present invention, the pixels and the gate driver include a plurality of transistors. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the transistor, the carriers begin to flow from the source. The drain is an electrode from which the carrier exits from the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, the current flows from the source to the drain because the holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed depending on the applied voltage. In the following description of the embodiment, the source and the drain of the transistor will be referred to as first and second electrodes. In the following description, the invention is not limited by the source and the drain of the transistor.

1 and 2, test image data is inputted to an electroluminescence display device in an inspection process, and a test image is displayed on a screen. The electroluminescent display device displays the test image data with the driving characteristic deviation of each of the pixels being compensated in real time through the compensation circuit (S1). Such an electroluminescent display device can be made unsecured because of insufficient sampling time of the driving elements in each of the pixels. As a result, even if data of the same gradation level is written to the pixels, the difference in brightness between the pixels on the screen can cause a smear.

The computer 200 displays a test image on the display panel 100 of the electroluminescence display device at a test factory according to a preset program and photographs the screen of the display panel 100 with the camera 210 to obtain a test image The luminance is measured (S2). Incomplete compensation may be reflected in the image displayed on the electroluminescence display device, and the smear may be seen, and the smear is photographed by the camera 210. The test image image photographed by the camera 210 is transmitted to the computer 200.

The computer 200 stores a reference compensation value set in units of pixel blocks of a predetermined size. The pixel block includes M x N pixels. The computer 200 adjusts the reference compensation value until the luminance difference between the pixels in the image received from the camera 210 becomes equal to or less than the preset luminance uniformity, adds the compensation value to each pixel data of the test image, And transmits it to the display panel drive circuit. The display panel driving circuit writes the pixel data of the input image to the pixels of the display panel 100, and displays the pixel data of the input image on the pixels. If a smear is seen in the image photographed by the camera 210, it means that the luminance difference between the pixels is larger than the predetermined luminance uniformity.

The display panel drive circuit writes the pixel data of the test image received from the computer 200 to the pixels of the display panel 100 and displays the pixel data of the test image to which the compensation value is applied on the screen, ) Captures the updated test image (S2 to S4). The computer 200 stores the compensation value applied when the luminance deviation between the pixels of the image received from the camera 210 becomes equal to or less than the preset luminance uniformity, as an optimal compensation value (S5 and S6). The optimum compensation value is stored in the first memory 30 connected to the compensation circuit of the electroluminescence display. The first memory 30 may be a flash memory, for example, but is not limited to, a flash memory which is free from read / write while stored information is maintained even when the power is turned off. The compensation value for each pixel block is generated for each pixel and for each color by repeating steps S1 to S6.

The compensation value for each pixel block is divided into a real pixel pixel arrangement and a pentile pixel arrangement. A real pixel arrangement consists of one pixel of red, green and blue subpixels. As a result of performing the steps S1 to S6 while driving the display panel having the real pixel arrangement, the compensation value for each pixel block of the real pixel arrangement can be obtained. A display panel having a penta-pixel arrangement drives two sub-pixels of different colors into one pixel using a preset penta-pixel pixel rendering algorithm. As a result of performing the steps S1 to S6 while driving the display panel, a compensation value for each pixel block of the penta-pixel arrangement can be obtained. The penta pixel rendering algorithm compensates for the color representation that is lacking in each of the pixels with the color of the light emitted by the adjacent pixels.

The electroluminescent display device storing the optimum compensation value through steps S1 to S6 loads the compensation value stored in the first memory 30 into the second memory in the compensation circuit every time the power is turned on after shipment. The second memory 31 may be implemented as a RAM (random-access memory) such as SRAM (Static RAM).

The electroluminescence display device of the present invention collectively applies pixel data in at least one color in a pixel block with a compensation value read from a second memory when pixel data of an input image is input, and compensates the pixel data in real time S7). Therefore, according to the present invention, in the electroluminescence display of a high-resolution, high-speed driving model, by extracting the camera shooting-based mura compensation value in unit of pixel block and collectively applying the compensation value to at least one color in the pixel block, / Even if the compensation of the external compensation circuit is insufficient, it is possible to realize a uniform image quality throughout the entire screen by further reflecting the compensation based on camera shooting, and the memory capacity to which the compensation value is applied can be greatly reduced.

3 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present invention.

3 to 5, an electroluminescent display device of the present invention includes a display panel 100, a drive IC (Integrated Circuit) 20 for writing pixel data of an input image to pixels of the display panel 100, A first memory 30 connected to the drive IC 20, a gate driver 40, a host system 50, and the like.

The display panel 100 includes a pixel array in which the gate lines GL1 and GL2 intersecting with the data lines DL1 to DL6 and the pixels P are arranged in a matrix form. The data lines DL1 to DL6 supply the data voltages from the drive IC 20 to the pixels P. [ The gate lines GL1 to GL3 supply a gate signal from the gate driver 40 to the pixels P. [ The gate signal can be divided into a scan signal SCAN, an emission control signal EM (hereinafter referred to as EM signal), an initialization signal INI, and the like as shown in FIG. In this case, each of the gate lines GL1 and GL2 includes a SCAN line 71 for supplying a scan signal SCAN to one line of pixels P, an EM signal EM to one line of pixels P An IN line 73 for supplying the initialization signal INI to one line of pixels P, and the like.

Each of the pixels includes sub-pixels of different colors for color implementation. Subpixels include red (hereinafter referred to as "R"), green (hereinafter referred to as "G subpixel"), and blue (hereinafter referred to as "B subpixel"). Although not shown, a white sub-pixel (hereinafter referred to as " W sub-pixel ") may be further included. Each of the subpixels may include, but is not limited to, the pixel circuit shown in FIG. It should be noted that the pixel circuit may be implemented as a pixel circuit of various known structures.

4 is a diagram showing an example of a penta-pixel arrangement. In the example of FIG. 4, one pixel includes R subpixels and G subpixels or includes B and G subpixels. Each of the pixels in the pentamer pixel arrangement consists of but is not limited to two subpixels in the example of FIG. The penta pixel rendering algorithm renders each of the pixel data of the input image including the RGB data to fit the color arrangement of the pixel P and compensates the color representation by adding the missing color data to the color data of the neighboring pixels. Any of the well-known penta-pixel rendering algorithms are available.

5 is a diagram showing an example of a real pixel arrangement. In the example of Fig. 5, one pixel includes R subpixel, G subpixel, and B subpixel. Thus, each of the pixels in the real pixel arrangement consists of three subpixels in the example of FIG. 5, but is not limited thereto.

The display panel 100 includes an ELVDD line 74 for supplying a pixel driving voltage ELVDD to the pixels P as shown in Fig. 6, a Vref line (not shown) for supplying a reference voltage Vref to the pixels 75, an ELVSS electrode 76 for supplying a low potential power supply voltage ELVSS to the pixels, and the like. These power supply lines are connected to a power supply circuit not shown. The power supply circuit generates a DC power required for driving the display panel by using a DC-DC converter. The DC-DC converter includes a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply circuit may be implemented as a power integrated circuit (PIC).

The power supply circuit outputs a power source necessary for driving the pixels P of the display panel, for example, ELVDD, VGH, VGL, Vref, an analog gamma voltage, and the like. VGH is the gate high voltage, and VGL is the gate low voltage.

A gate driver 40 may be formed on the substrate of the display panel 100 together with the pixel array. Each of the pixels P and the gate driver 40 is implemented with a plurality of transistors. The transistors include TFTs including oxide semiconductor, thin film transistors (TFT), amorphous silicon (a-Si), and low temperature polysilicon (LTPS) Or more. The TFT may be implemented by a metal oxide semiconductor field effect transistor (MOSFET) structure. The TFT may be implemented as one of an n-type transistor (NMOS) or a p-type transistor (PMOS) or a combination thereof.

The gate signal outputted from the gate driver 40 is a gate-on voltage between the gate on voltage on which the TFT can be turned on and a gate off voltage on which the TFT can be turned off . In the NMOS, the gate-on voltage is VGH and the gate-off voltage is VGL. In the PMOS, the gate-on voltage is VGL and the gate-off voltage is VGH.

The gate driver 40 includes a shift register. The shift register includes a plurality of stages connected in a dependent manner and shifts the output voltage according to the gate shift clock timing to sequentially supply the gate signals GATE1 and GATE2 to the gate lines GL1 and GL2 do.

The driver IC 20 includes a timing control section 21, a data driving section 22, a second memory 31, a compensation section 32, a register 33, and the like.

The timing control unit 21 uses the timing signals received from the host system 50 such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock signal DCLK and the data enable signal DE And generates timing control signals for controlling the operation timings of the gate driver 40 and the data driver 22. The host system 50 may be any one of a television system, a set top box, a navigation system, a personal computer (PC), a home theater system, a mobile system, a wearable system, and a virtual reality system.

The data driver 22 converts the pixel data (digital signal) of the input image received from the compensator 32 into an analog signal and outputs a data signal DATA1 to DATA6 Quot; DAC "). The data driver 22 supplies the data signals DATA1 to DATA6 to the pixels P through the data lines DL1 to DL6.

The second memory 31 stores the compensation value received from the first memory 30 when power is supplied and supplies the compensation value to the compensation unit 32. [ The compensation unit 32 receives the pixel data of the input image from the host system 50. [ The compensation unit 32 adds the pixel block compensation value input from the second memory 31 to the pixel data of the input image, and transmits the compensation value to the data driving unit 22. Therefore, the pixel data input to the data driver 22 includes the compensation value obtained through camera photographing.

The register 33 stores tables defining the function setting of the compensation unit 32. [ The function of the compensation unit 32 may be changed according to the register setting value.

6 is a circuit diagram showing an example of a pixel circuit. 7 is a waveform diagram showing a driving method of the pixel circuit shown in FIG. The pixel circuit of the present invention is not limited to Fig.

Referring to Figs. 6 and 7, the pixel circuit includes a plurality of TFTs M1 to M6, a capacitor Cstg, and an OLED.

A scan signal SCAN, an initialization signal INI, and an EM signal EM are supplied to the pixels P during one horizontal period (1H). One horizontal period 1H is obtained by sampling the threshold voltage of the third TFT M3 and adding it to the data voltage during the period of t2 and t3 for initializing the pixel circuit and by applying the voltage of the data signal Lt; RTI ID = 0.0 > Vdata). ≪ / RTI >

The OLED includes an anode and a cathode. The anode of the OLED is connected to the fifth and sixth TFTs M5 and M6. The low potential supply voltage (ELVSS) is applied to the cathode of the OLED.

The first TFT M1 is turned on according to the scan signal SCAN to apply the data signal from the data line 77 to the first node n1. The first TFT M1 includes a gate connected to the scan line 71, a first electrode connected to the data line 77, and a second electrode connected to the first node n1.

The second TFT M2 is turned on according to the EM signal EM to initialize the first node n1 to a predetermined reference voltage Vref. The second TFT M2 includes a gate connected to the EM line 72, a first electrode connected to the first node n1 and a second electrode connected to the Vref line 75 to receive the reference voltage Vref do. The fifth TFT M5 is turned on according to the EM signal EM to initialize the third node n3 to the reference voltage Vref. The fifth TFT M5 includes a gate connected to the EM line 72, a first electrode connected to the third node n3, and a second electrode connected to the anode of the OLED.

The third TFT M3 is a driving device for driving the OLED by regulating the current flowing in the OLED according to the gate voltage. The third TFT M3 includes a gate connected to the second node n1, a first electrode connected to the ELVDD line 74 and supplied with the ELVDD, and a second electrode connected to the third node n3. The capacitor Cst is connected between the first and second nodes n1 and n2 to hold the data voltage added with the threshold voltage of the third TFT M3 for one frame period.

The fourth TFT M4 is turned on during the period t3 and t4 during which the threshold voltage of the third TFT M3 is sampled to connect the gate of the third TFT M3 to the second electrode. The third TFT M3 operates as a diode by the fourth TFT M4 during the periods t3 and t4. The fourth TFT M4 is connected to the SCAN line 71 and has a gate supplied with the scan signal SCAN, a first electrode connected to the gate of the third TFT M3, and a second electrode connected to the second electrode of the third TFT T3, And a second electrode connected to the second electrode.

The sixth TFT M6 is turned on according to the initialization signal INI to initialize the anode of the OLED to the reference voltage Vref. The sixth TFT M6 includes a gate connected to the INI line 73, a first electrode connected to the Vref line 75, and a second electrode connected to the anode of the OLED.

The operation of the pixel circuit will be described step by step.

Each of the pixels maintains previous frame data in a period t1. During the period t1, the voltage of the first node n1 is applied with the reference voltage Vref.

The gate-on voltage of the initialization signal INI is applied to the pixel circuit at the same time as the start of the t2 period, and the gate-on voltage of the scan signal SCAN is applied to the pixel circuit immediately after the t3 period. the first and fourth TFTs Ml and M4 are turned on according to the gate on voltage of the initialization signal INI during the periods t2 and t3 after the sixth TFT M6 is turned on according to the gate- It turns on according to the voltage. Since the EM signal EM maintains the gate-on voltage during the periods t2 and t3, the second and fifth TFTs M2 and M5 remain on. As a result, the anode of the first node n1, the second node n2, the third node n3, and the OLED are initialized to the reference voltage Vref during the period t2.

The EM signal EM is inverted to the gate-off voltage in the period t4. Therefore, during the period t4, the second and fifth TFTs M2 and M5 are turned off. the data voltage DATA is charged to the first node n1 through the first TFT M1 during the period t4. During the period t4, when the gate voltage of the third TFT M3 and the voltage between the second electrodes reach ELVDD + Vth, the third TFT M3 is turned off. As a result, the voltages of the second and third nodes are charged to ELVDD + Vth in the period t4. At this time, the voltage of the capacitor Cstg is ELVDD + Vth + Vdata. And Vth is the threshold voltage of the third TFT (M3) which is the driving element. The period t4 is a programming period for sampling the threshold voltage Vth of the third TFT M3 as the driving element and compensating the data voltage Vdata by the threshold voltage Vth.

The EM signal EM is inverted to the gate-on voltage at the same time as the start of the t5 period. The period t5 is a light emitting period in which the OLED emits light according to the data voltage and emits light corresponding to the gradation of the pixel data. During the period t5, the scan signal SCAN and the initialization signal INI are inverted to the gate-off voltage. Thus, during the t5 period, the second and fifth TFTs M2 and M5 are turned on to form the current path of the OLED while the other switch elements M1, M4 and M6 are turned off.

The current (I _oled ) flowing in the OLED during the t5 period is given by the following equation. As can be seen from this equation, the current flowing through the OLED is not affected by the Vth of the third TFT M3, so that it is not affected by a change in Vth over time or a Vth deviation between pixels. Vgs is the gate-source voltage of the third TFT (M3) and Vds is the drain-source voltage of the third TFT (M3).

Here, K is a proportional constant determined by the charge mobility, parasitic capacitance, channel capacity, and the like of the third TFT (M3).

An image processing circuit other than the compensation unit 32 may be connected to the compensation unit 32 to process the pixel data of the input image in a complex manner. In this case, the compensation section 32 and other image processing circuits must be efficiently connected.

8 is a diagram showing an example in which various image processing circuits and compensation units are connected.

8, the drive IC 20 further includes a picture quality enhancement unit 81 and a real / penta conversion unit 82 disposed at the front end of the compensation unit 32. [

The image quality enhancement unit 81 processes the input image data by a preset algorithm to improve the image quality such as color temperature compensation, sharpness improvement, and HDR (High Dynamic Range).

The real / penta converter 82 converts real pixel data (RGB data) into penta-pixel data (RG or GB data) using a penta-pixel rendering algorithm. The real pixel data RGB RGB (2 pixels, 6 sub-pixels) is converted into RG BG (2 pixels, 4 sub-pixels) by the real /

When the compensation unit 32 is disposed in front of the image quality enhancement unit 81 or the real / penta converter 82, the compensation value for each pixel block is added by the compensation unit 32 and the modulated pixel data is supplied to the image quality enhancement unit 81 ) And / or the real / penta converter 82, the effect of applying the compensation value for each pixel block may be changed. Therefore, the compensation unit 32 is effective in applying the compensation value for each pixel block to the pixel data modulated by the other image processing circuit.

9 is a view showing the compensation unit 32 in detail.

Referring to FIG. 9, the compensation unit 32 collectively applies compensation values of the pixel blocks obtained through camera photographing to at least one color in a pixel block of the input image. The present invention can greatly reduce the capacity of the memories 30 and 31 by grouping the pixels into pixel block units of predetermined sizes and collectively applying the same compensation value to the pixel data of at least one color in the pixel block.

The function of the compensation unit 32 can be selected according to a register setting value defined in a table in the register 33. [ The compensation unit 32 includes an operation unit 321 and one or more look-up tables (LUTs) 341 to 349.

The operation unit 321 outputs data (DATA ') to which the camera shooting-based mura compensation value is applied by adding the compensation value for each pixel block to the pixel data (DATA) of the input image to modulate the pixel data. The compensation value for each pixel block may be added with a predetermined weight to the lookup tables 341 to 349. [ The weights may vary depending on the luminance value received from the host system and the pixel data of the input image. The lookup tables 341 and 342 can be selected according to the driving mode of the display device, the luminance value received from the host system, and the pixel data of the input image, and output a weight value. The host system 50 may analyze the various sensor signals and automatically switch the drive mode or switch the drive mode according to a user command input through the user interface.

The lookup tables 341 to 349 set different weights according to the luminance value DBV or the input tone value GRAY input to the host system 50. [ The input tone value is the tone of the pixel data received from the input image data, that is, the original tone value. The weight output from the lookup table is reflected in the pixel data of the input image as an additional compensation value added to the compensation value of the loaded pixel block from the second memory 31. [ The luminance value DBV indicates the maximum gradation value of the pixel data, for example, the brightness corresponding to the gradation 255 in the case of 8-bit data. The brightness value DBV is a brightness value automatically set by the host system by a user command inputted from a user through a user interface or various sensors such as an illuminance sensor.

The operation unit 32 inputs the luminance value DBV and the input tone value GRAY to the lookup tables 341 and 349 in the manner shown in Table 1 below to calculate the weights output from the lookup tables 341 and 349 as To the compensation value for each pixel block, and add the result to the pixel data. Each of the lookup tables 341 and 349 is selected in accordance with the luminance value DBV and the input tone value GRAY in the same manner as in Table 1. For example, the LUT1 341 is selected when the luminance value DBV is GCBDBV_TH1 [9: 0] and the tone value GRAY is GCBGRAY_TH1 [7: 0]. LUT3 343 is selected when the luminance value DBV is GCBDBV_255 and the tone value GRAY is GCBGRAY_TH1 [7: 0]. The LUT9 349 is selected when the luminance value DBV is GCBDBV_1023 and the gradation value GRAY is GCBGRAY_255.

In accordance with the luminance value DBV and the gray level value GRAY when mura is different depending on the luminance value of the maximum gradation level or the gradation value of the pixel data by using the weight value set in the lookup tables 341 to 349, It is possible to finely compensate various mura. If the peak value is set as the look-up table data as shown in Table 1 below, the compensation value can be divided into nine different situations in which the luminance value and the gray value are different from each other.

GCBGRAY_TH1 [7: 0] GCBGRAY_TH2 [7: 0] GCBGRAY_255 GCBDBV_TH1 [9: 0] LUT1 LUT2 LUT3 GCBDBV_TH2 [9: 0] LUT4 LUT5 LUT6 GCBDBV_1023 LUT7 LUT8 LUT9

The following example illustrates Table 1 as a quantitative value. In the table below, +2 set in the LUT1 341 is output when the luminance value DBV is 50 nit or less and the tone value GRAY is 15 or less. When the luminance value DBV is greater than 100 nits and less than 200 nit and the tone value GRAY is greater than 100 and less than 200, -1 set in the LUT9 349 is output. The weight setting method of the look-up table is not limited to this.

The register 33 includes one or more tables 331 to 333 for storing setting values for controlling the operation unit 321. [ The register settings may be stored in the first memory 30 and loaded into the second memory 31 from the first memory 30.

The first table 331 may be set as shown in Table 2 below. The first table 331 defines on / off setting of the compensator 32 and whether or not the compensator is supported in the various operation modes supported by the drive IC 22 and a support method. In Table 1, "Normal" indicates a state in which pixel data bypasses the data driver 22 without passing through the compensator 32. [ "GCB" is a camera shooting based mura compensation method of the present invention. Therefore, the GCB is a state in which the pixel data is input to the compensation unit 32 and the pixel data is modulated by the compensation value for each pixel block.

"PPA" represents a penta-pixel arrangement. The modulation section 32 supports real color arrangement (RGB) and penta color arrangement (RG / GB) at all resolutions. The compensation unit 32 supports all panel scan directions. The PID (Panel ID) and the SID (Scan ID) define various scan directions such as whether the scan direction moves from the upper left corner to the lower right direction, or whether the scan direction moves from the upper right corner to the lower left corner. The PID (Panel ID) and the SID (Scan ID) allow the scanning direction to be changed according to the real color arrangement (RGB) and the penta color arrangement (RG / GB) or according to the position of the drive IC 20.

The partial mode in Table 2 is a driving mode in which only a part of pixels in the pixel array of the display panel 100 is driven and the other pixels are turned off. In the always on mode and the virtual reality mode (VR), the screen can be driven in the partial mode. The compensation unit 32 applies a compensation value for each pixel block only to the pixel data to be written to the ON pixels in the partial mode, bypasses the other invalid data, Power, and heat can be efficiently managed.

The idle mode is one of a low power mode and reproduces pixel data in only eight colors by allowing only the minimum gradation G0 and the maximum gradation G255 to be expressed in each color of RGB. In this idle mode, the compensation unit 32 is not driven in the idle mode because the compensation value is applied by the compensation unit 32 or there is no image quality difference.

The PLC (peak luminance control) is a control method of the drive IC 20 that lowers the peak luminance in a bright image in order to reduce power consumption at a certain level or more of luminance of an input image. The compensation section 32 can operate in the PLC.

The BC (Brightness control) is a method of controlling various brightness of the drive IC 20. High brightness mode (HBM) is a driving mode that brightens pixels in outdoor environments. The image signal processing (ISP) is another image processing circuit described in the example of Fig. The compensation unit 32 may support BC, HBM, and ISP. The compensating unit 32 may further increase the brightness of the pixels by adding the maximum weight value (GCB_LUT7) set in the look-up table (LUT) to the compensation value for each pixel block to increase the luminance in the HBM.

State Normal GCB Remark Resolution Support Support Real support, PPA support, all resolutions supported Panel Scan Direction Support Support Operation for all PID, SID (PID during operation, change of SID is not supported) Partial Mode Support Support 1. Non-display area requires no operation
2. Partial area can be set line by line.
3. The GCB SRAM read function is supported by a partial area set. Idle Mode Support N / A G0, G255 do not need GCB.
Image data bypasses the GCB block PLC Support Support BC Support Support HBM Support Support Works with GCBDBV_1023 (GCB_LUT7-9) ISP Support Support

The second table 332 may be set as shown in Table 3 below. The second table 332 defines whether to apply weighting, a data error check option, and the like.

GCB_ERRFG "is a GCB error flag. When power is supplied to the drive IC 20 and the compensation value stored in the first memory 30 in the drive IC 20 The drive IC 20 calculates a checksum in order to check the error of the received data and outputs the calculated value to the first memory 31. [ If there is an abnormality in the received data as a result of the checksum calculation, change "GCB_ERRFG" to "1" to indicate that there is an error in the data loading exaggeration. When there is an error (erroe) in the checksum comparison process, "GCB_ERR_CNT [1: 0] ", the drive IC 20 reads data from the first memory 30 again and loads it. . If "GCB_ERR_CNT [1: 0]" is set to 2, checksum error is vanished twice and reloading of the first memory 30 data is possible up to three times. If GCB_ERR_CNT [1: 0] exceeds the number of loading times and the error still occurs, change GCB_ERRFG to 1 and operate as defined by GCB_CON. GCB_SUM [15: 0] FLASH_RD_ST "," FRASH_RD_STB ", and" FLASH_FRM [2: 0] "are read out options of the second memory data. Options can be changed.

Register Name Description Default GCB_EN 0: Bypass 1: Enable 0h GCBDBV_TH1 to 2 [9: 0] Luminance LUT Range setting.
Both TH1 and TH12 can be set from 0 to 1023.
0? TH1? TH2? 1023 GCBGRAY_TH1 ~ 2 [7: 0] Gray LUT Range setting.
TH1,2 All 0 ~ 255 can be set.
0? TH1? TH2? 255 GCB_LUT1 to 9 [3: 0] weight.
Final Output = compensation value per pixel block + LUT output
In case of HBM, GCB_LUT7 ~
0: Bypass (Original image)
1: -7 2: -6 3: -5 4: -4 5: -3 6: -2 7: -1 8: +0 9: +1 10: +2 11: +3 12: +5 14: +6 15: +7 8h GCB_LUT_EN 0: Disable (weight is not applied)
1: Enable (Weighted)
(HBM is weighted by GCB_LUT7 ~ 9 output even if GCB_LUT_EN = 0) 0h GCB_SUM [15: 0] Checksum parameter. Read only GCB_ERRFG
When the number of failures set in GCB_ERR_CNT is exceeded, GCB_ERRFG is changed to 1.
Recovery to 0 only at Sleep-in. Read only GCB_ERR_CNT [1: 0] Fail Allowance Count during Checksum Comparison
0: 0 1: 1 2: 2 3: 3 1h GCB_CON If GCB_ERRFG is 1 (read error of 1st memory), GCB operation setting.
0: Ignore Error and GCB operation,
1: GCB function Bypass 1h FLASH_RD_ST At the time of the read start of the first memory at the time of sleep-out
0: Sleep-out and synchronous
1: (FLASH_RD_STB + FLASH_FRM) After time 0h FLASH_RD_STB [7: 0] Flash read start delay at sleep-out.
0H to 255H 0h FLASH_FRM [2: 0] The frame delay to apply to FLASH_RD_ST.
0: 0 frame 1: 0.5 2: 1 3: 1.5 4: 2 5: 2.5 6: 3 7: 3.5 0h

The third table 333 can be set as shown in Table 4 below. The third table 333 defines the read / write options of the first and second memories 30 and 31.

Register Name Description SRAM Read / Write
Definition of how a user can read / write data to a second memory Flash Read / Write Define the data read / write method for each of the second memory -> first memory, first memory -> second memory Flash Low Power Mode After completing the data read of the first memory, the first memory is switched to the low power mode (when sleep-out is switched to the normal mode) Flash Power Down Mode After data read of the first memory is completed, the first memory is switched to the power down mode
(switch to normal mode at sleep-out) SRAM Power Down Mode When GCB function is disabled
Switching the power down mode of the second memory

10 is a diagram showing an example of an 8x4 pixel block applicable in a pentagonal pixel layout. 11 is a diagram showing an example of grouping pixels by dividing the pixels into 8x4 pixel blocks shown in FIG. 10 in the pentagonal pixel arrangement of WQXGA (1600x2560). 12 is a diagram showing the number of subpixels for each color when the penta pixel arrangement of WQXGA (1600x2560) is divided into 8x4 pixel blocks.

Referring to FIG. 10, an 8x4 pixel block includes 8 pixels in the row direction and 4 pixels in the column direction. Each of the pixels P includes an R subpixel and a B subpixel as shown in FIG. 4, or two subpixels including a B subpixel and a G subpixel. Thus, an 8x4 pixel block includes 16x4 subpixels.

Each of the pixel data is input as real pixel data including RGB data, and the real pixel data is converted into pixel data including RG or GB data by the real / The real pixel data RGB RGB (2 pixels, 6 sub-pixels) is converted into RG BG (2 pixels, 4 sub-pixels) by the real /

Each of the R data and B data to be written in the 8x4 pixel block is 8x4 in terms of real pixel data. The number of G data to be written in 8x4 pixel blocks is 8x4.

In the case of the 8x4 pixel block as shown in Fig. 10, the compensation value for each pixel group is divided into one R compensation value to be collectively applied to 8x4 R data, one B compensation value to be collectively applied to 8x4 B data, And a total of four compensation values including two G compensation values GL and GR to be applied. Accordingly, the compensation value for each pixel group includes compensation values much smaller than the actual number of pixels, so that the memory capacity required for the compensation unit 32 can be greatly reduced. Each of the compensation values may be 8 bits, that is, R: 8 bits, GL: 8 bits, B: 8 bits, and GR: 8 bits. If each of the compensation values is 8-bit data, -127 to +128 can be represented, so -127 to +128 can be added to the pixel data of the input image.

The present invention separates the G compensation values (GL, GR) having high luminance contribution into two in order to finely represent the luminance of a 4x4 pixel block. When the pixel block is divided into the left half sub block BLOCK1 and the right half block BLOCK2, the G compensation values GL and GR are divided into a first G compensation value GL, which is collectively applied to the G subpixels of the left half sub block BLOCK1, Value GL and a second G compensation value GR applied collectively to the G subpixels of the right subblock BLOCK2. On the other hand, in the 2.2 gamma curve, the contribution of luminance to each RGB color is R: G: B = 0.25: 0.65: 0.10.

It is not limited that the G compensation value is divided into two in the 8x4 pixel block. For example, in the case of a model in which it is not necessary to separate the G compensation value within an 8x4 pixel block, the G compensation value can be set to one.

10 to 12, 1600x2560 is divided into 8x4 pixel blocks in the penta pixel arrangement of WQXGA (1600x2560). Therefore, the memory size of the second memory 31, that is, the SRAM is compensated for each pixel Value is much less than 1600/8 x 2560/4 x 32 bits = 4,096,000 bits. Here, 32 bits is a data size obtained by adding R: 8 bits, GL: 8 bits, B: 8 bits, and GR: 8 bits. (X / M) stored in the second memory 31, that is, the SRAM, in the case of the display panel 100 having the resolution of X x Y (X is larger than M and Y is larger than N) x (Y / N) x is the compensation value data size per pixel block. In the above example, the compensation value data size per pixel block = 8 bits x 4 = 32 bits.

FIGS. 13 to 15 are views showing the compensation values stored in the first memory 30 when the WQXGA screen is divided into 8x4 pixel blocks by the method as shown in FIGS. 10 to 12. FIG. 13 is a diagram illustrating an example in which compensation values are stored in the first memory in the order of scan directions defined by PID = 00 and SID = 00 when the WQXGA screen is divided into 8x4 pixel blocks in the same manner as in FIGS. 10 to 12 . FIG. 14 is a diagram showing compensation values and checksum data stored in the first memory in the order shown in FIG. 15 is a diagram showing compensation values of 4 Bytes defined in one 8x4 pixel block.

13 to 15, the compensation value for each pixel block may be stored in the first memory 30 in the order of following the scanning direction determined by the PID and the SID. For example, when PID = 00 and SID = 00, the compensation value of the pixel block located at the upper right end 200, 1 from the compensation values R1_1, GL1_1, B1_1 and GR1_1 of the pixel block located at the upper left (1, (R200_1, GL200_1, B200_1, GR200_1) are stored in the first memory (30) in the order of the pixel block compensation values. Subsequently, compensation values for the respective pixel blocks are stored in the order of the lower left pixel block to the lower right pixel block. The compensation values R200_640, GL200_640, B200_640, and B200_640 of the pixel block located at the lower right 200 and 640 from the compensation values (R1_640 GL1_640, B1_640 and GR1_640) of the pixel block located at the lower left end (1,640) The compensation values for each pixel block are stored in the first memory 30 in the order of GR200_640.

The compensation values allocated to one 8x4 pixel block are stored in the first memory with 4 Byte data. For example, the compensation values to be applied to the pixel data of the upper left 8x4 pixel block (1, 1) include R bytes of 1-byte R compensation value (R1_1), 1-byte GL compensation value (GL1_1) A B compensation value B1_1 of 1 byte, and a GR compensation value GR1_1 of 1 byte. The luminance of the smear photographed by the camera is a smear (+) of luminance higher than the target luminance and a smear (-) of luminance lower than the target luminance. Thus, the compensation value may also include a + compensation value and a compensation value. When the compensation value is 8 bits, the compensation value can express -127 to +128 in the actual use gradation using the complement of 2.

2 bytes of check sum data (Checksum1 and Checksum2) for data error checking are stored in the first memory 30 when the computer 200 transmits compensation value data for each pixel block to the first memory 30. [ The data for each pixel block is applied to the pixel data of the input image in real time, and the checksum data (Checksum1 and Checksum2) are not reflected in the pixel data.

Accordingly, when the WQXGA screen is divided into 8x4 pixel blocks by the method as shown in FIGS. 10 to 12, the first memory, that is, the flash memory size is much smaller (200x640x4) byte + 2byte checksum . In the case of the display panel 100 having the X x Y resolution, the data size = (X / M) x (Y / N) × the compensation value data size per pixel block + the checksum data size stored in the first memory 30.

The drive IC 20 of the present invention can be applied to both a display panel having a penta-pixel arrangement and a display panel having a real pixel arrangement. If a register set value is selected according to the pixel arrangement, one of the light ICs 20 can be applied to a penta pixel arrangement or a real pixel arrangement.

16 is a diagram showing an example of an 8x4 pixel block applicable in a real pixel arrangement. 17 is a diagram showing an example in which pixels are grouped into 8x4 pixel blocks shown in Fig. 16 in a real pixel arrangement of resolution (1072x2560). FIG. 18 is a diagram showing subpixels for each color when the real pixel arrangement of resolution (1072x2560) as shown in FIG. 17 is divided into 8x4 pixel blocks.

Referring to FIG. 16, an 8x4 pixel block includes 8 pixels in the row direction and 4 pixels in the column direction. Each of the pixels P includes an R subpixel, a G subpixel, and a B subpixel as shown in Fig. Thus, an 8x4 pixel block includes 24x4 subpixels. Each of the R data, G data, and B data to be written in the 8x4 pixel block is 8x4.

In the case of the 8x4 pixel block as shown in Fig. 16, the compensation value for each pixel group is divided into one R compensation value to be collectively applied to 8x4 R data, one G compensation value to be collectively applied to 8x4 G data, And a total of three compensation values including one B compensation value to be applied. Accordingly, the compensation value for each pixel group includes compensation values much smaller than the actual number of pixels, so that the memory capacity required for the compensation unit 32 can be greatly reduced. Each of the compensation values may be 8 bits, that is, R: 8 bits, G: 8 bits, and B: 8 bits. If each of the compensation values is 8-bit data, -127 to +128 can be represented, so -127 to +128 can be added to the pixel data of the input image.

The G compensation value may be set to one for each 8x4 pixel block and may be divided into two in each pixel block in the same manner as the embodiment shown in Fig.

16 to 18, 1072x2560 is divided into 8x4 pixel blocks in the real pixel arrangement of resolution (1072x2560). Therefore, the memory size of the second memory 31, that is, the SRAM, Which is much less than 1072/8 x 2560/4 x 24 bits = 2,058,240 bits. Here, 24 bits is a data size obtained by adding R: 8 bits, G: 8 bits, and B: 8 bits. In the case of the display panel 100 having the X, Y, and Y resolution, the data size = (X / M) x (Y / N) x pixel block compensation value data size stored in the second memory 31, that is, the SRAM. In the above example, the compensation value data size per pixel block = 8 bits x 3 = 24 bits.

FIGS. 19 to 21 are diagrams showing compensation values stored in the first memory 30 when a screen of resolution (1072x2560) is divided into 8x4 pixel blocks by the method shown in FIGS. 16 to 8. FIG. 19 shows an example in which the compensation values are stored in the first memory in the order of scan directions defined by PID = 00 and SID = 00 when the screen of resolution (1072x2560) is divided into 8x4 pixel blocks by the method shown in Figs. It is a drawing. FIG. 20 is a diagram showing compensation values and checksum data stored in the first memory in the order of FIG. FIG. 21 is a diagram showing compensation values of 3 bytes defined in one 8x4 pixel block.

19 to 21, the compensation value for each pixel block may be stored in the first memory 30 in the order of following the scan direction determined by the PID and the SID. For example, when PID = 00 and SID = 00, the compensation value (R134_1) of the pixel block located at the upper right end 134, 1 from the compensation values R1_1, G1_1 and B1_1 of the pixel block located at the upper left (1, , G134, and B134_1 are stored in the first memory 30 in the order of the pixel block compensation values. Subsequently, compensation values for the respective pixel blocks are stored in the order of the lower left pixel block to the lower right pixel block. (R134_640, G134_640, B134_640) of the pixel block located at the lower right end (134, 640) from the compensation value (R1_640 G1_640, B1_640) of the pixel block located at the lower left end (1,640) The compensation values for each pixel block are stored in the first memory 30 in this order.

The compensation values allocated to one 8x4 pixel block are stored in the first memory 30 as 3-byte data. For example, the compensation values to be applied to the pixel data of the upper left 8x4 pixel block (1, 1) include R bytes of 1-byte R compensation value R1_1, 1 byte G compensation value G1_1, and 1 And the B compensation value B1_1 of the Byte.

2 bytes of check sum data (Checksum1 and Checksum2) for data error checking are stored in the first memory 30 when the computer 200 transmits compensation value data for each pixel block to the first memory 30. [ The data for each pixel block is applied to the pixel data of the input image in real time, and the checksum data (Checksum1 and Checksum2) are not reflected in the pixel data.

When the screen of resolution (1072x2560) is divided into 8x4 pixel blocks in the same manner as in Figs. 16 to 18, the size of the first memory, i.e., the flash memory is much smaller (134x640x4) byte + 2byte checksum. In the case of the display panel 100 having the X x Y resolution, the data size = (X / M) x (Y / N) × the compensation value data size per pixel block + the checksum data size stored in the first memory 30.

FIG. 22 is a diagram illustrating an example of applying the compensation value of the 8x4 pixel block shown in FIG. 10 to pixel data.

22, "R4x4" is pixel data (R data) of an input image to be written in 4x4 R subpixels existing in the left half BLOLK1 and right half BLOLK2, and G4x4L " (G data) of the input image to be written to 4x4 G subpixels existing in the right half BLOLK2 of the input image to be written to 4x4 G subpixels present in the right half BLOLK2, Data). And "B4x4" is pixel data (B data) of the input image to be written in 4x4 B subpixels existing in the left half (BLOLK1) and the right half (BLOLK2). "R1_1_OFFSET" is one R compensation value to be collectively applied to the R subpixels. Quot; GL1_1_OFFSET "is one G compensation value GL to be collectively applied to the G subpixels of the left half (BLOLK1). "GR1_1_OFFSET" is one G compensation value (GR) to be collectively applied to the G subpixels of the right half (BLOLK2). "B1_1_OFFSET" is one B compensation value to be collectively applied to B subpixels. Each of the compensation values may be added to the weight set in the lookup table, but is not limited thereto.

FIG. 23 is a diagram illustrating an example of applying the compensation value of the 8x4 pixel block shown in FIG. 16 to pixel data.

23, "R8x4" is pixel data (R data) of an input image to be written to 8x4 R subpixels, and G8x4 "is pixel data (G data) of an input image to be written to 8x4 G subpixels. (B data) of the input image to be written to 8x4 B subpixels "R1_1_OFFSET" is one R compensation value to be collectively applied to R subpixels. "G1_1_OFFSET" B1_1_OFFSET "is a single B compensation value to be collectively applied to the B subpixels. Each of the compensation values may be weighted in the lookup table, but is not limited thereto.

In Fig. 22 and Fig. 23, "Red Gray Output" is compensation applied R data written to R subpixels in the pixel block by adding R compensation value (R1_1_OFFSET). "Green Gray Output" is compensation applied G data added to G subpixels in a pixel block by adding G compensation values (GL1_1_OFFSET, GR1_1_OFFSET). "Blue Gray Output" is compensation applied B data written to B subpixels in the pixel block by adding the B compensation value (B1_1_OFFSET).

The arithmetic unit 321 adjusts the result of the operation of the pixel data that overflows and underflows during the data operation as shown in Fig.

Referring to FIG. 24, when the compensation value is added to the pixel data, if there is data having a maximum value of 255 or more in the calculation result (S241, S242), the data is adjusted to 255 and the gray gap In the overflow calculation process, the other pixel data is adjusted by adding the 255-maximum value to each of the pixel data other than the maximum value (S243). In Fig. 24, "flash data" is a compensation value per pixel block. "LUT data" is a weight value.

As an example, as a result of adding the compensation value OFFSET = 10 to 4x1 input R data 246, 252, 249, and 250 in the pixel block, (246, 252, 249, ), The gradation difference between the pixel data is lost, and the original gray gap of the input image can not be expressed. In this case, in the overflow calculation process (S243), the operation unit 32 adds +3 to the maximum value 252 of the input R data 246, 252, 249, and 250 to adjust it to 255, (249, 255, 252, 253) to express the gradation difference of the input image. In the overflow calculation process, a calculation value of 0 or less is processed as 0 (S244, S245).

When the compensation value is added to the pixel data, if there is data having a minimum value of 0 or less in the calculation result (S246, S247), the data is adjusted to "0", and the gray gap between the pixel data In step S248, the CPU 201 adjusts the other pixel data as a result of adding the minimum value to each of the pixel data other than the minimum value in the underflow calculation process.

As an example, since (9, 5, 7, 4) is obtained as (0, 0, 0, 0) as a result of adding -10 to 4x1 input R data 9, 5, 7, The gradation difference between the pixel data is lost and the gradation difference of the input image can not be expressed. In this case, in the underflow calculation process (S248), the operation unit 32 adds -3 to the minimum value 4 and adjusts it to 0 in the input R data 9, 5, 7 and 4, (5, 1, 3, 0) to express the gradation difference of the input image.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 20: Driver IC
21: timing control section 22: data driving section
30: first memory (flash memory) 31: second memory (SRAM)
32: compensation section 33: register
81: picture quality enhancement unit 82: real / penta conversion unit

Claims (30)

A first memory storing a plurality of compensation values for each pixel block set in units of pixel blocks including M x N (M and N are each a positive integer of 2 or more) pixels;
A second memory for receiving the plurality of compensation values for each pixel block from the first memory;
A compensation unit for adding the compensation value for each pixel block to the pixel data of the input image to modulate the pixel data; And
And a data driver for converting the compensated pixel data received from the compensator into a data voltage,
Wherein the compensation value for each pixel block comprises a compensation value applied in batch to each pixel in the pixel block in at least one color,
Wherein the pixel data and the compensation value for each pixel block are added between data of the same color. The method according to claim 1,
Wherein the compensation value for each pixel block compensates for the smear obtained through image shooting of the display panel. The method according to claim 1,
The pixel block
At least one first penta-pixel including a subpixel of a first color and a subpixel of a second color; And
And at least one second penta pixel including a subpixel of a third color and a subpixel of the second color. The method according to claim 1,
The pixel block
At least one first real color pixel comprising a subpixel of a first color, a subpixel of a second color, and a subpixel of a third color; And
And at least one second real color pixel including a subpixel of the first color, a subpixel of the second color, and a subpixel of the fourth color. The method according to claim 3 or 4,
The pixel block
Real-time compensation circuit with 8 x 4 pixels. The method according to claim 1,
Wherein the compensating unit is also applied to a display panel including the penta-pixels and a display panel including the real color pixels according to a register setting value. The method according to claim 6,
The first real pixel data including the data of the first color, the data of the second color, and the data of the third color is converted into the first penta pixel data including the data of the first color and the data of the second color ,
The second real pixel data including the data of the first color, the data of the second color, and the data of the third color is divided into the third color data and the second penta-pixel data And a real / penta converter for converting the real-
Wherein the compensation unit adds the compensation value for each pixel block to the pixel data of the input image received from the real / penta converter. The method according to claim 3 or 4,
The compensation value for each pixel block is
A first compensation value collectively applied to the subpixels of the first color;
A second compensation value collectively applied to the subpixels of the second color; And
And a third compensation value applied collectively to the subpixels of the third color. The method of claim 3,
The pixel block
A left half sub-block including the first and second penta-pixels located in the left half of the pixel block; And
And a right half sub-block including the first and second penta pixels positioned on the right half of the pixel block. 10. The method of claim 9,
The compensation value for each pixel block is
A first compensation value collectively applied to the subpixels of the first color;
A 2-1 compensation value collectively applied to the subpixels of the second color existing in the left half subblock;
A 2-2 compensation value collectively applied to the subpixels of the second color existing in the right half subblock; And
And a third compensation value applied collectively to the subpixels of the third color. 11. The method of claim 10,
Wherein the first compensation value, the second compensation value, the second compensation value, and the third compensation value are 8-bit data. 11. The method of claim 10,
The pixel block
8 x 4 pixels,
Wherein the left half pixel block and the right half pixel block each comprise 4 x 4 penta pixels. The method according to claim 1,
In a pixel array of a display panel having a resolution of X x Y (where X is greater than M and Y is a positive integer greater than N)
Wherein the data size stored in the first memory is (X / M) x (Y / N) x compensation value data size + checksum data size. 14. The method of claim 13,
In the pixel array of the display panel having the X x Y resolution,
Wherein the data size stored in the second memory is (X / M) x (Y / N) x compensation value data size. The method according to claim 1,
Wherein the compensation value for each pixel block is applied to the pixel data only for pixels that are on among all the pixels of the display panel when the display panel operates in the partial mode. The method according to claim 1,
The compensation unit
And adding a result of weighting the compensation value to pixel data of the input image. 17. The method of claim 16,
The compensation unit
Up table in which weights are individually set according to a luminance value received from a host system and pixel data of the input image. The method according to claim 1,
Wherein the compensation unit comprises:
Adding a result of weighting the compensation value to pixel data of the input image,
Wherein a relatively large weight is added to the compensation value when the display panel is driven in a high brightness mode (HBM) mode. The method according to claim 1,
Wherein the first memory includes a flash memory,
And the second memory includes a static random access memory (SRAM). A memory for storing a plurality of compensation values for each pixel block set in pixel block units including M x N (M and N are each a positive integer of 2 or more) pixels;
A compensation unit for adding the compensation value for each pixel block to the pixel data of the input image to modulate the pixel data; And
And a data driver for converting the compensated pixel data received from the compensator into a data voltage,
Wherein the pixel data and the compensation value for each pixel block are added between data of the same color. A display panel on which data lines, gate lines intersecting with the data lines, and pixels are arranged;
A first memory storing a plurality of compensation values for each pixel block set in units of pixel blocks including M x N (M and N are each a positive integer of 2 or more) pixels; And
A driver IC for generating compensated pixel data by adding the compensation value for each pixel block read from the first memory to the pixel data of the input image and for converting the compensated pixel data to a data voltage and applying the compensated pixel data to the data lines Respectively,
Wherein the compensation value for each pixel block comprises a compensation value applied in batch to each pixel in the pixel block in at least one color,
Wherein the pixel data and the compensation value for each pixel block are added between data of the same color. 22. The method of claim 21,
Wherein the drive IC includes:
The second memory loaded with the compensation value for each pixel block from the first memory;
A compensation unit for adding the compensation value for each pixel block to the pixel data of the input image to modulate the pixel data and outputting the compensated pixel data; And
And a data driver for converting the compensated pixel data received from the compensator into a data voltage. 22. The method of claim 21,
When the resolution of the display panel is X x Y (where X is greater than M and Y is a positive integer greater than N)
Wherein the data size stored in the first memory is (X / M) x (Y / N) x compensation value data size + checksum data size. 22. The method of claim 21,
When the resolution of the display panel is X x Y (where X is greater than M and Y is a positive integer greater than N)
Wherein the data size stored in the second memory is (X / M) x (Y / N) x compensation value data size. 22. The method of claim 21,
Wherein the compensation value for each pixel block is applied to the pixel data only for pixels that are on among all the pixels of the display panel when the display panel operates in the partial mode. 22. The method of claim 21,
The compensation unit
And adds a result of weighting the compensation value to pixel data of the input image. 27. The method of claim 26,
The compensation unit
And one or more lookup tables in which weights are individually set according to a luminance value received from the host system and pixel data of the input image. 22. The method of claim 21,
Wherein the compensation unit comprises:
Adding a result of weighting the compensation value to pixel data of the input image,
Wherein when the display panel is driven in a high brightness mode (HBM) mode, a relatively large weight value is added to the compensation value. 22. The method of claim 21,
Wherein the first memory includes a flash memory,
And the second memory includes an SRAM (Static RAM). 22. The method of claim 21,
Wherein each of the pixels includes a compensation circuit for sampling a threshold voltage of a driving element for driving the light emitting element to add a threshold voltage to a data voltage of the pixel data.

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