KR20180042754A - Display Device - Google Patents

Abstract

A display device according to the present invention includes a pixel array in which data lines and gate lines are defined, pixels are arranged in a matrix form, and a shift register which sequentially supplies gate pulses to the gate lines using the stages to which the pixels are connected, . At least one of the stages includes a pull-up transistor that charges the output terminal in response to the voltage of the Q node, a pull-down transistor that discharges the output terminal to the first low potential voltage in response to the voltage of the QB node, And a first Q node discharge control transistor for discharging the QB node to a third low potential voltage in response to a first reset signal applied during a vertical blank period, And a control transistor. The second low potential voltage is set to be lower than the first low potential and higher than the third low potential.

Description

[0001]

The present invention relates to a display device.

The display device is arranged such that the data lines and the gate lines are orthogonal and the pixels are arranged in a matrix form. Video data voltages to be displayed are supplied to the data lines and gate pulses are sequentially supplied to the gate lines. The video data voltage is supplied to the pixels of the display line to which the gate pulse is supplied and all of the display lines are sequentially scanned by the gate pulse to display the video data.

The gate driver for supplying the gate pulse to the gate lines of the display device usually includes a plurality of gate integrated circuits (hereinafter referred to as "IC"). Since each of the gate drive ICs must sequentially output gate pulses, it basically includes a shift register and may include circuits and output buffers for adjusting the output voltage of the shift register depending on the driving characteristics of the display panel.

A gate driver for generating a gate pulse, which is a scan signal in a display device, may be implemented as a gate-in-panel (GIP) type in which a combination of thin film transistors is formed in a bezel region which is a non-display region in a display panel. The GIP type gate driver includes a stage corresponding to the number of gate lines, and each stage outputs a gate pulse to the corresponding gate line on a one-to-one basis.

The transistors of the stages may be shifted in characteristic curves by deterioration. The transistors with severe deterioration phenomenon are not operated properly, which causes a problem that the output of the gate pulse becomes unstable.

The present invention is intended to provide a display device capable of improving the deterioration phenomenon of transistors disposed in a shift register.

The display device according to the present invention has a pixel array in which data lines and gate lines are defined, pixels are arranged in a matrix form, and a gate pulse is applied to the gate lines using subordinate connected stages And a shift register for sequentially supplying the data. At least one of the stages includes a pull-up transistor that charges the output terminal in response to the voltage of the Q node, a pull-down transistor that discharges the output terminal to the first low potential voltage in response to the voltage of the QB node, And a first Q node discharge control transistor for discharging the QB node to a third low potential voltage in response to a first reset signal applied during a vertical blank period, And a control transistor. The second low potential voltage is set to be lower than the first low potential and higher than the third low potential.

The present invention keeps the " Vgs " value of a number of transistors where a deterioration phenomenon can occur to be a negative bias during the vertical blanking period. As a result, the threshold voltage of the transistors can be prevented from being shifted by the deterioration. In particular, the present invention can apply first to third low potential voltages having different voltage levels to the stage so that the " Vgs " value of the plurality of transistors becomes a negative bias.

1 is a view showing a display device according to the present invention.
2 is a diagram showing a shift register according to the present invention.
3 is a view showing the stage shown in Fig.
4 is a timing chart showing the input and output of the shift register.
5 is a diagram for explaining a frame period.
Figures 6 to 8 illustrate voltages applied to each electrode of the main transistors during a vertical blanking period.
9 is a diagram showing a voltage change of a Q node and a QB node of a stage;
10 is a view for explaining a threshold voltage shift phenomenon caused by a deterioration phenomenon of a transistor;

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

In the gate driving circuit of the present invention, the switching elements may be implemented as n-type or p-type metal oxide semiconductor field effect transistor (MOSFET) transistors. Although n-type transistors are exemplified in the following embodiments, it should be noted that the present invention is not limited thereto. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the transistor, the carriers begin to flow from the source. The drain is an electrode from which the carrier exits from the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, the current flows from the source to the drain because the holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed depending on the applied voltage. In the following embodiments, the invention should not be limited to the source and drain of the transistor.

In addition, the turn-on voltage in this specification refers to the operating voltage of the transistor. Since the present specification describes an n-type transistor as an embodiment, the high-potential voltage is defined as a turn-on voltage.

1 is a view showing a display device according to an embodiment of the present invention. Referring to FIG. 1, a display device of the present invention includes a display panel 100, a timing controller 110, a data driver 120, and gate drivers 130 and 140.

The display panel 100 includes a pixel array 100A in which data lines DL and gate lines GL are defined and pixels are arranged, a non-display region 100A in which various signal lines, pads, etc. are formed outside the pixel array 100A, (100B). The display panel 100 may be a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electrophoretic display (EPD), or the like.

The timing controller 110 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock DLCK through an LVDS or TMDS interface receiving circuit connected to an image board, . The timing controller 110 includes a data timing control signal DDC for controlling the operation timing of the data driver 120 and a gate timing control signal DDC for controlling the operation timing of the scan drivers 130 and 140 based on the input timing signal GDC).

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP controls the shift start timing of the data driver 120. The source sampling clock SSC is a clock signal for controlling the sampling timing of data in the data driver 120 based on the rising or falling edge.

The scan timing control signal includes a start pulse VST, a gate clock CLK, and the like. The start pulse VST is input to the shift register 140 to control the shift start timing. The gate clock CLK is level-shifted through the level shifter 130 and then input to the shift register 140.

The data driver 120 receives the digital video data RGB and the source timing control signal DDC from the timing controller 110. The data driver 120 converts the digital video data RGB to a gamma voltage in response to the source timing control signal DDC to generate a data voltage and supplies the data voltage to the data lines DL of the display panel 100. [ Lt; / RTI >

The gate drivers 130 and 140 include a level shifter 130 and a shift register 140.

The level shifter 130 is formed on the printed circuit board 105 connected to the display panel 100 in the form of an IC. The level shifter 130 level-shifts the clock signals (CLK) and the start signal (VST) by the control of the timing controller 110, and then supplies the level shift signals to the shift register 140.

2 is a diagram showing a shift register according to the present invention.

Referring to FIG. 2, the shift register 140 sequentially outputs gate pulses Gout corresponding to the gate clocks CLK and the start pulse VST. The shift register 140 includes a plurality of stages STG connected to each other. Although FIG. 2 shows the shift register 140 composed of n stages STG corresponding to n gate lines, the number of stages STG is not limited to this. For example, the stage may include a dummy stage for generating a carry signal or a downstream signal NEXT. In the following description, the term "front stage" means that the stage is located at the upper portion of the reference stage. For example, the front stage may be any one of the first stage STG1 to the i-1 stage STG (i-1) on the basis of the i-th stage STGi (i is a natural number larger than 5 and smaller than n) . Quot; rear stage "refers to a stage located at the bottom of the reference stage. For example, with respect to the i-th stage (1 <i <n) stage STGi, the trailing stage indicates either the i + 1 stage STG (i + 1) to the n-th stage.

Each stage STG of the shift register 140 sequentially outputs the gate pulses Gout [1] to Gout [n]. For example, the i-th stage STGi outputs the i-th gate pulse Gouti, and the n-th stage STGn outputs the n-th gate pulse Gout [n]. To this end, each stage STG receives one gate clock among sequentially sequentially delayed gate clocks CLK.

The [i-4] th gate pulse Gout [i-4] is applied to the [i-4] th gate line and also serves as a carry signal transmitted to the i th stage STGi. The [i + 4] gate pulse Gout [i + 4] is applied to the [i + 4] gate line and also serves as a next stage signal NEXT applied to the i-th stage STGi. The carry signal and the next stage signal NEXT shown in FIG. 2 are applied to the embodiment in which the phase of the gate clock signal CLK is 8 and the gate pulse Gout is output during 4 horizontal periods H, (NEXT) may vary depending on the phase of the gate clock.

Each of the stages STG receives a driving signal through signal lines. In particular, the stages STG are connected to the signal lines for receiving the first to third low potential voltages VGL1, VGL2, and VGL3. The voltage levels of the first to third low potential voltages VGL1, VGL2 and VGL3 are set so as to satisfy the condition of "VGL1> VGL2> VGL3".

FIG. 3 is a diagram showing the configuration of the stage shown in FIG. 2, and FIG. 4 is a diagram showing the timing and output signal of a driving signal input to the stage shown in FIG.

1 to 4, the ith stage STGi of the shift register 140 includes a pull-up transistor Tpu, a pull-down transistor Tpd, a start controller T1, And a plurality of transistors.

The pull-up transistor Tpu includes a gate electrode connected to the Q node, a drain electrode connected to the gate clock (CLK) input terminal, and a source electrode connected to the output terminal Nout.

The pull-down transistor Tpd includes a gate electrode connected to the QB node, a drain electrode connected to the output node Nout, and a source electrode connected to the gate low voltage input.

The start control unit T1 may include a transistor including a gate electrode and a drain electrode connected to the start pulse input terminal VST_P and a source electrode connected to the Q node. The start pulse input terminal VST_P receives any one of the first to fourth start pulses VST1 to VST4 or a carry signal. The start pulse input terminals VST_P of the first to fourth stages STG1 to STG4 receive the first to fourth start pulses VST1 to VST4 respectively and are connected to the start input terminal VST_P of the i- [I-4] gate pulse Gout [i-4] which is a carry signal.

The second transistor T2 includes a gate electrode connected to the second reset signal DRST input line, a drain electrode connected to the high voltage VDD input line, and a source electrode connected to the QB node. The second transistor T2 charges the QB node in response to the second reset signal DRST.

The third transistor T3 includes a gate electrode receiving a gate clock bar signal, a drain electrode connected to a high potential voltage (VDD) input terminal, and a source electrode connected to the QA node. The gate clock bar signal means a gate clock which is opposite in phase to the gate clock applied to the drain electrode of the pull-up transistor Tpu. For example, in the shift register using the 8-phase gate clock, the gate clock bar signal of the i-th stage STGi refers to the [i-4] gate clock CLK [i-4]. The third transistor T3 charges the QA node in response to the [i-4] gate clock CLK [i-4].

The fourth transistor T4 includes a gate electrode coupled to the QA node, a drain electrode coupled to the high voltage (VDD) input line, and a source electrode coupled to the QB node. The fourth transistor T4 charges the QB node when the QA node is charged.

The fifth transistor T5 includes a gate electrode connected to the Q node, a drain electrode connected to the QA node, and a source electrode connected to the third low potential voltage (VGL3) input line. The fifth transistor T5 forms a current path between the QA node and the third low potential voltage (VGL3) input line when the Q node is charged.

The sixth transistor T6 includes a gate electrode connected to the first reset signal BRST input line, a drain electrode connected to the QA node, and a source electrode connected to the third low potential voltage VGL3 input line. The sixth transistor T6 responds to the first reset signal BRST to discharge the QA node to the second low potential voltage VGL2.

The first Q node control transistor T7 includes a gate electrode coupled to the QB node, a drain electrode coupled to the Q node, and a source electrode coupled to the second low potential voltage (VGL2) input line. The first Q node control transistor T7 discharges the QB node to the second low potential voltage VGL2 when the Q node is charged.

The eighth transistor T8 includes a gate electrode connected to the Q node, a drain electrode connected to the QB node, and a source electrode connected to the second low potential voltage (VGL2) input line. The eighth transistor T8 discharges the Q node to the second low potential voltage VGL2 when the QB node is charged. In this specification, the eighth transistor T8 may be referred to as a second QB node discharge control transistor.

The second Q node control transistor T9 includes a gate electrode connected to the first reset signal BRST input line, a drain electrode connected to the QB node, and a source electrode connected to the second low potential voltage VGL2 input line do. The second Q node control transistor T9, in response to the first reset signal BRST, discharges the QB node to the second low potential voltage VGL2.

The output stage control transistor T10 includes a gate electrode connected to the first reset signal input line BRST_L, a drain electrode connected to the output node Nout, and a source electrode connected to the first low potential voltage VGL1 input line . The output stage control transistor T10 discharges the output node Nout to the first low potential voltage VGL1 in response to the first reset signal BRST.

The third Q node discharge control transistor T11 includes a gate electrode connected to the rear stage signal input NEXT_P, a drain electrode connected to the Q node, and a source electrode connected to the second low potential voltage (VGL2) input line. The third Q node discharge control transistor T11 discharges the voltage of the Q node to the second low potential voltage VGL2 in response to the subsequent stage signal NEXT.

The QB node control transistor T12 includes a gate electrode receiving the first reset signal BRST, a drain electrode connected to the QB node, and a source electrode connected to the third low potential voltage (VGL3) input line. The QB node control transistor T12 responds to the first reset signal BRST to discharge the output node Nout to the third low potential voltage VGL3.

The operation of the stages during one frame is as follows. The frame period is divided into an active period (AT) and a vertical blank period (VB). The active period AT and the vertical blank period VB can be defined based on the Video Electronic Standards Association (VESA) standard, as shown in Fig.

The active period AT is a period of time required to display one frame of data in all the pixels of the display area 100A in which the image is displayed on the display panel 100. [

The vertical blank period VB includes a vertical sync time VS, a vertical front porch FP, and a vertical back porch BP. The vertical sync time (VS) is the time from the polling edge to the rising edge of Vsync, indicating the start (or end) timing of one screen. The vertical front porch FP is a time from the polling edge of the last DE indicating the last line data timing of one frame data to the start of the vertical blank time VB. The vertical back porch BP is the time from the end of the vertical blank time VB to the rising edge of the first DE indicating the first line data timing of one frame of data.

The second reset signal DRST is applied to each stage STG in the initial period of the k-th (k is a natural number) frame. The second transistor T2 charges the QB node in response to the second reset signal DRST and the first Q node control transistor T7 discharges the Q node in response to the second reset signal DRST.

After the second reset signal DRST is completed, the first to fourth start signals VST1, VST2, VST3 and VST4 are applied to the first to fourth stages STG, respectively.

The start control unit T1 of the first to fourth stages pre-charges the Q node in response to the start pulse VST.

When the gate clock CLK is input to the drain electrode of the pull-up transistor Tpu in the state where the Q node is precharged, the Q node is bootstrapped as the drain electrode voltage of the pull-up transistor Tpu rises. As the Q node is bootstrapped, the potential difference between the gate and the source of the pull-up transistor Tpu becomes large, and eventually the pull-up transistor Tpu is turned on when the voltage difference between the gate and the source reaches the threshold voltage. The turn-on pull-up transistor Tpu charges the output node Nout using the gate clock CLK. The output terminal Nout of the i-th stage STGi is connected to the i-th gate line GLi and the gate pulse Gouti is applied to the i-th gate line GLi.

After the gate clock CLK is inverted to the low level, the gate electrode of the third Q node discharge control transistor T11 receives the subsequent signal NEXT. The third Q node discharge control transistor T11 is turned on in response to the subsequent stage signal NEXT, thereby discharging the voltage of the Q node to the second low potential voltage VGL2.

In the active period, the third transistor T3 charges the QA node in response to the [i-4] gate clock CLK [i-4]. That is, the QA node maintains the high-potential voltage (VDD) during a period in which the i-th gate clock CLKi is not input. The fourth transistor T4 charges the QB node in response to the QA node. The i-th gate clock CLKi refers to the gate clock CLK applied to the drain electrode of the pull-up transistor Tpu to determine the output timing of the gate pulse output by the i-th stage STGi.

The fifth transistor T5 suppresses the fourth transistor T4 from operating in a period in which the Q node is charged. That is, the fifth transistor T5 discharges the QA node to the third low potential VGL3 while the start pulse VST and the i-th gate clock CLKi are input, so that the fourth transistor T4 operates .

During the vertical blank period VB after the active period AT ends, the first reset signal BRST is applied to each of the stages STG.

The sixth transistor T6 discharges the QA node in response to the first reset signal BRST. As a result, the fourth transistor T4 maintains the turn-off state. Since the fourth transistor T4 is turned on for a long time during the active period AT, the fourth transistor T4 is subjected to a great stress. The fourth transistor T4 may not operate during the vertical blank period VB so that the sixth transistor T6 discharges the QA node during the vertical blank period VB to prevent the fourth transistor T4 from operating do.

The second Q node control transistor T9, the output stage control transistor T10 and the QB node control transistor T12 are turned on in response to the first reset signal BRST. The second Q node control transistor T9 is turned on to discharge the Q node to the second low potential voltage VGL2. The output stage control transistor T10 is turned on to discharge the output terminal Nout to the first low potential voltage VGL1. The first QB node control transistor T12 is turned on to discharge the QB node to the third low potential voltage VGL3.

As described above, the first reset signal BRST applied during the vertical blank period VB turns on the second Q-node control transistor T9, the output stage control transistor T10 and the QB node control transistor T12 . In particular, the second Q-node transistor T9, the output stage control transistor T10 and the QB node control transistor T12 discharge the Q node, the output node Nout and the QB node to different low potential voltages, respectively. In other words, during the vertical blank period VB, the Q node, the output node Nout and the QB node are supplied with low potential voltages of different voltage levels.

As a result, the voltage levels of the respective electrodes of the first Q node control transistor T7, the pull-up transistor Tpu and the pull-down transistor Tpd during the vertical blanking period VB become the states shown in FIGS.

6, during the vertical blanking period VB, the gate electrode of the first Q node control transistor T7 is at the voltage level of the third low potential voltage VGL3, and the source and drain electrodes are connected to the second low- And becomes the voltage level of the potential voltage VGL2. As a result, &quot; Vgs &quot; of the first Q node control transistor T7 becomes a value obtained by subtracting the second low potential voltage VGL2 from the third low potential VGL3. Since the third low potential voltage VGL3 is at a voltage level lower than the second low potential voltage VGL2, "Vgs" of the first Q node control transistor T7 becomes a negative bias smaller than zero.

7, during the vertical blank period VB, the gate electrode of the pull-down transistor Tpd becomes the voltage level of the third low potential voltage VGL3, and the source electrode and the drain electrode thereof are at the first low potential voltage VGL1 ). As a result, "Vgs" of the pull-down transistor Tpd becomes a value obtained by subtracting the first low potential VGL1 from the third low potential VGL3. Since the third low potential voltage VGL3 is at a voltage level lower than the first low potential voltage VGL1, "Vgs" of the pull-down transistor Tpd becomes a negative bias smaller than zero.

8, during the vertical blank period VB, the gate electrode of the pull-up transistor Tpu is at the voltage level of the second low potential voltage VGL2, and the source and drain electrodes are at the first low potential voltage VGL1 ). As a result, &quot; Vgs &quot; of the pull-up transistor Tpu becomes a value obtained by subtracting the first low potential voltage VGL1 from the second low potential voltage VGL2. Since the second low potential voltage VGL2 is at a voltage level lower than the first low potential voltage VGL1, "Vgs" of the pull-up transistor Tpu becomes a negative bias smaller than zero.

As a result, during the vertical blank period VB, the first Q node control transistor T7, the pull-up transistor Tpu and the pull-down transistor Tpd are all at low potential.

In the active period (AT), the QB node maintains a high potential voltage except for a period in which the Q node is precharged or bootstrapped, as shown in FIG. As a result, since the first Q node control transistor T7 and the pull-down transistor Tpd whose gate electrode is connected to the QB node maintain a turn-on state for a long time during the active period AT, a threshold voltage deviation due to deterioration A phenomenon of shifting occurs.

10 is a view for explaining a phenomenon in which the voltage-current characteristic curve of transistors is shifted by deterioration.

10, the voltage-current characteristic curve of the first Q-node control transistor T7 and the pull-down transistor Tpd having the form of the first graph gr1 is shifted to the second graph gr2 by the deterioration . As a result, a phenomenon occurs in which the gate-source voltage of the first Q node control transistor T7 and pull-down transistor Tpd is not turned on even though it is applied at the voltage level of the initially set threshold voltage Vth. Therefore, since the first Q node control transistor T7 and the pull-down transistor Tpd are not operated properly, a gate pulse may be outputted in an undesired period.

The stages of the shift register according to the present invention apply different low potential voltages to the QB node and the Q node during the vertical blank period VB so that the &quot; Vgs &quot; value of the first Q node control transistor T7 and pull down transistor Tpd All of them can be made negative bias. Since the low potential voltage different from the QB node and Q is also applied to the output node Nout during the vertical blank period VB, "Vgs" of the pull-up transistor Tpu also becomes a negative bias.

As described above, the present invention applies a low-potential voltage level of a different voltage level to the main node during the vertical blank period, and applies a negative bias to the first Q node control transistor T7, the pull-up transistor Tpu and the pull- . As a result, the deterioration phenomenon of the first Q node control transistor T7, the pull-up transistor Tpu and the pull-down transistor Tpd can be improved.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the appended claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

100: display panel 110: timing controller
120: Data driver 130, 140: Gate driver

Claims (8)

A pixel array in which data lines and gate lines are defined, and pixels are arranged in a matrix form; And
And a shift register for sequentially supplying gate pulses to the gate lines by using stages connected in a dependent manner,
At least one of the stages
A pull-up transistor that charges the output terminal in response to the voltage of the Q node;
A pull-down transistor responsive to a voltage of the QB node for discharging the output terminal to a first low potential voltage;
A first Q node discharge control transistor responsive to a voltage of the QB node for discharging the voltage of the Q node to a second low potential voltage; And
And a first QB node discharge control transistor responsive to a first reset signal applied during a vertical blank period to discharge the QB node to a third low potential voltage,
And the second low potential voltage is lower than the first low potential voltage and higher than the third low potential voltage. The method according to claim 1,
Wherein the first reset signal maintains a turn-off voltage during an active period of writing image data to the pixel array. The method according to claim 1,
At least one of the stages
And a second Q node discharge control transistor including a gate electrode receiving the first reset signal, a drain electrode connected to the Q node, and a source electrode receiving the second low potential voltage. The method according to claim 1,
At least one of the stages
And an output terminal discharge control transistor including a gate electrode to which the first reset signal is applied, a drain electrode connected to the output terminal, and a source electrode to which the third low potential voltage is applied. The method according to claim 1,
The stage for outputting the i-th (i is a natural number) gate pulse is
A start controller for precharging the Q node in response to a start pulse or a gate pulse other than the i-th gate pulse; And
And a third Q node discharge control transistor for discharging the Q node to the second low potential voltage in response to a last stage signal applied at the end of the i &lt; th &gt; gate pulse. The method according to claim 1,
And a second QB node discharge control transistor including a gate electrode connected to the Q node, a drain electrode connected to the QB node, and a source electrode to which the second low potential voltage is applied. 5. The method of claim 4,
And the first to third low potential voltages are negative biases. The method according to claim 1,
The pull-up transistor charges the output terminal using a gate clock applied to the drain electrode,
Wherein the gate clock maintains the second low potential voltage during the active period and maintains the first low potential voltage during the vertical blank period.

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