KR20180036400A - Shift register and display device using the same - Google Patents

Abstract

The present invention relates to a shift register capable of reducing power consumption while multiple output defects of the shift register can be prevented by rapidly removing a ripple of a control node. According to an embodiment of the present invention, in the shift register, a QB node control part of each stage comprises: a QB switching part charging a QB node; and a QB voltage adjusting part adjusting at least one voltage supplied to the QB switching part according to a resistance ratio of a first adjustment TFT and a second adjustment TFT, and automatically compensating for voltage of the QB node according as a stress is applied to the QB node.

Description

[0001] SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a shift register capable of preventing multiple output defects and reducing power consumption, and a display using the shift register.

2. Description of the Related Art [0002] Flat panel display devices that have recently become popular as display devices include liquid crystal displays (LCDs) using liquid crystals, OLED display devices using organic light emitting diodes (OLEDs) Display devices (ElectroPhoretic Display; EPD), and the like.

A flat panel display device includes a display panel for displaying an image of a pixel array in which each pixel is independently driven by a thin film transistor (TFT), a panel driver for driving the display panel, a timing controller for controlling the panel driver . The panel driver includes a gate driver for driving the gate lines of the display panel, and a data driver for driving the data lines of the display panel.

The gate driver includes a shift register composed of stages for separately driving gate lines of the display panel, and each stage is composed of a plurality of TFTs. Recently, the gate driver is formed together with the TFT array of the pixel array to mainly use a gate-in-panel (GIP) method built in the display panel.

In each stage, the pull-down TFT operates during most of the pull-down periods except for the pull-up period during which the pull-up TFT is driven for each frame, and outputs the gate low voltage. To this end, a high voltage is applied to the QB node controlling the pull-down TFT during the pull-down period, so that a positive bias stress (PBTS) accumulates. As a result, the pull-down TFT has a weak point that the threshold voltage is shifted in the positive direction by the accumulated PBTS with deterioration of the drive time.

In order to reduce the PBTS of the pull-down TFT, a method of applying an AC signal to the QB node is applied, but the AC signal increases the power consumption and coupling by the AC signal occurs to remove the ripple generated at the Q- And it is disadvantageous that additional TFTs for ripple removal are required.

The ripple of the Q node is generated by the coupling of the parasitic capacitors every time the clock applied to the pull-up TFT during the pull-down period transitions, and thus the pull-up TFT is abnormally driven to cause multiple output failure.

The present invention provides a shift register capable of rapidly removing a ripple of a control node and preventing a multi-output failure of a shift register while reducing power consumption, and a display device using the shift register.

In the shift register according to the embodiment of the present invention, each stage is controlled by a set terminal to set up a Q node; A reset unit controlled by the reset terminal to discharge the Q node; A pull-up unit controlled by the Q node to output a corresponding clock supplied to a clock terminal among a plurality of clocks; A pull down unit controlled by the QB node to output a low voltage; A QB node control unit for controlling a QB node; And a noise removing unit controlled by the QB node to discharge the Q node.

The QB node control unit may include a QB switching unit for charging the QB node during a second period different from the first period in which the set unit charges the Q node; And a QB voltage adjusting unit for adjusting at least any one voltage supplied to the QB switching unit according to the resistance ratio between the first adjusting TFT and the second adjusting TFT and automatically compensating the voltage of the QB node as the stress is applied to the QB node .

A QB switching unit according to an embodiment includes a QB switch controlled by a reset terminal to connect a QB input node and a QB node. The QB voltage regulator according to an exemplary embodiment includes a first regulating TFT controlled by a reset terminal to supply an input voltage to a QB input node and a second regulating TFT controlled by a QB node to output a QB input node to a terminal to which a second gate- And a second adjusting TFT for connecting the TFTs. The voltage of the QB input node and the voltage of the QB node automatically increases as the resistance component of the second adjusting TFT increases due to the positive stress applied to the QB node.

The QB switching unit according to an embodiment includes a first QB switch controlled by the control node to connect the QB input node and the QB node. The QB voltage regulator according to an embodiment includes a first regulating TFT controlled by a reset terminal to supply an input voltage to a control node, and a control node controlled by the QB node to connect the control node to a terminal to which a second gate- And a second control TFT. The QB controller according to an exemplary embodiment further includes a QB voltage generator for generating a voltage of a QB input node using an input voltage. As the resistance component of the second control TFT increases due to the positive stress applied to the QB node, the voltage of the control node and the QB node automatically rise.

The QB switching unit according to one embodiment further comprises a second QB switch controlled by the set terminal to connect the QB input node and the QB node. The QB voltage generating unit according to an embodiment includes a charging TFT controlled by an input voltage and supplying an input voltage to a QB input node, and a control terminal controlled by a set terminal to connect a QB input node to a terminal to which a second gate- And a discharge TFT.

The QB switching unit according to one embodiment further comprises a second QB switch controlled by the Q node to connect the QB node with a terminal to which a second gate-off voltage is supplied. The QB voltage generator according to an exemplary embodiment includes a charge TFT controlled by an input voltage to supply an input voltage to a QB input node.

The input voltage is supplied with an inverted clock or gate-on voltage having a phase inverted from the clock supplied to the clock terminal.

In the display device according to the embodiment of the present invention, the above-mentioned shift register is embedded in the non-display area of the display panel to individually drive the gate line of the display panel.

The shift register and the display device using the shift register according to the present invention enable the QB node controller to supply the DC voltage to the QB node and quickly remove the ripple of the Q node through the noise eliminator controlled by the QB node, Can be saved.

The shift register and the display device using the same according to the present invention can compensate the voltage of the QB node to rise automatically according to deterioration of the TFT by using the voltage regulator including the TFT controlled by the QB node together with the pull- have. Therefore, even when the PBTS is accumulated due to the application of the DC voltage of the QB node, the QB node voltage is automatically compensated even when the threshold voltage of the pull-down TFT is shifted, so that the normal operation of the degraded pull-down TFT can be performed. have.

1 is a block diagram showing the structure of a shift register according to an embodiment of the present invention.
2 is a circuit diagram showing the configuration of a stage in a shift register according to an embodiment of the present invention.
3 is a driving waveform diagram of the stage shown in Fig.
4A and 4B are waveform diagrams showing simulation results before and after deterioration of TFTs in one stage according to an embodiment of the present invention.
5 is a circuit diagram showing the configuration of a stage in a shift register according to an embodiment of the present invention.
6 is a circuit diagram showing the configuration of a stage in a shift register according to an embodiment of the present invention.
FIG. 7 is a block diagram schematically showing a configuration of a display device incorporating a shift register according to an embodiment of the present invention. Referring to FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically showing the structure of a shift register according to an embodiment of the present invention.

The shift registers shown in FIG. 1 have a plurality of stages ST1 to STn (n is a number of stages) that are connected to each other and generate a separate scan output Gout. For convenience, the first to fifth stages ST1 to ST5).

Hereinafter, "front stage" means any one of at least one stage located at a previous (upper) position of the stage, and "rear stage" means at least one stage Which means either.

Each of the stages ST1 to STn includes a set terminal S, a reset terminal R, a clock terminal CK, a power supply terminal PT, an output terminal OUT, a carry terminal CR, And the like.

The set terminal S of each stage is supplied with the set signal as the start signal Vst supplied through the start signal line or the preceding carry signal supplied from the carry terminal CR of the front stage. The reset terminal R of each stage ST receives a reset signal supplied from the carry signal supplied from the carry terminal CR of the subsequent stage or a reset signal supplied through the reset signal line.

The clock terminal CK of each stage ST is supplied with any one of a plurality of clock signals such as two-phase, four-phase, six-phase, eight-phase, etc. having different phases. For example, first and second clock signals CLK1 and CLK2 having inverted phases are alternately supplied to the clock terminals CK of the stages ST1 to ST5 as shown in FIG. That is, the first clock signal CLK is supplied to the clock terminals CK of the odd-numbered stages ST1, ST3, and ST5, and the second clock signal CK is supplied to the clock terminals CK of the even- CLK2 may be supplied.

The additional input terminal CT of each stage ST is supplied with a voltage to be supplied to the QB node and is supplied with the inverted clock signal different from the clock supplied to the clock terminal CK of the stage, Can be supplied. The gate high voltage VGH can be expressed as a gate-on voltage with a positive high-potential power supply voltage capable of turning on the TFT.

The output terminal OUT of each stage ST is connected to the gate line of the display panel and outputs a scan output Gout. The carry terminal CR of each stage ST is connected to at least one of the set terminal of the subsequent stage and the reset terminal of the preceding stage and outputs a carry signal.

A plurality of power supply terminals PT of each stage ST are supplied with a gate low voltage VGL, a low potential voltage VSS, and the like supplied through a plurality of power supply lines. The gate-low voltage (VGL) and the low-potential voltage (VSS) can be respectively represented by the first and second gate-off voltages with a low potential voltage of negative polarity capable of turning off the TFT. The low-potential voltage VSS is a second gate-off voltage used for the carry signal, and a gate-low voltage VGL used for the scan output, that is, a voltage lower than the first gate-off voltage is used. Accordingly, the low potential voltage (VSS) of the carry signal at another stage using the carry signal as a control signal such as a set signal or a reset signal can reduce the leakage current by stably turning off the TFT concerned.

Each of the stages ST1 to ST5 is pulled up sequentially in response to the set signal Set supplied to the set terminal S and supplies the corresponding clock signal to the clock terminal CK through the output terminal OUT And outputs it as a scan signal (Gout) and a carry signal (CRY) to another stage through a carry terminal (CR). Each of the stages ST1 to ST5 is sequentially pulled down in response to a reset signal supplied to a reset terminal R so that a gate low voltage VGL is applied to the scan output Gout And outputs the low potential voltage VSS as a low voltage of the carry signal through the carry terminal CR.

FIG. 2 is a circuit diagram showing the configuration of one stage in the shift register according to the embodiment of the present invention shown in FIG. 1, and FIG. 3 is a driving waveform diagram of the stage shown in FIG.

2 includes a set unit 10, a reset unit 20, a pull-up unit 30, a pull-down unit 40, a QB node control unit 80, and a noise removing unit 90.

The TFTs constituting each stage use an amorphous TFT using an amorphous silicon semiconductor layer, a poly TFT using a polysilicon semiconductor layer, or an oxide TFT using a metal oxide semiconductor layer.

The set section 10 sets (charges) the Q node to a high voltage in response to the set signal (Set) of the set terminal S to which the star signal Vst or the preceding carry signal is supplied. The set portion 10 includes at least one set TFT (T1). The set TFT (T1) has a diode structure in which a gate electrode and a drain electrode are connected to a set terminal (S), and a source electrode is connected to the Q node. The set TFT (T1) is turned on when the set signal (Set) is at the high voltage to charge the Q node to the high voltage of the set signal (Set).

The reset unit 20 resets (discharges) the Q node to a low voltage in response to a reset signal Reset of a reset terminal R to which a subsequent carry signal or a reset signal is supplied. The reset section 20 includes at least one reset TFT T2. In the reset TFT T2, a gate electrode is connected to the reset terminal R, a drain electrode is connected to the Q node, and a source electrode is connected to the supply terminal PT2 of the low potential voltage VSS. The reset TFT T2 is turned on by the high voltage of the reset signal Reset to discharge the Q node to the low potential VSS.

Up section 30 is pulled up by the control of the Q node to output the clock signal CLK1 supplied to the clock terminal CK to the output terminal OUT and the carry terminal CR. The pull-up section 30 includes first and second pull-up TFTs Tpu1 and Tpu2. In the first pull-up TFT (Tpu1), a gate electrode is connected to the Q node, a drain electrode is connected to the clock terminal (CK), and a source electrode is connected to the output terminal (OUT). The second pull-up TFT (Tpu2) has a gate electrode connected to the Q node, a drain electrode connected to the clock terminal (CK), and a source electrode connected to the carry terminal (CR). The first pull-up TFT Tpu1 is turned on by the high voltage of the Q node to output the clock signal CLK1 to the scan output Gout (N) through the output terminal OUT, and the second pull-up TFT Tpu2 Is turned on by the high voltage of the Q node to output the clock signal CLK1 to the carry signal CRY (N) via the carry terminal CR.

Down section 40 is pulled down under the control of the QB node so that the gate low voltage VGL and the low potential voltage VSS supplied to the power supply terminals PT1 and PT2 are supplied to the output terminal OUT and the carry terminal CR . The pull-down section 40 includes first and second pull-down TFTs Tpd1 and Tpd2. The first pull-down TFT (Tpd1) has a gate electrode connected to the QB node, a drain electrode connected to the output terminal (OUT), and a source electrode connected to the supply terminal PT1 of the gate low voltage (VGL). The second pull-down TFT (Tpd2) has a gate electrode connected to the QB node, a drain terminal connected to the carry terminal CR, and a source electrode connected to the supply terminal PT2 of the low potential voltage VSS. The first pull-down TFT (Tpd1) is turned on by the high voltage of the QB node to output the gate low voltage (VGL) to the low voltage of the scan output (Gout (N) And is turned on by the high voltage of the node to output the low potential voltage VSS to the low voltage of the carry signal CRY (N).

The QB control unit 80 includes a QB voltage generation unit 50, a QB voltage regulation unit 60, and a QB switch unit 70.

The QB voltage generating unit 50 generates the QB input voltage at the QB input node QB_in using the input voltage supplied through the additional input terminal CT. The QB voltage generating section 50 includes a charging TFT T4H and a discharging TFT T4L. The charging TFT T4H has a diode structure in which a gate electrode and a drain electrode are connected to the additional input terminal CT, and a source electrode is connected to the QB input node QB_in. The discharge TFT T4L has a gate electrode connected to the set terminal S, a drain electrode connected to the QB input node QB_in and a source electrode connected to the supply terminal PT2 of the low potential voltage VSS. The additional input terminal CT is supplied with the inverted clock signal CLK2 or the gate high voltage VGH. The charging TFT T4H is turned on by the inversion clock CLK2 or the gate high voltage VGH to supply the inverted clock CLK2 or the gate high voltage VGH to the QB input node QB_in. The discharge TFT T4L is turned on by the set signal Set to discharge the QB input node QB_in to the low potential voltage VSS when the Q node is charged by the set portion 10. [ When the QB switching unit 70 is turned off, the charging TFT T4L periodically supplies the high logic of the inverted clock signal CLK2 to the QB input node QB_in or supplies the gate high voltage VGH to the QB input node QB_in, The high voltage of the QB node can be prevented from falling through the QB switching unit 70 which is turned off.

The QB voltage regulator 60 regulates the voltage of the control node CN applied to the gate electrode of the first QB switch TS1 of the QB switching unit 70 and controls the voltage of the control node CN CN) is automatically increased. The QB voltage regulator 60 includes a first adjusting TFT T5H and a second adjusting TFT T5L The gate of the first adjusting TFT T5H is connected to the reset terminal R, A drain electrode is connected to the terminal CT and a source electrode is connected to the control node CN. The second adjusting TFT T5L has a gate electrode connected to the QB node, a drain electrode connected to the control node CN And the source electrode is connected to the supply terminal PT2 of the low potential voltage VSS The first adjustment TFT T5H is turned on by the reset signal Reset to generate the inverted clock CLK2 or the gate high voltage The second adjusting TFT T5L is turned on by the high voltage of the QB node to supply the control node CN and the supply terminal PT2 of the low potential voltage VSS to the control node CN Connect.

The voltage of the control node CN that controls the first QB switch TS1 is determined according to the resistance ratio of the first control TFT T5H and the second control TFT T5L. In other words, the gate voltage of the first QB switch TS1 is determined according to the ratio of at least one of the channel sizes of the first control TFT T5H and the second control TFT T5L, that is, the channel length and the channel width. As the channel size of the second adjusting TFT T5L is larger, the voltage of the control node CN decreases. Therefore, when the first adjusting TFT T5H is turned on by the reset signal Reset and the second adjusting TFT T5L is turned on by the QB node, The channel size of the first adjusting TFT T5H is set so that the control node CN can supply the turn-on voltage to the first QB switch TS1 using the inverted clock CLK2 or the gate high voltage VGH. 2 < / RTI > control TFT T5L.

Particularly, the second adjusting TFT T5L receives the PBTS of the QB node which is the same as the pull-down portion 40 and deteriorates at the same speed as the pull-down portion 40, and the resistance component increases as the PBST deteriorates, Thereby raising the voltage. That is, as the threshold voltages of the first and second pull-down TFTs Tpd1 and Tpd2 and the second adjusting TFT T5L shift in the positive direction by the PBTS of the QB node, the resistance component of the second adjusting TFT T5L increases The voltage of the control node CN, that is, the gate voltage of the first QB switch TS1, is automatically increased. As a result, the QB voltage supplied from the QB input node QB_in to the QB node by the rise of the gate voltage of the first QB switch TS1 is also automatically increased to compensate for the pull-down portion 40 ) Can be driven normally, so that the service life can be prolonged.

The QB switching unit 70 switches the connection between the QB input node QB_in and the QB node to supply a high level DC voltage to the QB node during the pull down period and maintains the supplied DC voltage. The QB switching unit 70 includes a first QB switch TS1 and a second QB switch TS2 connected in parallel between a QB input node QB_in and a QB node. When the first control TFT T5L is turned on by the reset signal Reset and the control node CN is at the high voltage, the first QB switch TS1 is turned on and supplied to the QB input node QB_in And supplies the voltage (CLK2 or VGH) to the QB node. The second QB switch TS2 is turned on by the set signal Set to discharge the QB node together with the discharge TFT T4L to the low potential voltage VSS when the set portion 10 charges the Q node .

The noise eliminator 90 eliminates noise such as ripple that is turned on by the control of the QB node and generated at the Q node. The noise eliminator 90 has at least one noise eliminating TFT T3. In the noise eliminating TFT T3, the gate electrode is connected to the QB node, the drain electrode is connected to the Q node, and the source electrode is connected to the supply terminal PT2 of the low potential voltage VSS. The noise removing TFT T3 is turned on during the pull-down period in which the QB node is in the high voltage state to discharge the Q node to the low potential voltage VSS. Accordingly, whenever the clock signal CLK supplied to the pull-up unit 30 during the pull-down period transitions, the ripple generated in the Q-node is rapidly removed by the coupling of the parasitic capacitors, Can be prevented.

The stage shown in FIG. 2 further includes first and second capacitors CB and CQB1, and may further include a third capacitor CQB2.

The first capacitor CB connected between the gate electrode and the source electrode of the first pull-up TFT Tpu1 is turned on when the first pull-up TFT Tpu1 is pulled up to output a high voltage of the clock signal CLK It is possible to reduce the rising time of the scan output Gout (N) by bootstrapping and amplifying the voltage.

The second capacitor CQB1 connected between the QB node and the supply terminal PT2 of the low potential voltage VSS is turned off when the leakage current is generated through the QB switching unit 70 turned off .

The third capacitor CQB2 connected between the QB input node QB_in and the supply terminal PT2 of the low potential voltage VSS is turned on when the inverted clock signal CLK is supplied to the QB input node QB_in, It is possible to prevent the voltage of the QB input node QB_in from fluctuating every time the clock signal CLK transitions. On the other hand, when the gate high voltage VGH is supplied to the QB input node QB_in, the third capacitor CQB2 may be omitted.

The driving process of the stage shown in FIG. 2 will be described with reference to the driving waveform shown in FIG.

Each stage shown in Fig. 2 is driven for each frame with a pull-down period including the first and second periods t1 and t2 shown in Fig. 3, and a third period t3 and thereafter .

During the first period t1 of the pull-up period, the set TFT T1 is turned on by the high voltage of the set signal (Set) to which the previous carry signal or the start signal is supplied to charge the Q node to the high voltage. The pull-up unit 30 is turned on by the charged Q node to output the low voltage of the clock signal CLK1 as the low voltage of the scan output Gout (N) and the carry signal CRY (N). During this first period t1, the discharge TFT T4L and the second QB switch TS2 are turned on by the high voltage of the set signal Set so that the QB node is discharged to the low potential voltage VSS, The portion 40 is turned off.

During the second period t2 of the pull-up period, the set TFT T1 is turned off by the low voltage of the set signal Set so that the Q node is floated in the high voltage state and the turn- The pull-up unit 30 outputs the high voltage of the clock signal CLK1 to the scan output Gout (N) and the carry signal CRY (N) by the high voltage of the clock signal CLK1 output through the pull- N) at a high voltage. During this second period t2, the discharge TFT (T4L) and the second QB switch (TS2) are turned off by the set signal (Set) of the low voltage to cause the QB node to float in the low voltage state.

During the third period t3, which is the pull-down period, the reset TFT T2 is turned on by the high-level voltage of the reset signal Reset supplied with the subsequent carry signal or the reset pulse from the outside to turn the Q node to the low potential VSS The pull-up unit 30 is turned off. During the third period t3, the first control TFT T5H is turned on by the high voltage reset signal to turn the control node CN to the high logic or gate high voltage VGH of the inverted clock CLK2 The first QB switch TS1 is turned on and the QB input node QB_in is supplied with the high logic or gate high voltage VGH of the inverted clock CLK2 through the charging TFT T4H. The turned-on first QB switch TS1 charges the QB node to a high voltage using the inverted clock CLK2 or the gate high voltage VGH. The pull-down unit 40 is turned on by the charged QB node to output the gate low voltage VGL to the low voltage of the scan output Gout (N) and the low voltage VSS to the carry signal CRY N).

During the pull-down period after the third period t3, the set signal (Set) and the reset signal (Reset) maintain the low voltage and therefore the set portion 10, the reset portion 20, the pull- (70) is turned off. Accordingly, the QB node is floated in the high voltage state, so that the pull-down section 40 outputs the gate low voltage VGL to the low voltage of the scan output Gout (N) and the low potential voltage VSS to the carry signal CRY (N)). Even if the QB switching unit 70 is turned off during this pull down period, the charging TFT T4H periodically supplies the high voltage of the inverted clock signal CLK2 to the QB input node QB_in or supplies the gate high voltage VGH to the QB input node QB_in The high voltage of the QB node can be prevented from falling through the QB switching unit 70 turned off.

Further, during the pull-down period in which the QB node is in a high state, the noise eliminating TFT T3 is turned on and the ripple generated in the Q node by the clock signal CLK is quickly removed, .

Also, even if the PBTS accumulates and the pull-down TFTs (Tpd1, Tpd2) deteriorate as the QB node maintains the high state during the pull-down period, the deteriorated second adjusting TFT T5L, through the first QB switch TS1, The pull-down TFTs (Tpd1, Tpd2) whose threshold voltages are shifted in the positive direction by the PBTS can be normally driven, so that the lifetime can be increased.

4A and 4B are waveform diagrams showing simulation results before and after deterioration of TFTs in one stage according to an embodiment of the present invention.

4A and 4B, during a pull-up period in which the Q node sequentially charges the first high voltage and the second high voltage, the pull-up unit 30 outputs the clock to the scan output Gout Output. The pull-down unit 40 outputs the gate-low voltage VGL to the scan output Gout during a pull-down period during which the Q-node is discharged at a low voltage and the QB node is charged and maintained at a high voltage.

4A shows an initial state before the PBTS is accumulated in the QB node, that is, an initial state before the QB node voltage is compensated. The pull-down portion 40 is pulled down by the high logic voltage of about -3 V of the QB node And the gate-low voltage VGL is stably output by the scan output Gout.

4B shows a state in which the PBTS is accumulated in the QB node and the threshold voltages of the pull-down unit 40 and the second adjusting TFT T5L are shifted by 10 V or more in the positive direction to automatically compensate the QB node voltage to about 6.8 V. QB The pull-down unit 40 is pulled down by the high logic voltage of about 6.8 V of the node and stably outputs the gate low voltage VGL to the scan output Gout.

5 is a circuit diagram showing the configuration of a stage in a shift register according to an embodiment of the present invention.

In contrast to the stage shown in Fig. 2, in the stage shown in Fig. 5, the second QB switch TS2a of the QB switching unit 72 of the QB control unit 82 discharges the QB node under the control of the Q node, There is a difference in that the discharge TFT T5L is omitted in the QB voltage generating section 52, and the remaining components are the same, so that the description of the same components as those of FIG. 2 will be omitted.

The QB control unit 82 shown in FIG. 5 includes a QB voltage generation unit 52, a QB voltage regulation unit 60, and a QB switch unit 72. In the QB switching unit 72, the second QB switch TS2a is turned on when the Q node is charged to discharge the QB node to the low potential voltage VSS. Accordingly, the QB voltage generating unit 52 can include only the charging TFT T4H that charges the QB input node QB_in to the inverted clock CLK2 or the gate high voltage VGH, The TFT T4L can be omitted. Therefore, the stage shown in Fig. 5 can simplify the circuit configuration by reducing the number of TFTs as compared with the stage shown in Fig.

6 is a circuit diagram showing the configuration of a stage in a shift register according to an embodiment of the present invention.

6, the stages shown in FIG. 6 are arranged such that the first and second adjustment TFTs T5H and T5L of the QB voltage regulator 64 of the QB control unit 84 are connected to the QB input node QB_in, And the QB switching unit 74 includes only the first QB switch TS1a for switching the voltage of the QB input node QB_in to the QB node by the control of the reset signal Reset, The QB voltage generator 50 and the second QB switch TS2 shown in FIG. 2 are omitted, and the remaining components are the same, so that the description of the same components as those of FIG. 2 will be omitted.

The QB controller 84 shown in FIG. 6 includes a QB voltage regulator 64 and a QB switch 74.

In the QB voltage regulator 64, the first adjusting TFT T5H is turned on by the reset signal Reset to supply the inverted clock CLK2 or the gate high voltage VGH to the QB input node QB_in. The second adjusting TFT T5L is turned on by the QB node to connect the QB input node QB_in and the supply terminal PT2 of the low potential voltage VSS. The voltage applied to the QB input node QB_in is determined according to the resistance ratio between the first control TFT T5H and the second control TFT T5L. The channel size of the first tuning TFT T5H is preferably larger than the channel size of the second tuning TFT T5L. When the first tuning TFT T5H is turned on by the reset signal Reset and the second tuning TFT T5L is turned on by the QB node through the first tuning TFT T5H to the QB input node A high logic voltage is applied to the QB input node QB_in by the inverted clock CLK2 or the gate high voltage VGH supplied to the QB switch QB_in. Then, the QB switch TS1a is turned on by the reset signal Reset - on to charge the QB node with the high voltage of the QB input node (QB_in).

The resistance component of the second adjusting TFT T5L increases as the first and second pull-down TFTs Tpd1 and Tpd2 and the second adjusting TFT T5L are deteriorated by the PBTS, so that the QB connected through the QB switch TS1a The voltages of the input node QB_in and the QB node are automatically increased and compensated. Accordingly, even if the threshold voltage of the pull-down unit 40 is shifted due to the deterioration due to the PBTS, the QB node voltage automatically rises and the pull-down unit 40 can be normally driven, thereby extending the service life.

The stage shown in Fig. 6 can omit the QB voltage generators 50 and 52 and the second QB switches TS2 and TS2a shown in Figs. 2 and 5, It is possible to further simplify the circuit configuration.

FIG. 7 is a block diagram schematically showing a configuration of a display device incorporating a shift register according to an embodiment of the present invention. Referring to FIG.

7 includes a display panel 500 including a pixel array 600 and a gate driver 400, a data driver 300, a timing controller 100, and a power supply (not shown).

The timing controller 100 inputs the basic timing control signal together with the video data supplied from the host set. The timing controller 100 modulates the image data using various data processing methods for image quality compensation and power consumption reduction, and outputs the modulated image data to the data driver 300.

The timing controller 100 generates a data control signal for controlling the operation timing of the data driver 300 and a gate control signal for controlling the operation timing of the gate driver 400 using the basic timing control signal, 300 and supplies a gate control signal to the gate driver 400. [ The basic timing control signal may include a dot clock signal and a data enable signal, and may further include a horizontal synchronization signal and a vertical synchronization signal. The data control signal includes a source start pulse and a source shift clock for controlling the latch timing of the video data in the data driver 300 and a source output enable signal for controlling the output period of the video data signal. (Source Output Enable) signal. The gate control signal includes a gate start pulse for controlling the operation timing of the gate driver 400 and a gate clock for use as an output signal or a shift control signal.

A level shifter LS may be additionally provided between the timing controller 100 and the gate driver 400 and the level shifter 200 may be incorporated in a power supply unit. The level shifter 200 outputs a gate control signal from the timing controller 100, that is, a gate start pulse and a TTL (transistor transistor logic) voltage of clocks to a gate high voltage for driving the TFT of the pixel array 600 And gate-off voltage (gate-off voltage), and supplies the level-shifted voltage to the gate driver 400.

The data driver 300 receives data control signals and image data from the timing controller 100. The data driver 300 is driven in accordance with the data control signal to divide the set of reference gamma voltages supplied from the gamma voltage generator into gradation voltages corresponding to the gradation values of the data, and then, using the subdivided gradation voltages, Converts the image data into analog image data signals, and supplies the analog image data signals to the data lines of the display panel 500, respectively.

The data driver 300 includes a plurality of data driver ICs for dividing and driving the data lines of the display panel 500. Each data driver IC includes a tape carrier package (TCP), a chip on film (COF) Circuit or the like to be mounted on a display panel 500 by a tape automatic bonding (TAB) method or a COG (Chip On Glass) method on a display panel 500.

The display panel 500 displays an image through a pixel array 600 in which pixels are arranged in a matrix. Each pixel of the pixel array 600 typically has a combination of R (Red), G (Green), and B (Blue) sub-pixels to implement a desired color and further includes a W do. Each sub-pixel is independently driven by a TFT. As the TFT, an amorphous TFT, a poly TFT, an oxide TFT, or the like can be used. As the display panel 500, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electrophoretic display (EPD), or the like can be used.

The gate driver 400 is a GIP type embedded in the non-display area of the display panel 500 and is composed of TFTs formed on the substrate together with the TFT array of the pixel array 600. [ The gate driver 400 may include any one of various embodiments of the shift register described above with reference to FIGS. 2-6 and may include gate lines of the pixel array 600 in response to a gate control signal from the timing controller 100 Respectively. The gate driver 400 outputs the scan output of the gate-on voltage during the scan period of each gate line, and outputs the gate-off voltage during the remaining period of time. The built-in gate driver 400 may be formed on one side or both side of the pixel array 600.

As described above, in the shift register and the display device using the shift register according to the present invention, the QB node controller supplies the DC voltage to the QB node and quickly removes the ripple of the Q node through the noise eliminator controlled by the QB node, The power consumption can be reduced.

The shift register and the display device using the same according to the present invention can compensate the voltage of the QB node to rise automatically according to deterioration of the TFT by using the voltage regulator including the TFT controlled by the QB node together with the pull- have. Therefore, even when the PBTS is accumulated due to the application of the DC voltage of the QB node, the QB node voltage is automatically compensated even when the threshold voltage of the pull-down TFT is shifted, so that the normal operation of the degraded pull-down TFT can be performed. have.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: set section 20: reset section
30: pull-up part 40: pull-down part
50, 52: QB voltage generator 60, 64: QB voltage regulator
70, 72, 74: QB switching unit 80, 82, 84: QB control unit
100: timing controller 200: level shifter (LS)
300: Data driver 400: Gate driver
500: display panel 600: pixel array

Claims (11)

In a shift register having a plurality of stages connected to each other in a dependent manner,
In each stage,
A set portion that is controlled by the set terminal to charge the Q node;
A reset unit controlled by a reset terminal to discharge the Q node;
A pull-up unit controlled by the Q node to output a corresponding clock supplied to a clock terminal among a plurality of clocks;
A pull down unit controlled by the QB node to output a low voltage;
A QB node controller for controlling the QB node;
And a noise eliminator controlled by the QB node to discharge the Q node,
The QB node control unit
A QB switching unit for charging the QB node during a second period different from the first period in which the set unit charges the Q node;
A QB voltage adjusting unit that adjusts at least one voltage supplied to the QB switching unit according to a resistance ratio between the first adjusting TFT and the second adjusting TFT and adjusts the QB voltage to automatically compensate the voltage of the QB node as the stress is applied to the QB node And a shift register. The method according to claim 1,
A first pull-up TFT controlled by the Q node and outputting the corresponding clock as a scan output through an output terminal; and a second pull-up TFT controlled by the Q node for outputting the corresponding clock as a carry signal through a carry terminal, 2 pull-up TFTs;
A pull-down section controlled by the QB node to output a first gate-off voltage to the output terminal; and a second pull-down TFT controlled by the QB node to output a second gate- TFT;
The noise remover includes at least one noise cancellation TFT controlled by the QB node to discharge the Q node to the second gate off voltage;
The set section includes at least one set TFT which is controlled by the set terminal and charges the Q node using the set signal supplied to the set terminal;
The reset section having at least one reset TFT controlled by the reset terminal to discharge the Q node to the second gate off voltage;
The set terminal is supplied with a start signal or a preceding carry signal supplied from any one of the preceding stages,
Wherein the reset terminal is supplied with a subsequent carry signal or a reset signal supplied from one of the succeeding stages. The method of claim 2,
Wherein the QB switching unit has a QB switch controlled by the reset terminal to connect the QB input node and the QB node;
The QB voltage regulator
The first control TFT controlled by the reset terminal to supply an input voltage to the QB input node,
And the second control TFT controlled by the QB node and connecting the QB input node to a terminal to which the second gate-off voltage is supplied;
And the inverted clock or gate-on voltage having a phase inverted from the clock supplied to the clock terminal is supplied to the input voltage supplied to the QB input node. The method of claim 3,
The channel size of the first adjustment TFT is set larger than the channel size of the second adjustment TFT,
Wherein a voltage of the QB input node and a voltage of the QB node are automatically increased as the resistance component of the second adjusting TFT increases due to a positive stress applied to the QB node. The method of claim 3,
A first capacitor connected between the Q node and the output terminal,
And a second capacitor connected between the QB node and a terminal to which the second gate-off voltage is supplied. The method of claim 2,
The QB switching unit has a first QB switch controlled by the control node to connect the QB input node and the QB node;
The QB voltage regulator
The first control TFT controlled by the reset terminal to supply an input voltage to the control node,
And the second control TFT controlled by the QB node to connect the control node with a terminal to which the second gate-off voltage is supplied;
The QB control unit
Further comprising a QB voltage generator for generating a voltage of the QB input node using the input voltage;
And the inverted clock or gate-on voltage having a phase inverted from the clock supplied to the clock terminal is supplied to the input voltage. The method of claim 6,
The channel size of the first adjustment TFT is set larger than the channel size of the second adjustment TFT,
And the voltage of the control node and the voltage of the QB node are automatically increased as the resistance component of the second control TFT increases due to the positive stress applied to the QB node. The method of claim 7,
The QB switching unit further comprises a second QB switch controlled by the set terminal to connect the QB input node and the QB node;
Wherein the QB voltage generator comprises: a charging TFT controlled by the input voltage to supply the input voltage to the QB input node; and a control terminal controlled by the set terminal to connect the QB input node to a terminal to which the second gate- And a discharge TFT connected thereto. The method of claim 7,
The QB switching unit further comprises a second QB switch controlled by the Q node to connect the QB node with a terminal to which a second gate-off voltage is supplied;
And the QB voltage generator includes a charging TFT controlled by the input voltage to supply the input voltage to the QB input node. The method of claim 7,
A first capacitor connected between the Q node and the output terminal,
And a second capacitor connected between the QB node and a terminal to which the second gate-off voltage is supplied,
And a third capacitor connected between the QB input node and a terminal to which the second gate-off voltage is supplied when the inverted clock is supplied to the input terminal. A display panel;
The display device according to any one of claims 1 to 10, which is embedded in a non-display region of the display panel and drives gate lines of the display panel individually.

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