KR20180024909A - driving transistor and Organic light emitting diode display device having the driving transistor, and Method for manufacturing the same - Google Patents

Abstract

The present invention relates to a driving transistor and an organic light emitting diode display device having the same, and a manufacturing method thereof to adjust gradation with a wide range of an input voltage value even if a pixel size is small. A driving transistor according to the present invention comprises a gate electrode, an active layer, a back bias gate electrode, a first gate insulating film between the gate electrode and the active layer, and a second gate insulating film between the back bias gate electrode and the active layer. The thickness of the first gate insulating layer is greater than or equal to the thickness of the second gate insulating layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving transistor and an organic light emitting diode (OLED) display device having the same,

The present invention relates to a driving transistor, an organic light emitting diode display device having the driving transistor, and a method of manufacturing the same. More particularly, the present invention relates to a driving transistor capable of expressing a finer gradation by enlarging a width of a data input voltage and an organic light emitting diode And a process for their preparation.

Recently, with the development of multimedia, the importance of flat panel display devices is increasing. In response to this, flat panel display devices such as liquid crystal display devices, plasma display devices, and organic light emitting display devices have been commercialized.

Among such flat panel display devices, an organic light emitting diode (OLED) display device is a self light emitting device that emits an organic light emitting layer by recombination of electrons and holes, has a high luminance, a low driving voltage, a high response speed, There is no problem in the next generation flat panel display device.

The organic light emitting diode display device includes subpixels of red (R), green (G), and blue (B) as one unit pixel (Unit Pixel) As shown in FIG.

Each of the plurality of subpixels constituting the OLED display device includes an OLED element composed of an anode and a cathode and an organic light emitting layer therebetween, and a pixel circuit for independently driving the OLED element.

The pixel circuit comprises a switching thin film transistor (TFT) for supplying a data voltage to the storage capacitor to charge a voltage corresponding to the data voltage, and a current control circuit for controlling the current according to the voltage charged in the storage capacitor, A thin film transistor (TFT) that supplies a current to the OLED element, and the OLED element generates light proportional to the current.

In recent years, as the resolution increases, the size of the sub-pixel becomes smaller. That is, the size of the sub-pixel is reduced from the size of 63 μm × 31.5 μm (403 ppi) to the size of 16.9 μm × 8.45 μm (1500 ppi). As the size of the sub-pixel is reduced, the current flowing in the OLED element is also reduced by a reduction ratio of the size. Moreover, when used for VR, it is unnecessary to use pol to prevent external reflection, so if the same current flows, the brightness is twice as bright as when applied to a TV or a smart phone. In the case of the VR product, the current flowing through the OLED device will be reduced to half of that of the other products when the brightness is on the screen.

When WOLED is used, the maximum value of current flowing in one subpixel is expected to be 5 x 10 < ^-9 > In this case, considering the characteristics of LTPS (Low Temperature Polycrystaline Silicon) TFT (Thin Film Transistor), the width of the data voltage usable for expressing the OLED gradation is not wide. Therefore, there is a difficulty in expressing the gradation.

1A is a graph showing the range of the gate voltage Vg of the driving thin film transistor when the subpixel size is 403 ppi, and FIG. 1B is a graph showing the range of the gate voltage Vg of the driving thin film transistor when the subpixel size is 1500 ppi. Fig.

As can be seen from FIGS. 1A and 1B, when the size of the subpixel is reduced from 403 ppi to 1500 ppi as the resolution increases, the gate voltage range of the driving thin film transistor becomes narrow and the width of the data voltage becomes narrow. Is difficult to express.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a driving transistor capable of adjusting gradation to a wide range of input voltage values, And to provide a manufacturing method thereof.

According to an aspect of the present invention, there is provided a driving transistor including a gate electrode, an active layer, a back bias gate electrode, a first gate insulating film between the gate electrode and the active layer, and a first gate insulating film between the back bias gate electrode and the active layer. And a second gate insulating film, wherein the first gate insulating film is thicker than or equal to the thickness of the second gate insulating film.

According to another aspect of the present invention, there is provided an organic light emitting diode (OLED) display device including a driving transistor and an OLED in a sub-pixel, the driving transistor including a gate electrode, an active layer, A gate electrode, a first gate insulating film between the gate electrode and the active layer, and a second gate insulating film between the back bias gate electrode and the active layer, wherein a thickness of the first gate insulating film is greater than a thickness of the second gate insulating film It is characterized by thicker or equal.

According to another aspect of the present invention, there is provided a method of manufacturing a driving transistor including: forming a gate electrode on a substrate; Forming a first gate insulating film on the entire surface of the substrate including the gate electrode; Forming an active layer on the first gate insulating film; Forming a second gate insulating film on the entire surface of the substrate including the active layer to a thickness thinner than or equal to that of the first gate insulating film; And forming a back bias gate electrode on the second gate insulating film.

According to another aspect of the present invention, there is provided a method of manufacturing an organic light emitting diode display, including: forming a first electrode of a storage capacitor on a substrate; Forming a dielectric film on the entire surface of the substrate on which the first electrode is formed; Forming a gate electrode of the driving transistor so as to overlap the first electrode on the dielectric film; Forming a first gate insulating film on the entire surface of the substrate including the gate electrode; Forming active layers for a switching transistor, a sensing transistor, and the driving transistor on the first gate insulating layer; Forming a second gate insulating film on the entire surface of the substrate including the active layer; Forming a back bias line including a scan line and a back bias gate electrode on the second gate insulating film in correspondence with each active layer; And selectively implanting impurity ions into the active layer to form the source / drain regions for the switching transistor, the sensing transistor, and the driving transistor.

Here, the manufacturing method of the organic light emitting diode display device may include forming an interlayer insulating film on the entire surface of the substrate including the scan line and the back bias line, inspecting a source / drain region of the switching transistor, a source / Forming first to third contact holes in a source / drain region of a driving transistor, respectively; Wherein the first contact hole connects the source / drain region of the switching transistor and the gate electrode of the driving transistor, the source / drain region of the sensing transistor and the driving transistor through the second contact hole, Forming a high potential driving voltage supply line connected to a source / drain region of the driving transistor through the second metal plug to which the first electrode of the capacitor is connected and the third contact hole; Forming a first protective film on the entire surface of the substrate, forming fourth to sixth contact holes on the source / drain region of the switching transistor, the source / drain region of the sensing transistor, and the second metal plug, respectively; A data line connected to the source / drain region of the switching transistor through the fourth contact hole, a reference voltage line connected to the source / drain region of the sensing transistor through the fifth contact hole, Forming a fourth metal plug to be connected; Forming a second protective film and a planarizing film on the entire surface of the substrate and forming a seventh contact hole on the fourth metal plug; The anode electrode of the OLED is formed on the planarization layer to be connected to the fourth metal plug through the contact hole 27, and the cathode electrode of the OLED is formed in order.

The first gate insulating layer is formed to a thickness of 1000 Å to 4500 Å, the active layer is formed to a thickness of 300 Å to 800 Å, and the second gate insulating layer is formed to a thickness of 500 Å to 1500 Å.

The driving transistor according to the present invention having the above characteristics, the organic light emitting diode display device having the same, and the method of manufacturing the same have the following effects.

First, since a back bias gate electrode is formed in the driving thin film transistor and a back bias of a constant potential is applied to the back bias gate electrode, even if the pixel size is small, the gray level can be adjusted to a wide range of input voltage values, The gradation can be expressed.

Second, a back bias line for applying a back bias of a constant potential to the back bias gate electrode is overlapped with the data line in a wide region so that the back bias line shields the potential of the data line, Can be reduced.

Third, since the thickness of the gate insulating film of the driving transistor and the gate insulating film of the back bias is controlled, the range of expressing the gray level can be increased.

1A is a graph showing the range of the gate voltage (Vg) of the driving thin film transistor when the subpixel size is 403 ppi
1B is a graph showing the range of the gate voltage (Vg) of the driving thin film transistor when the subpixel size is 1500 ppi
2 is a circuit configuration diagram of unit subpixels of the organic light emitting diode display device according to the present invention
3 is a layout diagram of unit subpixels of an organic light emitting diode display device according to the present invention
4 is a cross-sectional view of a unit subpixel of an organic light emitting diode display device according to the present invention
5A to 5I are process layouts for explaining a method of manufacturing an organic light emitting diode display device according to the present invention
6A to 6I are cross-sectional views illustrating a method of manufacturing an organic light emitting diode display according to an embodiment of the present invention.
7 is a layout view showing scan lines and back bias lines of the organic light emitting diode display device according to the present invention.
8A is a graph showing the range of the gate voltage of the driving thin film transistor of the conventional structure
8B is a graph showing the range of the gate voltage of the driving thin film transistor according to the present invention
9 is a diagram showing a capacitor model for explaining the reason why an input data range according to the present invention increases;

The driving transistor according to the present invention having the above characteristics, the organic light emitting diode display device having the same, and the manufacturing method thereof will be described in more detail with reference to the accompanying drawings.

FIG. 2 is a circuit configuration diagram of unit subpixels of an organic light emitting diode (OLED) display device according to the present invention, FIG. 3 is a layout diagram of unit subpixels of the organic light emitting diode display device according to the present invention, Sectional view of a unit sub-pixel of an organic light emitting diode display device according to the present invention.

The unit sub-pixel of the OLED display according to the present invention includes a pixel driving circuit including a light emitting device OLED and a plurality of transistors for driving the unit OLED, as shown in FIGS. The pixel driving circuit includes a driving transistor (D-TFT), a switching transistor SW1, a sensing transistor SW2, and a storage capacitor Cst.

In the embodiment of the present invention, a pixel driving circuit having a 3T1C structure is described by way of example, but it is not necessarily limited thereto, and the structure of the pixel driving circuit can be changed by an ordinary technician as needed.

The switching transistor SW1 has a gate electrode connected to a scan line Scan of each subpixel, a source electrode connected to a data line Vdata, a first node N 1, which is a first terminal of the storage capacitor Cst, ) Is connected to the drain electrode.

The switching transistor SW1 supplies the data voltage Vdata of the data line Vdata to the first node N in response to the first scan signal from the scan line Scan of each subpixel.

The gate electrode 3 is connected to the first node N, the drain electrode is connected to the high potential driving voltage source Vdd, and the anode electrode 28 of the light emitting element OLED The source electrodes 15 and 24 are connected.

Accordingly, the driving transistor D-TFT changes the amount of current flowing to the light emitting element OLED according to the source-gate voltage Vgs of the driving transistor D-TFT, that is, the voltage applied between the high potential voltage source Vdd and the first node N. [ .

The sensing transistor SW2 has a gate electrode connected to the sensing control line Sense of each subpixel, a source electrode connected to the second node S, and a drain electrode connected to the reference voltage line Vref. Here, the sensing transistor SW2 may be controlled by the scan line Scan instead of the sensing control line Sense.

Accordingly, the sensing transistor SW2 supplies a precharging voltage from the reference voltage line Vref to the second node S in response to the second scan signal from the sensing control line Sense or the scan line , And supplies the voltage of the anode electrode 28 of the light emitting element OLED to the reference voltage line Vref during the sensing period.

The storage capacitor Cst has a first terminal connected to the first node N and a second terminal connected to the second node S. The storage capacitor Cst charges the difference voltage between the voltages supplied to the first and second nodes N and S and supplies the difference voltage to the driving voltage Vgs of the driving transistor D-TFT. For example, the storage capacitor Cst charges the difference voltage between the data voltage Vdata and the precharge voltage Vpre supplied to the first and second nodes N and S, respectively.

Here, a back bias gate electrode is formed in the driving transistor (D-TFT) and is connected to the bias line (Vbias).

Since a constant potential is provided through the bias line Vbias, even if the pixel size is small, the gradation can be adjusted to a wide range of input voltage values, so that more detailed gradation can be expressed.

3, a bias line Vbias for applying a back bias of a constant potential to the back bias gate electrode is overlapped with a data line Vdata in a wide region so that a bias line Vbias is overlapped with the data line Vdata, (Vdata), the influence of the data line (Vdata) on the driving transistor (D-TFT) can be reduced.

As shown in Fig. 4, the driving transistor is composed of the gate electrode 3, the active layer 5c and the back bias gate electrode 7a. In this structure, the gate insulating film 4 between the gate electrode 3 and the active layer 5c is formed to a thickness of about 3000 Å, and the gate between the back bias gate electrode 7a and the active layer 5c If the insulating film 6 is formed to have a thickness of about 1000 angstroms, the range in which gradation can be expressed can be increased. The remaining configuration of Fig. 4 is described in 6a to 6i.

Although it is possible to further increase the range of gradation representation by forming the gate insulating film 4 to have a thickness larger than the thickness of the gate insulating film 6 as described above, The range of the gradation representation can be increased even if the thickness of the liquid crystal layer 6 is made equal. That is, the thickness of the gate insulating film 4 may be greater than or equal to the thickness of the gate insulating film 6.

A method of manufacturing unit subpixels having such a structure will be described below.

5A to 5I are process layout diagrams for explaining a method of manufacturing an organic light emitting diode display device according to the present invention, and FIGS. 6A to 6I are cross-sectional views illustrating a method of manufacturing an organic light emitting diode display device according to the present invention .

5A to 5I are process layout diagrams for explaining a method of manufacturing a unit pixel according to the present invention, and FIGS. 6A to 6I illustrate a method of manufacturing a driving transistor of a unit pixel according to the present invention Sectional view.

5A and 6A, a buffer layer 99 of about 3000 Å is formed on the substrate 100, a metal layer Mo is deposited on the buffer layer 99 to a thickness of about 500 Å, To form the first electrode 1 of the storage capacitor Cst.

5B and 6B, a dielectric film 2 (SiNx) for the storage capacitor Cst is formed to a thickness of about 1000 Å on the entire surface of the substrate 100 on which the first electrode 1 is formed. A metal layer Mo is deposited on the dielectric film 2 to a thickness of about 500 Å and selectively removed to form a driving transistor D-TFT on the dielectric film 2 so as to overlap the first electrode 1, The gate electrode 3 is formed. At this time, the gate electrode 3 also serves as a second electrode of the storage capacitor Cst.

A gate insulating film (SiO ₂ ) 4 and a semiconductor layer (a-Si) are sequentially formed on the entire surface of the substrate including the gate electrode 3, as shown in FIGS. 5C and 6C. The semiconductor layer is selectively removed to form the active layer 5a of the switching transistor SW1, the active layer 5b of the sensing transistor SW2, and the active layer 5c of the driving transistor D-TFT. Here, the gate insulating layer 4 is formed to a thickness of about 1000 Å to 4500 Å (for example, 3000 Å), and the active layers 5a, 5b and 5c are formed to have a thickness of 300 Å to 800 Å (for example, 500 Å).

The gate insulating film 6 for the back-bias, the switching transistor SW1 and the sensing transistor SW2 is formed on the entire surface of the substrate including the active layers 5a, 5b and 5c as shown in FIG. 5D and FIG. (For example, 1000 ANGSTROM). Then, a metal layer Mo is deposited and selectively removed to form a scan line 8, a back bias line 7, and a back bias gate electrode 7a so as to cross the active layers 5a, 5b, and 5c .

That is, the scan line 8 is formed to cross the active layers 5a and 5b to form the switching transistor SW1 and the sensing transistor 9SW2. The back bias line 7 and the back bias gate electrode The gate electrode 7a is formed to cross the active layer 5c to form a back bias gate electrode 7a and a back bias line 7 and Vbias of the driving transistor D-TFT.

The channel portions of the active layers 5a, 5b, and 5c on the substrate on which the scan line 8, the back bias line 7, and the back bias gate electrode 7a are formed, And the N-type impurity is implanted at a high concentration into the active layers 5a, 5b, and 5c using the photoresist pattern 9 as a mask. Then, the photoresist pattern 9 is removed and the active layer 5a, 5b, 5c is patterned by using the scan line 8, the back bias line 7, and the back bias gate electrode 7a as a mask, The source / drain regions (N +) 10a and 10b of the LDD structure of each of the transistors SW1, SW2 and D-TFT are formed by injecting impurities at a low concentration.

5F and 6F, an interlayer insulating film 11 (SiNx) is formed on the entire surface of the substrate on which the scan line 8, the back bias line 7 and the back bias gate electrode 7a are formed, . The contact holes 11, 12, and 13 are formed in the source / drain regions of the switching transistor SW1, the source / drain regions of the sensing transistor SW2, and the source / drain regions of the driving transistor D- .

Then, a metal layer is deposited and patterned on the interlayer insulating film 11 so that the contact holes 11, 12, and 13 are filled with the first to third metal plugs (the first metal plug is not shown, 15 and 16 ) And a high-potential driving voltage supply line 17 (see Vdd in Fig. 2).

The first metal plug (not shown in the figure) connects the source / drain region of the switching transistor SW1 and the gate electrode 3 of the driving transistor D-TFT, and the second metal plug 15 Drain region 10b of the sensing transistor SW2 and the driving transistor D-TFT to the first electrode 1 of the storage capacitor Cst and the third metal plug 16, Drain region 10a of the driving transistor D-TFT and the high-potential driving voltage supply line 17. The source /

Here, the first metal plug 14 corresponds to the first node N in FIG. 2, and the second metal plug 15 corresponds to the second node S in FIG.

In addition, the second metal plug 15 is formed extending toward the back bias gate electrode 7a.

The first protective film 18 is formed on the entire surface of the substrate on which the first to third metal plugs 14, 15 and 16 and the high potential driving voltage supply line 17 are formed, as shown in FIGS. 5G and 6G Contact holes 19, 20 and 21 are formed on the source / drain regions of the switching transistor SW1, the source and drain regions of the sensing transistor SW2, and on the second metal plug 15, respectively.

A metal layer is deposited on the entire surface and selectively removed to form a data line 22 (refer to Vdata in FIG. 2) to be connected to a source / drain region of the switching transistor SW1. A source of the sensing transistor SW2 A reference voltage line 23 (see Vref in FIG. 2) is formed so as to be connected to the second metal plug 15, and a fourth metal plug 24 is formed to be connected to the second metal plug 15.

5H and 6H, a second protective film 25 and a planarization film 26 are formed on the entire surface of the substrate thus formed, and a contact hole 27 is formed on the fourth metal plug 24 .

5I and 6I, a metal layer is deposited and selectively removed on the planarization layer 26 to be electrically connected to the fourth metal plug 24 through the contact hole 27, An electrode 28 is formed and a light emitting layer and a cathode electrode of the OLED are sequentially formed on the anode electrode 28, though not shown in the drawings.

As described above, the organic light emitting diode display device according to the present invention is manufactured.

7 is a layout diagram illustrating scan lines and back bias lines of an organic light emitting diode display device according to the present invention.

7, when the array is arranged such that the unit subpixels are symmetrical in the up, down, left, and right directions, the plurality of scan lines Scan n, Scan (n + 1) and the plurality of back bias lines And the plurality of back bias lines may be connected to a separate metal line through the contact holes in the outer area to supply a back bias current.

FIG. 8A is a graph showing the range of the gate voltage (Vgs) of the driving thin film transistor of the conventional structure, and FIG. 8B is a graph showing the range of the gate voltage (Vgs) of the driving thin film transistor according to the present invention.

8A and 8B, the present invention forms a back bias gate electrode in the driving transistor and applies a constant bias current to the back bias gate electrode. Therefore, although the input data range capable of expressing the gradation is 1.2V as the pixel size is reduced to about 1500ppi, in the present invention, even if the pixel size is as small as about 1500ppi, the input data range capable of expressing the gradation is about 3V Respectively.

As described above, the reason why the input data range capable of expressing the gray level is greatly increased to about 3V will be described as follows.

FIG. 9 illustrates a capacitor model for explaining why the input data range increases according to the present invention.

The reciprocal of the slope of the gate voltage of the thin film transistor is represented by an S-factor.

The S-factor can be approximated as the following equation (1).

In the driving transistor (D-TFT) of the present invention, the gate electrode 3 and the back bias gate electrode 7a are formed on both sides of the active layer 5c with the gate insulating film 4 and the gate insulating film 6 interposed therebetween.

In this structure, the thickness of the gate insulating film 4 between the gate electrode 3 and the active layer 5c, the thickness of the gate insulating film 6 between the back bias gate electrode 7a and the active layer 5c is adjusted The S-factor can be changed.

A capacitor model according to the driving transistor according to the present invention is shown in FIG. 9 when the driving transistor is operated by applying the back bias voltage so that the active layer 5c satisfies the Fully depletion condition.

9, Vg1 denotes a gate voltage applied to the back bias gate electrode 7a, Vg2 denotes a gate voltage applied to the gate electrode 3, and? S1 denotes a channel of the top portion of the active layer 5c And? S2 is the channel potential of the bottom portion of the active layer 5c.

The channel potential (? S1) of the top portion of the active layer 5c when the gate voltage Vg1 applied to the back bias gate electrode 7a is varied is shown in Equation (2).

The channel potential (? S2) of the bottom portion of the active layer 5c when the gate voltage Vg2 applied to the gate electrode 3 is varied is expressed by the following Equation (3).

When the potential of the channel changes according to the gate voltages Vg1 and Vg2 in the above-mentioned equations (2) and (3), it is seen that the influence of the gate insulating film 6 which is relatively back-biased is greatly exerted. That is, the ratio of the S-factor St when driven by the back bias gate electrode 7a and the S-factor Sb when driven by the gate electrode 3 is obtained as follows.

Here, as described above, when the thickness of the gate insulating film 6 is 1000 Å and the thickness of the gate insulating film 4 is 3000 Å, the ratio of the S-factor can be estimated as follows .

For convenience, assuming that the capacitance value of the gate insulating film 6 is Cox when the thickness of the gate insulating film 6 is 1000 angstroms,

When the thickness of the gate insulating film 4 is about three times larger than the thickness of the gate insulating film 6, the S-factor is about 2.7 times larger.

Equation (5) is a formula for applying the back bias voltage so that the active layer 5c satisfies the Fully depletion condition,

A thin film transistor having a thick gate insulating film as a gate electrode and a thin gate insulating film as a back bias gate electrode and applying a bias voltage to the back bias gate electrode can form a thin film transistor having a large S-factor.

For example, when the thickness ratio of the gate insulating film 6 and the gate insulating film 4 is 1000 Å / 1500 Å, the S-factor ratio Sb / St is Sb / St = (1/6 + 1.5) / (Sb / St) = Sb / St = (1/6 + 2) / (1) where Sb and Sb are the thicknesses of the gate insulating film 6 and the gate insulating film 4, / 6 + 1) = 1.9.

In the above description, the driving transistor has a bottom gate structure. However, the present invention is not limited to this, and the driving transistor may have a top gate structure and the back bias gate electrode may be formed at the bottom of the driving transistor.

Also in this structure, the thickness of the gate insulating film between the active layer and the gate electrode may be equal to or greater than the thickness of the gate insulating film between the active layer and the back bias gate electrode.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

1: first electrode 2: dielectric film
3: gate electrode 4: gate insulating film
5a, 5b, 5c: active layer 6: gate insulating film
7: bias line 7a: back bias gate electrode
8: scan line 9: photosensitive film pattern
10a, 10b: source / drain regions 11, 12, 13, 19, 20, 21, 27:
15, 16, 24: metal plug 17: high potential drive voltage supply line
18, 25: protective film 22: data line
23: reference voltage line 26: planarization film
28: anode electrode 30: interlayer insulating film

Claims (9)

A gate electrode, an active layer, a back bias gate electrode, a first gate insulating film between the gate electrode and the active layer, and a second gate insulating film between the back bias gate electrode and the active layer, And the second gate insulating film is thicker than or equal to the thickness of the second gate insulating film. The method according to claim 1,
Wherein the thickness of the first gate insulating layer is 1000 ANGSTROM to 4500 ANGSTROM, the thickness of the active layer is 300 ANGSTROM to 800 ANGSTROM, and the thickness of the second gate insulating layer is 500 ANGSTROM to 1500 ANGSTROM. An organic light emitting diode display device having a driving transistor and an OLED in a sub-pixel,
The driving transistor includes a gate electrode, an active layer, a back bias gate electrode, a first gate insulating film between the gate electrode and the active layer, and a second gate insulating film between the back bias gate electrode and the active layer, Wherein the thickness of the second gate insulating layer is greater than or equal to the thickness of the second gate insulating layer. The method of claim 3,
Wherein the thickness of the first gate insulating layer is 1000 ANGSTROM to 4500 ANGSTROM, the thickness of the active layer is 300 ANGSTROM to 800 ANGSTROM, and the thickness of the second gate insulating layer is 500 ANGSTROM to 1500 ANGSTROM. Forming a gate electrode on the substrate;
Forming a first gate insulating film on the entire surface of the substrate including the gate electrode;
Forming an active layer on the first gate insulating film;
Forming a second gate insulating film on the entire surface of the substrate including the active layer to a thickness thinner than or equal to that of the first gate insulating film;
And forming a back bias gate electrode on the second gate insulating film. 6. The method of claim 5,
Wherein the first gate insulating layer is formed to a thickness of 1000 Å to 4500 Å, the active layer is formed to a thickness of 300 Å to 800 Å, and the second gate insulating layer is formed to a thickness of 500 Å to 1500 Å. Forming a first electrode of the storage capacitor on the substrate;
Forming a dielectric film on the entire surface of the substrate on which the first electrode is formed;
Forming a gate electrode of the driving transistor so as to overlap the first electrode on the dielectric film;
Forming a first gate insulating film on the entire surface of the substrate including the gate electrode;
Forming active layers for a switching transistor, a sensing transistor, and the driving transistor on the first gate insulating layer;
Forming a second gate insulating film on the entire surface of the substrate including the active layer;
Forming a back bias line including a scan line and a back bias gate electrode on the second gate insulating film in correspondence with each active layer; And
And selectively implanting impurity ions into the active layer to form the source / drain regions for the switching transistor, the sensing transistor, and the driving transistor. 8. The method of claim 7,
An interlayer insulating film is formed on the entire surface of the substrate including the scan line and the back bias line, and a source / drain region of the switching transistor, a source / drain region of the sensing transistor, 3 forming a contact hole;
Wherein the first contact hole connects the source / drain region of the switching transistor and the gate electrode of the driving transistor, the source / drain region of the sensing transistor and the driving transistor through the second contact hole, Forming a high potential driving voltage supply line connected to a source / drain region of the driving transistor through the second metal plug to which the first electrode of the capacitor is connected and the third contact hole;
Forming a first protective film on the entire surface of the substrate, forming fourth to sixth contact holes on the source / drain region of the switching transistor, the source / drain region of the sensing transistor, and the second metal plug, respectively;
A data line connected to the source / drain region of the switching transistor through the fourth contact hole, a reference voltage line connected to the source / drain region of the sensing transistor through the fifth contact hole, Forming a fourth metal plug to be connected;
Forming a second protective film and a planarizing film on the entire surface of the substrate and forming a seventh contact hole on the fourth metal plug; And
Forming an anode electrode of an OLED on the planarization layer so as to be connected to the fourth metal plug through the contact hole 27 and sequentially forming a light emitting layer and a cathode electrode of the OLED, ≪ / RTI > 8. The method of claim 7,
Wherein the first gate insulating layer is formed to a thickness of 1000 A to 4500 ANGSTROM, the active layer is formed to a thickness of 300 ANGSTROM to 800 ANGSTROM, and the second gate insulating layer is formed to a thickness of 500 ANGSTROM to 1500 ANGSTROM.

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