KR20170065240A - Programming method of a non volatile memory device - Google Patents

Abstract

A programming method of a non-volatile memory device is disclosed. A programming method of a non-volatile memory device according to an embodiment of the present disclosure includes programming the memory cells based on a primary program voltage that is set to program at least a portion of the memory cells into a target state; Dividing the memory cells into a plurality of cell groups having different threshold voltage spreads, based on a programming rate of the memory cells determined according to a threshold voltage distribution of the memory cells; A plurality of cell groups other than the first cell group programmed to the target state among the plurality of cell groups are set to the target state based on a plurality of secondary program voltages set based on a threshold voltage difference between the plurality of cell groups And reprogramming.

Description

[0001] The present invention relates to a method of programming a nonvolatile memory device,

Technical aspects of the present disclosure relate to a semiconductor device, and more particularly, to a programming method of a nonvolatile memory device.

A memory device is used to store data, and is divided into a volatile memory device and a non-volatile memory device. As an example of a non-volatile memory device, the flash memory device may be used in a cell phone, a digital camera, a personal digital assistant (PDA), a mobile computer device, a stationary computer device, and other devices.

The problem to be solved by the technical idea of the present disclosure is to provide a programming method of a nonvolatile memory device and a nonvolatile memory device which can improve the program speed and reduce the width of the threshold voltage distribution of memory cells in programmed state .

According to another aspect of the present invention, there is provided a method for programming a non-volatile memory device including memory cells storing multi-bit data, the method comprising: Programming the memory cells based on a voltage; Dividing the memory cells into a plurality of cell groups having different threshold voltage spreads, based on a programming rate of the memory cells determined according to a threshold voltage distribution of the memory cells; And a plurality of cell groups other than the first cell group programmed to the target state among the plurality of cell groups based on a plurality of secondary program voltages set based on a threshold voltage difference between the plurality of cell groups, Lt; / RTI >

According to another aspect of the present invention, there is provided a method of programming a nonvolatile memory device, the method comprising: programming memory cells to an N-th (N is an integer of 2 or more) state; Detecting a program rate of a word line coupled to the memory cells; Adjusting a voltage level of the Nth program voltage set corresponding to the N state based on the detected program rate of the word line; And programming at least a portion of the memory cells to the N-th state based on the N-th program voltage set, wherein programming the memory cells to the N-1 state comprises: Dividing the memory cells into a plurality of cell groups having different threshold voltage ranges according to the program speed based on the distribution of the threshold voltages of the memory cells in accordance with the primary program voltage, It is possible to apply a plurality of secondary program voltages set based on the threshold voltage difference of the plurality of cell groups.

According to another aspect of the present invention, there is provided a method of programming a non-volatile memory device including memory cells storing multi-bit data, Programming a first program voltage corresponding to a first word line; programming the memory cells of the (n + 1) th word line based on the primary program voltage corresponding to the (n + 1) th word line; And dividing the memory cells of the n-th word line into a plurality of cell groups according to a program rate, and based on a plurality of secondary program voltages set based on a threshold voltage difference between the plurality of cell groups, Programming the memory cells of the word line to the target state.

According to the programming method of the nonvolatile memory device according to the technical idea of the present disclosure, based on the threshold voltage distribution of the one-shot memory cell, the memory cells are divided into a plurality of cell groups according to the program speed, Programming each cell group based on program voltages set based on a threshold voltage difference of the plurality of cell groups so that each of the plurality of cell groups having a width is programmed to a target state, And reduce the width of the threshold voltage distribution of each program state.

According to the programming method of the nonvolatile memory device according to the technical idea of the present disclosure, before the memory cells are programmed into their respective program states, the programming speed for each word line is checked, The width of the threshold voltage distribution of each programmed state programmed into the memory cell array can be reduced.

In addition, according to the programming method of the nonvolatile memory device according to the technical idea of the present disclosure, when the program is executed for the memory cells of one word line, the word line and the word line adjacent to the word line By performing a secondary program on the memory cells of the word line based on a threshold voltage distribution of the one-shot memory cells of the word line after applying a corresponding primary programming voltage to perform the primary programming, It is possible to prevent the shift of the threshold voltage distribution of each program state according to the human coupling effect.

BRIEF DESCRIPTION OF THE DRAWINGS A brief description of each drawing is provided to more fully understand the drawings recited in the detailed description of the present disclosure.
1 is a block diagram illustrating a memory device according to an embodiment of the present disclosure;
2 is a circuit diagram showing an example of a memory block according to an embodiment of the present disclosure;
3 is a circuit diagram showing another example of the memory block according to the embodiment of the present disclosure;
4 is a perspective view showing a memory block according to the circuit diagram of Fig.
5A and 5B are diagrams illustrating a method of operating a memory device according to an embodiment of the present disclosure.
6 is a flow diagram illustrating a method of operating a memory device in accordance with an embodiment of the present disclosure.
7A and 7B are graphs showing the distribution of memory cells according to the setting of the threshold voltage range of the cell groups.
8A to 8D are graphs showing steps of an example of the programming method according to the embodiment of the present disclosure.
FIG. 9 is a waveform diagram of a voltage applied to a word line connected to a memory cell programmed in FIG.
10 is a diagram illustrating in more detail a programming method according to an embodiment of the present disclosure.
11 (a) to 11 (c) are graphs showing steps of an example of the programming method according to the embodiment of the present disclosure.
12 is a waveform diagram of a voltage applied to a word line connected to a memory cell programmed in FIG.
13 is a diagram illustrating in more detail a programming method according to an embodiment of the present disclosure.
14A and 14B are diagrams for explaining a method of operating the memory device according to the embodiment of the present disclosure.
15 (a) to (f) are graphs showing steps of an example of the program method according to the embodiment of the present disclosure.
16 is a waveform diagram of a voltage applied to a word line connected to a memory cell programmed in FIG.
17A to 17D are graphs showing steps of an example of the programming method according to the embodiment of the present disclosure.
18 is a waveform diagram of a voltage applied to a word line connected to a memory cell programmed in Fig.
19 is a flow chart illustrating a method of operating a memory device in accordance with an embodiment of the present disclosure.
20 is a flow diagram illustrating a method of operating a memory device in accordance with an embodiment of the present disclosure.
Figure 21 shows the threshold voltage distribution of memory cells in accordance with each program state.
22 is an example of a method of operating a memory device according to an embodiment of the present disclosure, and is a waveform showing a voltage pulse applied to a word line.
23 is an example of a method of operating a memory device according to an embodiment of the present disclosure, and is a waveform showing a voltage pulse applied to a word line.
24 is a flowchart showing another example of the program method according to the embodiment of the present disclosure.
25A to 25C are graphs showing the threshold voltage distribution of the word line according to each step in the flowchart of FIG.
26A and 26B are diagrams showing the initial programming steps and the late programming steps for the memory cells of the word line.
27 is a flowchart showing another example of the program method according to the embodiment of the present disclosure.
28 shows a programming method of a memory cell array according to an embodiment of the present disclosure.
29 is a graph showing the program speed for each word line.
30 is a flow diagram illustrating a method of operating a memory device in accordance with an embodiment of the present disclosure.
31 is a diagram illustrating a program speed sensing and program voltage level compensation method of a word line according to an embodiment of the present disclosure;
32 is a diagram illustrating a method of setting a program voltage level to reflect a program speed of a word line according to an embodiment of the present disclosure;
33A-33C are graphs showing the threshold voltage distribution of word lines in stages of the programming method according to an embodiment of the present disclosure;
34 is a flow chart illustrating a method of operation of a memory device in accordance with an embodiment of the present disclosure.
35 is a diagram showing a method of detecting a program speed of a word line during program execution.
36 illustrates an embodiment of a method of operating a memory device according to an embodiment of the present disclosure.
37 is a flow chart illustrating in greater detail an operation method of a memory device according to an embodiment of the present disclosure.
38 is a block diagram showing an example of a program control unit according to the embodiment of the present disclosure;
39 is a block diagram illustrating a memory system in accordance with an embodiment of the present disclosure.
40 is a block diagram illustrating a memory card system in accordance with one embodiment of the present disclosure;
41 is a block diagram illustrating a computing system in accordance with one embodiment of the present disclosure.
42 is a block diagram illustrating an SSD system in accordance with one embodiment of the present disclosure;
43 is a block diagram illustrating a universal flash storage (UFS) according to an embodiment of the present disclosure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Also, the terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

1 is a block diagram illustrating a memory device according to an embodiment of the present disclosure;

Referring to FIG. 1, a memory device 100 may include a memory cell array 110, a row decoder 120, an input / output circuit 130, a voltage generator 140, and a control logic 150. The memory device 100 may be a non-volatile memory device that includes non-volatile memory cells.

The memory cell array 110 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. Hereinafter, embodiments will be described by exemplifying the case where a plurality of memory cells are NAND flash memory cells. However, the technical idea of the present disclosure is not limited thereto, and in other embodiments, the plurality of memory cells may be resistive memory cells such as resistive RAM (RRAM), phase change RAM (PRAM), or magnetic RAM .

In one embodiment, the memory cell array 110 may be a three-dimensional (3D) memory cell array. The three-dimensional memory cell array includes an active region disposed over a silicon substrate, and a circuitry associated with operation of the memory cells, wherein the three-dimensional memory cell array is monolithically formed on at least one physical level of memory cell arrays having a circuit formed on or in the substrate. do. The term "monolithic" means that layers of each level that make up the array are stacked directly on top of the layers of each lower level of the array. The 3D memory cell array includes NAND strings arranged in a vertical direction so that at least one memory cell is located above another memory cell. The at least one memory cell may include a charge trap layer. However, it is not so limited, and in another embodiment, the memory cell array 110 Dimensional memory cell array.

In this embodiment, each memory cell included in the memory cell array 110 may be a multi level cell (MLC) that stores two or more bits of data. For example, a memory cell may be a multi level cell (MLC) that stores 2-bit data. As another example, a memory cell may be a triple level cell (TLC) that stores 3-bit data. However, the present disclosure is not limited to this. In another embodiment, some of the memory cells included in the memory cell array 110 are single level cells (SLC) for storing 1-bit data, May be a multi level cell (MLC).

The memory cell array 110 includes a plurality of memory cells and may be connected to the word lines WL, the string selection lines SSL, the ground selection lines GSL, and the bit lines BL. Specifically, the memory cell array 110 is connected to the row decoder 120 through the word lines WL or the selection lines SSL and GSL and is connected to the input / output circuit 130 through the bit lines BL .

The memory cell array 110 may include a plurality of memory blocks BL1 to BLKi. The plurality of memory blocks BLK1 to BLKi may include at least one of a single level cell block including single level cells, a multi level cell block including multi level cells, and a triple level cell block including triple level cells . Some of the plurality of memory blocks included in the memory cell array 110 may be single level cell blocks and the other blocks may be multi level cell blocks or triple level cell blocks.

When an erase voltage is applied to the memory cell array 110, a plurality of memory cells are erased. When a program voltage is applied to the memory cell array 110, a plurality of memory cells are programmed. At this time, each memory cell may have an erase state E and at least one program state that are classified according to a threshold voltage (Vth).

In one embodiment, if the memory cell is a single level cell, the memory cell may have an erase state and a program state. In another embodiment, if the memory cell is a multi-level cell, the memory cell may have an erase state and at least three program states.

In this embodiment, the memory cells are divided into a plurality of cell groups according to the programmed speed and can be programmed.

For example, the memory cells may be programmed based on a preset primary programming voltage in response to a program state, and then programmed based on a threshold voltage distribution of the Gaussian form of the memory cells (hereinafter briefly referred to as " As shown in FIG. Subsequently, other cell groups other than the first cell group corresponding to the uppermost region of the distribution of the memory cells among the three cell groups can be reprogrammed into the program state based on the plurality of secondary program voltages. At this time, the plurality of secondary program voltages may be preset according to the dispersion of the one-shot memory cells and the primary program voltage.

In one embodiment, the first cell group is programmed at the highest rate among the three cell groups, and the distribution of the first cell group may be included in the target distribution of the programmed state.

In one embodiment, the threshold voltage range of the cell group corresponding to the middle region of the distribution of memory cells may be narrower than the threshold voltage range of other cell groups.

During one program cycle including these steps, the memory cells may be programmed into one of a plurality of program states. During a plurality of program cycles, memory cells may be programmed in a plurality of program states. For example, if the memory cell is a multi-bit cell storing two bits of data, the memory cell may have three program states and each of the plurality of memory cells during three program cycles may be programmed into one of the three program states .

The row decoder 120 may select some of the word lines WL in response to the row address X-ADDR. The row decoder 120 transfers the word line voltage to the word line. In operation of the program, the row decoder 120 may apply a program voltage and a verify voltage to a selected word line and a program, a non-selected word line (Unselected WL). For example, in a read operation, the row decoder 120 may apply a read voltage to a selected word line and a readable heavit voltage to a non-selected word line. In addition, the row decoder 120 may select some of the string selection lines or the ground selection lines GSL among the string selection lines SSL in response to the row address X-ARRD.

The input / output circuit 130 receives data from the outside (for example, a memory controller) and stores the input data in the memory cell array 110. Also, the input / output circuit 130 can read data from the memory cell array 110 and output the read data to the outside. The input / output circuit 130 may include page flushers (not shown) corresponding to the bit lines BL. The page buffer may be coupled to the memory cell array 110 via bit lines BL and may be coupled to some of the bit lines BL in response to a column address Y- Can be selected. The page buffer can function as a write driver and can program the data (DATA) to be stored in the memory cell array 110 during program operation.

The voltage generating unit 140 may generate various kinds of voltages for performing the program, read, and erase operations on the memory cell array 110 based on the voltage control signal CTRL_vol. Specifically, the voltage generating unit 140 may generate a word line voltage, for example, a program voltage (or a writing voltage), a reading voltage, a pass voltage (or a word line non-selecting voltage), or a verification voltage. The voltage generating unit 140 may generate a bit line voltage, for example, a bit line forcing voltage, an inhigh voltage, and the like. In addition, the voltage generator 140 may further generate the string selection line voltage and the ground selection line voltage based on the voltage control signal CTRL_vol.

The control logic 150 writes data to the memory cell array 110 or writes data to the memory cell array 110 based on the command CMD, the address ADDR and the control signal CTRL received from the memory controller 200 And can output various control signals for reading data from the array 110. [ Thereby, the control logic 150 can control the various operations in the memory device 100 as a whole.

The various control signals output from the control logic 150 may be provided to the voltage generator 140, the row decoder 120, and the input / output circuit 130. The control logic 150 may provide the voltage control signal CTRL_vol to the voltage generator 140 and may provide the row address X-ADDR to the row decoder 120 and the input / 130 may provide a column address (Y-ADDR). However, the present disclosure is not limited thereto, and the control logic 150 may further provide other control signals to the voltage generator 140, the row decoder 120, and the input / output circuit 130.

The control logic 150 may include a program control unit 160 for controlling a program for the memory cell array 110 according to a program sequence according to the programming method of the present disclosure.

The program control unit 160 can control the program operation of the memory device 100. [ In the embodiment, the program control unit 160 can set the voltage levels of the plurality of drive voltages corresponding to each of the plurality of program states. The plurality of drive voltages may include program voltages corresponding to each of the plurality of program states, verify voltages, offset voltages, compensation voltages according to the program speed of the word lines, and the like.

In an embodiment, the program control unit 160 may apply a test program voltage to the memory cell array 110 and determine a threshold voltage distribution of the Gaussian form of the memory cells based on the at least one read voltage. The program control unit 160 controls, based on the threshold voltage distribution of the memory cells, control signals for dividing the memory cells to be programmed into groups according to the programming rate, for example, at least one verification voltage, The time setting signal can be set. In addition, the program control unit 160 can set the voltage levels of the corresponding program voltage sets (e.g., the primary program voltage and the plurality of secondary program voltages) for each program state.

In the embodiment, the program control unit 160 detects the program speed for each word line before programming the memory cells into the respective program states, for example, when executing the program in the previous state, The voltage can be set. In addition, the program controller 160 may adjust the voltage level of the program voltage based on the compensation voltage and the program voltage of the previous state, when setting the program voltage for each program state.

In the embodiment, the program control unit 160 can control the word line-by-word program sequence of the memory cell array 110. The program control unit 160 performs a primary program on the memory cells of the word line on the basis of the primary program voltage when the program is executed on the memory cells of one word line, The cells may be divided into a plurality of cell groups for each program speed and a secondary program may be executed for the memory cells based on a plurality of secondary program voltages set based on a threshold voltage difference of the plurality of cell groups. At this time, the program control unit 160 executes a primary program for memory cells of one word line, performs a primary program for an adjacent word line, and then performs a secondary program for the memory cells of the word line By setting the program sequence so as to prevent the adjoining Wardmann coupling effect.

The memory device 100 according to the present embodiment can program memory cells based on a preset program voltage corresponding to each of a plurality of program states at the time of executing the program. Further, the memory device 100 divides the memory cells into a plurality of cell groups according to the program speed based on the threshold voltage distribution of the one-shot memory cells, and each of the plurality of cell groups having different threshold voltage spreading widths By programming each cell group based on program voltages set on the basis of the threshold voltage difference of the plurality of cell groups to be programmed to the target state, the same program number can be programmed for each program state. As a result, the programming time of the memory device 100 can be reduced and the width of the threshold voltage distribution of each program state can be reduced.

Further, the memory device 100 according to the present embodiment checks the program speed of the memory cells per word line before programming the memory cells into the respective program states, and reflects the compensation voltage according to the program speed to the program voltage , The width of the threshold voltage distribution of each programmed state programmed into the memory cell array can be reduced.

In addition, the memory device 100 according to the present embodiment is configured such that, when a program is executed for the memory cells of one word line, the first word line and the second word line corresponding to the word line adjacent to the word line, Performing a first program by applying a voltage and then performing a second program on the memory cells of the word line based on a threshold voltage distribution of the one-shot memory cell of the word line, .

Hereinafter, the programming method and the operating method of the memory device 100 and the memory device according to the embodiment of the present disclosure will be described in detail.

2 is a circuit diagram showing an example of a memory block according to an embodiment of the present disclosure;

Referring to FIG. 2, the memory block BLKa may be a horizontal NAND flash memory. The memory block BLKa may include, for example, d (d is an integer of 2 or more) strings (STRs) in which two memory cells are connected in series. Each string STR may include a string selection transistor SST and a ground selection transistor GST, which are connected to both ends of the memory cells MC connected in series. Here, the number of strings STR, the number of word lines WL, and the number of bit lines BL may be variously changed according to the embodiment.

The NAND flash memory device including the memory block having the structure as shown in FIG. 2 is erased in units of memory blocks and can perform a program in units of pages corresponding to the word lines WL1 to WL8. In one example, when the memory cell MC is a single level cell, one page (PAGE) may be associated with each word line. In another example, when the memory cell MC is a multi-level cell or a triple level cell, a plurality of pages (PAGE) may be associated with each word line.

3 is a circuit diagram showing another example of the memory block according to the embodiment of the present disclosure;

Referring to FIG. 3, the memory block BLKb may be a vertical NAND flash memory. The memory block BLKb includes a plurality of NAND strings NS11 to NS33, a plurality of word lines WL1 to WL8, a plurality of bit lines BL1 to BL3, ground selection lines GSL1, GSL2 and GSL3, A plurality of string selection lines SSL1 to SSL3, and a common source line CSL. Here, the number of NAND strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may be variously changed according to the embodiment.

NAND strings NS11, NS21 and NS31 are provided between the first bit line BL1 and the common source line CSL and NAND strings NS11, NS21 and NS31 are provided between the second bit line BL2 and the common source line CSL. NS12, NS22 and NS32 are provided and NAND strings NS13, NS23 and NS33 are provided between the third bit line BL3 and the common source line CSL. Each NAND string (e.g., NS11) may include a string selection transistor SST connected in series, a plurality of memory cells MC1 through MC8, and a ground selection transistor GST. Hereinafter, the NAND string will be referred to as a string for convenience.

Strings connected in common to one bit line constitute one column. For example, the strings NS11, NS21, and NS31 connected in common to the first bit line BL1 correspond to the first column and the strings NS12, NS22, and NS31 connected in common to the second bit line BL2, NS32 correspond to the second column, and the strings NS13, NS23, and NS33 connected in common to the third bit line BL3 may correspond to the third column.

The strings connected to one string selection line constitute one row. For example, the strings NS11, NS12 and NS13 connected to the first string selection line SSL1 correspond to the first row and the strings NS21, NS22 and NS23 connected to the second string selection line SSL2 correspond to the first row, And the strings NS31, NS32, NS33 connected to the third string selection line SSL3 may correspond to the third row.

The string selection transistor SST is connected to the string selection lines SSL1 to SSL3. A plurality of memory cells MC1 to MC8 are connected to the corresponding word lines WL1 to WL8, respectively. The ground selection transistor GST is connected to the ground selection lines GSL1, GSL2 and GSL3. The string selection transistor SST is connected to the corresponding bit line BL, and the ground selection transistor GST is connected to the common source line CSL.

The word lines (for example, WL1) having the same height are connected in common, and the string selection lines SSL1 to SSL3 are separated from each other. For example, when programming the memory cells connected to the first word line WL1 and belonging to the strings NS11, NS12 and NS13, the first word line WL1 and the first string selection line SSL1, Can be selected. In one embodiment, as shown in FIG. 4, the ground selection lines GSL1, GSL2, and GSL3 may be separated from each other. In another embodiment, the ground selection lines GSL1, GSL2, and GSL3 may be connected to each other.

4 is a perspective view showing a memory block according to the circuit diagram of Fig.

Referring to FIG. 4, the memory block BLK is formed in a direction perpendicular to the substrate SUB. The substrate SUB may be the first semiconductor layer 10 of Fig. The substrate SUB has a first conductivity type (for example, p type) and extends on the substrate SUB in a first direction (e.g., x direction) and a second conductivity type , n-type) doped with impurities can be provided on the common source line CSL. The common source line CSL can function as a source region for supplying current to vertical memory cells.

A plurality of insulating films IL extending in a second direction (e.g., the y direction) are formed on a region of the substrate SUB between two adjacent common source lines CSL in a third direction (e.g., z direction), and the plurality of insulating films IL are spaced apart from each other by a specific distance along the third direction. For example, the plurality of insulating films IL may include an insulating material such as silicon oxide.

A channel hole is sequentially formed along the first direction on the region of the substrate SUB between two adjacent common source lines CSL and through the plurality of insulating films IL along the third direction . The channel hole may be formed in a cup shape (or a bottomed cylinder shape) extending in the vertical direction. Or the channel hole may be formed in a pillar shape as shown in FIG. Hereinafter, the channel hole will be referred to as pillars. The plurality of pillars (P) can contact the substrate (SUB) through a plurality of insulating films (IL). In particular, the surface layer S of each pillar P may comprise a silicon material having a first type and function as a channel region. On the other hand, the inner layer (I) of each pillar (P) may comprise an insulating material such as silicon oxide or an air gap.

A charge storage layer CS is provided along the exposed surfaces of the insulating films IL, pillars P and the substrate SUB in the region between the two adjacent common source lines CSL. For example, the charge storage layer (CS) may have an oxide-nitride-oxide (ONO) structure. In addition, in the region between the two adjacent common source lines CSL, the gate electrode GE can be provided on the exposed surface of the charge storage layer CS.

Drains or drain contacts DR are provided on the plurality of pillars P, respectively. For example, the drains or drain contacts DR may comprise silicon material doped with dopants having a second conductivity type. On the drains or drain contacts DR, bit lines BL extending in a second direction (e.g., the y direction) and spaced a certain distance along the first direction may be provided.

Referring to Fig. 4, an embodiment of a memory block has been described. However, the present invention is not limited thereto, and the structure of the memory block may be variously modified.

5A and 5B are diagrams illustrating a method of operating a memory device according to an embodiment of the present disclosure. FIG. 5A shows a method of dividing memory cells into a plurality of cell groups according to a program rate based on one-shot distribution of memory cells, FIG. 5B shows a method of dividing a program voltage applied to a plurality of cell groups .

One-shot scattering refers to the scattering of the threshold voltages of memory cells that occur when one program pulse voltage is applied to a selected word line. Referring to FIG. 5A, when one program pulse voltage is applied to a word line, the threshold voltage distribution of the memory cells connected to the word line, that is, one-shot dispersion, may have a Gaussian distribution, as shown.

According to the operating method of the memory device according to the present embodiment, that is, according to the programming method, a one-shot dispersion (OS) of a memory cell formed on the basis of a primary program voltage such as a first program voltage Vpgm1 MCG1, MCG2, and MCG3 according to the program speed and divides the threshold voltage difference between the plurality of cell groups MCG1, MCG2, and MCG3 or the plurality of cell groups MCG1, Such as the second program voltage Vpgm2, and the third program voltage Vpgm2, which are set based on the threshold voltage range (dVth1, dVth2, dVth3; or the threshold voltage dispersion width) (Vpgm3), the memory cells can be programmed to the target program state Pn. At this time, the threshold voltage ranges (dVth1, dVth2, dVth3) of the plurality of cell groups MCG1, MCG2, MCG3 can be set to be different from each other. In the embodiment, the threshold voltage range (dVth1, dVth2, dVth3) can be set based on the number of memory cells included in the unit threshold voltage range of each cell group. For example, the threshold voltage range (dVth1, dVth2, dVth3) may be set in inverse proportion to the number of memory cells included in the unit threshold voltage range of each cell group (hereinafter referred to as the number of unit cells). According to the Gaussian-type one-shot scattering shown in the figure, the number of unit cells of the second cell group MCG2 included in the middle region of the one-shot scattering is larger than that of the first cell group MCG1 included in the edge region of the one- Or the number of unit cells of the third cell group MCG3. Therefore, the threshold voltage range dVth2 of the second cell group MCG2 can be set to be narrower than the threshold voltage range dVth1, dVth3 of the first cell group MCG1 or the second cell group CMG3.

On the other hand, the offset voltage Voff1, Voff2 between the program voltages Vpgm1, Vpgm2, and Vpgm3, that is, the voltage increase amount is the threshold voltage difference of the plurality of cell groups MCG1, MCG2, MCG3 or the threshold voltage range dVth1, dVth2 , dVth3). For example, the first offset voltage Voff1 and the second offset voltage Voff2 are set based on the threshold voltage range dVth2 of the second cell group MCG2 and the threshold voltage range dVth3 of the third cell group MCG3 Can be set. The first offset voltage Voff1 and the second offset voltage Voff2 are set to the threshold voltage range dVth2 of the second cell group MCG2 and the threshold voltage range dVth3 of the third cell group MCG3, . ≪ / RTI > In an embodiment, the first offset voltage Voff1 and the second offset voltage Voff2 may be equal to the threshold voltage ranges dVth2 and dVth3, respectively. Since dVth3 is wider than dVth2, the second offset voltage Voff2 may be larger than the first offset voltage Voff1.

On the other hand, the primary program voltage, that is, the first program voltage Vpgm1 is set so that at least some of the memory cells, for example, among the memory cells, the memory cells whose programming speed is relatively fast are included in the target distribution TP of the target state Pn It may be a preset voltage. In an embodiment, the first program voltage Vpgm1 may be a pre-set voltage such that the memory cells of the top cell group, e.g., the first cell group MCG1, of the one-shot dispersion are included in the target distribution TP.

6 is a flow diagram illustrating a method of operating a memory device in accordance with an embodiment of the present disclosure. 5A, 5B, and 6, a method of programming memory cells into one of a plurality of program states according to an operation method of a memory device according to an embodiment of the present disclosure will be described.

Referring to FIG. 6, memory cells may be programmed based on the primary program voltage (S110). The primary program voltage includes the first program voltage Vpgm1. The first program is executed by applying the first program voltage Vpgm1 to the memory cells in the previous state Pn-1 (or erase state). Some of the memory cells, memory cells with fast program speeds, may be included in the target spread (TP).

For example, when the memory cells are programmed in the first program state, a predetermined primary programming voltage, i.e., the first program voltage Vpgm1, corresponding to the first program state may be applied to the memory cells. Thus, the memory cells can be roughly programmed to the first program state. Some of the memory cells, e.g., some of the memory cells, may be included in the target distribution of the first program state, with some memory cells having relatively fast programming speeds.

The memory cell in which the primary program has been executed can be verified and read out, and the memory cells can be divided into a plurality of cell groups according to the programming speed based on the threshold voltage of the memory cells (S120). For example, memory cells may be divided into at least three cell groups.

According to the primary program execution, one-shot scattering of memory cells is formed, and the memory cells can be read out to be divided into a plurality of cell groups. Although FIG. 5A illustrates that the memory cells are divided into three cell groups, the present invention is not limited thereto. The memory cells can be divided into a larger number of cell groups.

When the memory cell is a multi-level cell storing two bits of data, the memory cells can be divided into three cell groups. In another embodiment, when the memory cell is a triple level cell storing three bits of data, the memory cells can be divided into five cell groups. However, the present invention is not limited thereto, and the number of cell groups can be determined according to the width of the target distribution in the program state. For example, the number of cell groups when the target scatter width in the program state is narrow may be larger than the number of cell groups in the case where the target scatter width in the program state is wide.

On the other hand, in step S120, the threshold voltage ranges of the plurality of cell groups may be set to be different from each other. For example, the threshold voltage range of the cell group corresponding to the middle region of the distribution of the memory cells among the plurality of cell groups may be set to be relatively narrower than the threshold voltage range of the other cell groups. Further, the threshold voltage range of the cell groups corresponding to the upper region or the lower region of the distribution of the memory cells may be set to be relatively wider than the threshold voltage range of the other memory cells.

5A, the threshold voltage range dVth2 of the second cell group MCG2 corresponding to the middle region of the distribution of the memory cells among the first to third cell groups MCG1, MCG2, and MCG3, May be set to be relatively narrower than the threshold voltage range (dVth1, dVth3) of the first cell group MCG1 or the third cell group MCG3 corresponding to the edge region of the scattering.

Meanwhile, the memory cells can be divided into a plurality of cell groups by reading and verifying based on a preset verification voltage. At this time, the verify voltage may be set so that a plurality of cell groups have different threshold voltage ranges. The verify voltage can be used to determine the program state of the memory cells in accordance with the one-shot program (e.g., the dispense range of the one-shot dispense, the dispense position, etc.) May be set based on the threshold voltage ranges of the cell group

For example, the memory cells can be divided into a plurality of cell groups by verifying and reading the memory cells based on the first verify voltage Vrf1 and the second verify voltage Vrf2. The voltage difference between the first verify voltage Vrf1 and the second verify voltage Vrf2 may be proportional to the threshold voltage range dVth2 of the second cell group MCG2.

In one embodiment, memory cells can be divided into three cell groups through a single verify read operation by sensing memory cells twice at different times based on one verify voltage. This can be referred to as a double sensing operation. At this time, the time interval between the first sensing time and the second sensing time may be set based on the threshold voltage range (dVth2) of the second cell group MCG2. For example, the time interval when the threshold voltage range of the second cell group MCG2 is 1V (volt) may be set to be narrower than the time interval when the threshold voltage range is 0.8V.

Thereafter, based on the second program voltage Vpgm2 and the third program voltage Vpgm3, the voltage level of which is set based on the threshold voltage difference of the plurality of cell groups, at least some of the plurality of cell groups The cell group can be reprogrammed (S130). In other words, among the plurality of cell groups, the cell groups excluding the cell group included in the target spread TP can be reprogrammed. For example, if the first cell group MCG1 is included in the target spread TP and the other cell groups MCG2 and MCG3 are out of the target spread TP, The second cell group MCG2 and the third cell group MCG3 excluding the cell group MCG1 can be reprogrammed to the target state. The second cell group MCG2 and the third cell group MCG3 can be reprogrammed based on a plurality of secondary program voltages, i.e., the second program voltage Vgpm2 and the third program voltage Vpgm3. The second program voltage Vpgm2 whose voltage level is increased by the first offset voltage Voff1 from the first program voltage Vpgm1 can be applied to the second cell group MCG2 and the third cell group MCG3. Accordingly, the memory cells of the second cell group MCG2 may be included in the target spread TP. Next, the third program voltage Vpgm3 whose voltage level is increased by the second offset voltage Voff2 from the second program voltage Vpgm2 may be applied to the third cell group MVG3. Accordingly, the memory cells of the third cell group MCG3 may be included in the target spread TP.

The first program voltage Vpgm1 is applied to the second cell group MCG2 and the third cell group MCG3 at a voltage level equal to the sum of the first offset voltage Voff1 and the second offset voltage Voff2, By applying the increased second program voltage Vpgm2, a secondary program can be executed. At this time, the programming speed of the second cell group MCG2 can be slowed down by applying the forcing voltage to the bit lines of the memory cells of the second cell group MCG2. The voltage level of the forcing voltage may be equal to the level of the second offset voltage Voff2. Accordingly, the memory cells of the second cell group MCG2 and the third cell group MCG3 may be included in the target spread TP.

7A and 7B are graphs showing the distribution of memory cells according to the setting of the threshold voltage range of the cell groups. FIG. 7A shows a case where the threshold voltage ranges of the cell groups are set to be the same, and FIG. 7B shows the case where the threshold voltage ranges of the cell groups are set differently according to the embodiment of the present disclosure.

Referring to FIG. 7A, when memory cells are programmed according to the ISPP (Incremental Step Pulse Programming) scheme, the memory cells may be divided into a plurality of cell groups having the same threshold voltage range. Since the voltage pulse is increased to a certain level according to each program step, the threshold voltage range (or the spreading width) of the cell groups programmed in the target program state in each program step may also be equal to each other. At this time, the number of memory cells of the second cell group MCG2 is larger than the number of memory cells of the first cell group MCG1 or the third cell group MCG3. Therefore, the threshold voltage range dVthF2 of the final dispersion of the second cell group MCG2 may be wider than the threshold voltage range dVthF1 of the final dispersion of the first cell group MCG1 and the third cell group MCG3. In this way, when the memory cells are divided into a plurality of cell groups having the same threshold voltage range, the threshold voltage range of the final threshold voltage distribution of the cell groups may be different from each other. The final threshold distribution of the cell groups should be included in the target distribution of the target program state. Thus, the number of programs can be increased to match the final disparity of the cell group with the largest disparity among the cell groups to the target disparity.

However, as shown in FIG. 7B, according to the embodiment of the present disclosure, the memory cells are divided into a plurality of cell groups with different threshold voltage ranges, and the threshold voltages of the respective cell groups in inverse proportion to the number of the unit cells of each cell group If the range is set, the difference in the number of memory cells included in each cell group may not be large.

If a plurality of cell groups are programmed based on the program voltages whose voltage levels are set according to the threshold voltage range, the threshold voltage range (dVthF3) of the final dispersion of the respective cell groups may be similar to each other. 7A, the maximum value (dVthF3) of the threshold voltage range of the final dispersion of each cell group may be narrower than the maximum value (dVthF2) of the final dispersion of each cell group in Fig. 7A. Therefore, according to the programming method according to the embodiment of the present disclosure, by setting the threshold voltage range of the cell groups differently, programming can reduce the program number or reduce the width of the threshold voltage distribution of the memory cells in which the program is completed .

8A to 8D are graphs showing steps of an example of the programming method according to the embodiment of the present disclosure. FIG. 9 is a waveform diagram of a voltage applied to a word line connected to a memory cell programmed in FIG.

8A and 9, a first program voltage, that is, a first program voltage Vpgm1, is applied to the memory cells in the erase state E. Thereby, a one-shot dispersion of the memory cells according to the first program voltage Vpgm1 is formed. One-shot shots can have a Gaussian shape. The upper region of the one-shot scatter (right region of the one-shot scatter) may be included in the target scatter TP1 of the first program state P1. In other words, in one-shot shots of memory cells, the threshold voltage of the memory cells of the upper portion may be included within the threshold voltage range dVT of the target distribution TP1.

Referring to FIG. 8B, the memory cells are divided into three cell groups G1, G2 and G3 according to the programming speed, based on the threshold voltages of the memory cells. The memory cells can be divided into three cell groups through the verification readout. In one embodiment, the memory cells can be divided into three cell groups by verifying and reading the memory cells based on the first verify voltage Vrf1 and the second verify voltage Vrf2. In the embodiment, the voltage difference between the first verify voltage Vrf1 and the second verify voltage Vrf2 may be equal to the threshold voltage range dVth2 of the second cell group G2. In an embodiment, the first verify voltage Vrfl may be equal to the verify read voltage Vvl for the first program state to verify that the memory cells are normally programmed to the first program state.

The threshold voltage range (dVth1, dVTh2, dVth3) of the cell groups G1, G2, G3 can be set based on the unit threshold voltage range of the corresponding cell group. For example, the threshold voltage range (dVth1, dVth2, dVth3) may be set in inverse proportion to the number of memory cells included in the unit threshold voltage range of each cell group (hereinafter referred to as the number of unit cells). The threshold voltage range dVth2 of the second cell group G2 may be narrower than the threshold voltage range dVthl of the first cell group G1 or the threshold voltage range dVth3 of the second cell group G3.

The second program voltage Vpgm2 of the plurality of secondary program voltages is applied to the memory cells of the second cell group G2 and the third cell group G3, . The voltage level of the second program voltage Vpgm2 is a value obtained by adding the first offset voltage Voff1 to the voltage level of the first program voltage Vpgm1. The first offset voltage Voff1 may be equal to the threshold voltage range dVth2 of the second cell group G2.

The second program voltage Vpgm2 is applied to the memory cells of the second cell group G2 and the third cell group G3 except for the first cell group G1 already included in the target distribution TP1, The threshold voltage dispersion of the two cell group G2 and the third cell group G3 moves to the right and the second cell group G2 can be included in the target dispersion TP1.

Thereafter, as shown in Fig. 8 (d), the third program voltage Vpgm3 of the secondary program voltage is applied to the memory cells of the third cell group G3. The voltage level of the third program voltage Vpgm3 is a value obtained by adding the second offset voltage Voff2 to the voltage level of the second program voltage Vpgm2. The second offset voltage Voff1 may be equal to the threshold voltage range dVth3 of the third cell group G3. Therefore, the threshold voltage distribution of the third cell group G3 moves to the right, and the third cell group G3 can be included in the target cell population TP1. Thereby, the memory cells can be programmed in the first program state P1.

8 and 9, the case of programming the memory cells into the first program state P1 has been described step by step. The above-described method can also be applied to the case where the memory cells are programmed in a different program state.

10 is a diagram illustrating in more detail a programming method according to an embodiment of the present disclosure. FIG. 10 is a more detailed description of the programming method according to FIGS. 8 and 9, and the description with reference to FIGS. 8 and 9 can be applied to the embodiment of FIG.

Referring to FIG. 10, a first program may be executed by applying a first program voltage to a word line to which memory cells are connected (S210). The distribution of a portion of the memory cells, i. E., The distribution of the upper region of the one-shot distribution of memory cells, may be included in the target distribution of the target programmed state.

Based on the threshold voltages of the memory cells, the memory cells are divided into three cell groups according to the program speed (S220). The first programmed memory cells may be verified and read based on a preset verification voltage to divide the memory cells into three cell groups according to the threshold voltage. At this time, a cell group having a relatively high threshold voltage, for example, a first cell group includes a fast cell having a high program rate, and a cell group having a relatively low threshold voltage, such as a third cell group, . Thus, the memory cells can be divided into three cell groups according to the program speed. At this time, the threshold voltage range of the cell group corresponding to the middle region of the scattering of the memory cells among the three cell groups, for example, the second cell group, is higher than the threshold voltage range of the other cell groups such as the first cell group and the second cell group Can be set narrowly.

After the memory cells are divided into three cell groups, a second program step S230 and a third program step S240 may be performed.

First, an inhigh voltage is applied to the bit line of the memory cells of the first cell group (S231). The distribution of the first cell group may be included in the target distribution of the target program state. Thus, the program for the first cell group no longer proceeds. An inhigh voltage may be applied to the bit line of the memory cells of the first cell group to prevent the program from being performed for the first cell group.

Thereafter, the second program voltage may be applied to the word line (S232). The second program voltage is a voltage whose voltage level is increased from the first program voltage by the first offset voltage, and the first offset voltage may be set based on the threshold voltage range of the second cell group. According to the second program S230, the distribution of the second cell group may be included in the target distribution of the target program state.

Since the scattering of the first cell group and the second cell group is included in the target scatter, a third program (S240) may then be performed for the third cell group.

An inhigh voltage is applied to the bit lines of the memory cells of the first cell group and the second cell group (S241), and the third program voltage is applied to the word line (S242). The third program voltage may be a voltage whose voltage level is increased from the second program voltage by a second offset voltage and the second offset voltage may be set based on a threshold voltage range of the third cell group. According to the third program (S240), the distribution of the third cell group may be included in the target distribution. Thereby, the program for one program state can be completed.

Meanwhile, although not shown, in one embodiment, after step S240, a verify reading step may be performed to determine whether the memory cells are normally programmed to the target program state. If the threshold number of memory cells deviate from the target spread of the target program state, additional programming may be performed on the memory cells. Or a page including the memory cells may be failed.

11 (a) to 11 (c) are graphs showing steps of an example of the programming method according to the embodiment of the present disclosure. 12 is a waveform diagram of a voltage applied to a word line connected to a memory cell programmed in FIG.

11A and 12, a first program voltage, that is, a first program voltage Vpgm1 is applied to the memory cells in the erase state E, and the first program PGM1 is performed on the memory cells . Referring to FIG. 11B, the memory cells are divided into three cell groups G1, G2 and G3 according to the programming speed, based on the threshold voltages of the memory cells. The steps of FIGS. 11A and 11B are the same as those of FIGS. 8A and 8B, and a detailed description thereof will be omitted.

The second program voltage Vpgm2 may be applied to the memory cells of the second cell group G2 and the third cell group G3 so that the second program PGM2 may be performed. The dispersion of the memory cells is changed as shown in Fig. 11 (c). The voltage level of the second program voltage Vpgm2 is a value obtained by adding the offset voltage Voff to the voltage level of the first program voltage Vpgm1. The offset voltage Voff may be equal to the threshold voltage range dVth2 of the second cell group G2 and the threshold voltage range dVth3 of the third cell group G3. The second program voltage Vpgm2 is applied to the memory cells of the second cell group G2 and the third cell group G3 except for the first cell group G1 already included in the target distribution TP1, The threshold voltage distribution of the two-cell group G2 and the third cell group G3 can move to the right. On the other hand, if the second program voltage Vpgm2 is applied to the memory cells of the second cell group G3, the second cell group G3 may be over programmed. The threshold voltage of the distribution of the memory cells of the second cell group G3 may be higher than the threshold voltage of the target distribution TP1. In order to prevent this, the programming speed of the second cell group G2 can be slowed down by applying the forcing voltage VBLF to the bit lines of the memory cells of the second cell group G2. For example, the level of the forcing voltage VBLF may be lower than the level of the inhigh voltage. For example, the level of the forcing voltage VBLF may correspond to the threshold voltage range dVth3 of the third cell group G3. Accordingly, the second cell group G2 and the third cell group G3 are divided into the target cell group TP1 (TP1) and the second cell group G2 (cell group G2) by performing the secondary program PGM2 on the basis of the second program voltage Vpgm2 and the forcing voltage VBLF, ). Thereby, the memory cells can be programmed in the first program state P1.

13 is a diagram for explaining the programming method according to the embodiment of the present disclosure in more detail. FIG. 13 illustrates the programming method according to FIG. 11 and FIG. 12 in more detail, and the description with reference to FIG. 11 and FIG. 12 can be applied to the embodiment of FIG.

Referring to FIG. 13, a first program voltage is applied to a word line to which memory cells are connected, a first program is performed on the memory cells (S310), and the memory cells are programmed (S320). ≪ / RTI > Steps S310 and S320 are the same as steps S210 and S220 of FIG. 10, and a detailed description thereof will be omitted.

After dividing the memory cells into three cell groups, a second program (S330) may be performed.

Inhibit voltage is applied to the bit line of the memory cells of the first cell group (S331). The distribution of the first cell group may be included in the target distribution of the target program state. Thus, the program for the first cell group no longer proceeds. An inhigh voltage may be applied to the bit line of the memory cells of the first cell group to prevent the reprogramming from being performed for the first cell group.

A forcing voltage is applied to the bit lines of the memory cells of the second cell group (S332).

The dispersion of the second cell group and the third cell group is different in the position and range of scattering on the threshold voltage. In order to simultaneously program the second cell group and the third cell group in the target state, a forcing voltage is applied to the bit line of the memory cells of the second cell group having a relatively high program speed to slow the program speed.

Then, the second program voltage is applied to the word line (S343). The second program voltage is a voltage at which the voltage level is increased by the offset voltage from the first program voltage, that is, from the first program voltage, and the offset voltage is based on the threshold voltage range of the second cell group and the threshold voltage range of the third cell group . For example, the offset voltage is equal to the sum of the threshold voltage range of the second cell group and the threshold voltage range of the third cell group.

In one embodiment, the application of the inhavit voltage (S331) and the application of the forcing voltage (S332) can be performed simultaneously. Furthermore, the inhighbing voltage application (S331), the forcing voltage application (S332), and the second program voltage application (S343) can be performed simultaneously.

14A and 14B are diagrams for explaining a method of operating the memory device according to the embodiment of the present disclosure. FIG. 14A shows a method of dividing memory cells into five cell groups according to a program speed based on one-shot distribution of memory cells, and FIG. 14B shows a program voltage applied to a plurality of cell groups.

Referring to FIG. 14A, based on the one-shot distribution of memory cells, memory cells can be divided into five cell groups MCG1 to MCG5 according to the program speed. The threshold voltage ranges of the five cell groups (MCG1 to MCG5) may be different from each other.

For example, the threshold voltage range (dVth1 to dVth5) may be set in inverse proportion to the number of memory cells (hereinafter, referred to as unit cell number) included in the unit threshold voltage range of each cell group. According to the illustrated one-shot shot, the number of unit cells of the third cell group MCG3 may be greater than the number of unit cells of relatively different cell groups. Therefore, the threshold voltage range dVth3 of the third cell group MCG3 can be set to be narrower than the threshold voltage range of other cell groups. On the contrary, the number of unit cells of the edge area of the one-shot scattering, for example, the first cell group MCG1 or the fifth cell group MCG5, is smaller than the number of unit cells of relatively different cell groups. Therefore, the threshold voltage range dVthl of the one cell group MCG1 or the threshold voltage range dVth5 of the fifth cell group MCG5 can be set to be wider than the threshold voltage range of the other cell groups.

As described above, the memory cells divided into the five cell groups MCG1 MCG5 whose threshold voltage ranges are set to be different from each other are selected based on the threshold voltage difference or the threshold voltage range (dVth1 to dVth5) of the plurality of cell groups MCG1 to MCG5 And can be reprogrammed to the target program state Pn based on a plurality of secondary program voltages Vpgm2 to Vpgm5 to be set.

14B, the first program voltage Vpgm1 may be a predetermined voltage such that at least some of the memory cells are included in the target distribution TP of the target state Pn. In an embodiment, the first program voltage Vpgm1 may be a preset voltage such that the memory cells of the top cell group, e.g., the first cell group MCG1, of the one-shot scatter are included in the target spread TP.

The second to fifth program voltages Vpgm2 to Vpgm5 may be voltages whose voltage levels are sequentially increased from the first program voltage Vpgm1. Offset voltages Voff1 to Voff4 between the program voltages Vpgm1 to Vpgm5 In other words, the voltage increase amount is based on the threshold voltage difference or the threshold voltage range (dVth2 to dVth5) of the second to fifth cell groups MCG2 to MCG5 . In the embodiment, the offset voltages Voff1 to Voff4 may be proportional to the threshold voltage range (dVth2 to dVth5). In the embodiment, the offset voltages Voff1 to Voff4 may be equal to the threshold voltage range (dVth2 to dVth5), respectively. Accordingly, the second offset voltage Voff2 may be relatively small, and the fourth offset voltage Voff4 may be relatively large.

15 (a) to (f) are graphs showing steps of an example of the program method according to the embodiment of the present disclosure. 16 is a waveform diagram of a voltage applied to a word line connected to a memory cell programmed in FIG.

Referring to Figs. 15A and 16, a first program PGM1 is executed. The first program voltage Vpgm1 may be applied to the memory cells in the erase state E. Thereby, a one-shot dispersion of the memory cells according to the first program voltage Vpgm1 is formed. The upper region of the one-shot scatter (right region of the one-shot scatter) may be included in the target scatter TP1 of the first program state P1.

Referring to FIG. 15B, the memory cells are divided into five cell groups (G1 to G5) according to the programming speed, based on the threshold voltages of the memory cells. In one embodiment, the memory cells can be divided into five cell groups (G1 to G5) by sequentially reading the memory cells based on at least four verify voltages. In another embodiment, as shown in FIG. 16, memory memory cells can be divided into five cell groups (G1 to G5) through at least two verification steps (VF1, VF2).

In this embodiment, it is assumed that memory memory cells are divided into five cell groups (G1 to G5) through at least two verification steps (VF1 and VF2) as shown in FIG. In the first verification step VF1, the memory cells can be divided into three cell groups by verifying and reading the memory cells based on the first verification voltage Vrf1 and the second verification voltage Vrf2. The memory cells may be divided into a first cell group G1, a second cell group G2 and a remaining cell group G3, G4 and G5.

Thereafter, the second program VPGM2 is executed. The second program voltage Vpgm2 is applied to the memory cells of the second cell group G2 and the remaining cell groups G3 to G5 excluding the first cell group G1 included in the target distribution TP1, The dispersion of the cells is changed as shown in Fig. 15 (C). The voltage level of the second program voltage Vpgm2 is a value obtained by adding the first offset voltage Voff1 to the voltage level of the first program voltage Vpgm1. The first offset voltage Voff1 may be equal to the threshold voltage range dVth2 of the second cell group G2. The threshold voltage distribution of the second to fifth cell groups G2 to G5 moves to the right and the second cell group G2 can be included in the target dispersion TP1.

Next, the third program (VPGM3) is executed. The third program voltage Vpgm3 is applied to the memory cells of the remaining cell groups, for example, the third to fifth cell groups G3 to G5, so that the dispersion of the memory cells is changed as shown in Fig. 15 (d). The third cell group G3 may be included in the target spread TP1. The voltage level of the third program voltage Vpgm3 is a value obtained by adding the second offset voltage Voff2 to the voltage level of the secondary program voltage Vpgm2. The second offset voltage Voff2 may be equal to the threshold voltage range dVth3 of the third cell group G3. The second offset voltage Voff2 may be smaller than the first offset voltage Voff1. Accordingly, the shift width of the distribution of the memory cells according to the third program VPGM3 may be smaller than the shift width of the distribution of the memory cells according to the second program VPGM2.

Next, the secondary verification (VF2) is performed. The memory cells can be divided into three cell groups by verifying and reading the memory cells based on the first verify voltage Vrf1 and the second verify voltage Vrf2. The memory cells may be divided into first to third cell groups G1 to G3, a fourth cell group G4 and a fifth cell group G5 included in the target spread TP1. In one embodiment, the memory cells of the remaining cell groups (G3 to G5) except for the first cell group (G1) and the second cell group (G2) are verified and read, May be divided into a third cell group G3, a fourth cell group G4, and a fifth cell group G5. In this case, power consumption due to verification reading can be reduced.

Thereafter, the fourth program PGM4 is performed. The fourth program voltage Vpgm4 is applied to the memory cells of the fourth cell group G4 and the fifth cell group G5 excluding the first to third cell groups G1 to G3 included in the target distribution TP1 , The distribution of the memory cells is changed, as shown in Fig. 15 (e). The voltage level of the fourth program voltage Vpgm4 is a value obtained by adding the third offset voltage Voff3 to the voltage level of the third program voltage Vpgm3. The third offset voltage Voff3 may be equal to the threshold voltage range dVth4 of the fourth cell group G4. The threshold voltage distributions of the fourth cell group G4 and the fifth cell group G5 move to the right and the fourth cell group G4 can be included in the target cell population TP1.

Next, the fifth program (VPGM5) is executed. The fifth program voltage Vpgm5 is applied to the remaining cell groups not included in the target distribution TP1, that is, the memory cells of the fifth cell group G5, so that the dispersion of the memory cells is as shown in Fig. 15 (f) . The voltage level of the fifth program voltage Vpgm5 is a value obtained by adding the fourth offset voltage Voff4 to the voltage level of the fourth program voltage Vpgm4. The fourth offset voltage Voff4 may be equal to the threshold voltage range dVth5 of the fifth cell group G5. The fourth offset voltage Voff4 may be relatively larger than other offsets. Therefore, the shift range of the memory cells according to the fifth program VPGM5 can be relatively larger than the second to fourth programs VPGM2 to VPMG4. Accordingly, the fifth cell group G5 may be included in the target spread TP1. Thereby, the memory cells can be programmed in the first program state P1.

17A to 17D are graphs showing steps of an example of the programming method according to the embodiment of the present disclosure. 18 is a waveform diagram of a voltage applied to a word line connected to a memory cell programmed in Fig.

The programming method according to Figs. 17 (a) to 17 (d) (f). However, in the programming method according to the present embodiment, in the second program step PGM2 and the third program PGM3 step, two cell groups may be included in the target spread TP1. Referring to FIG. 17 (b) and the second program step PGM2 in FIG. 18, in the second program step PGM2, the first forcing voltage VBF1 is applied to the memory cells in the second cell group G2 , And the second program voltage Vpgm2 to the memory cells of the second to fifth cell groups G2 to G5. Accordingly, the memory cells of the second cell group G2 and the third cell group G3 can be included in the target spread TP1. At this time, the voltage level of the second program voltage Vpgm2 may be increased from the first program voltage Vpgm1 by the first offset voltage Voff1. The first offset voltage Voff1 may be equal to the sum of the threshold voltage range dVth2 of the second cell group G2 and the threshold voltage range dVth3 of the third cell group G3, VBLF1 may be equal to the threshold voltage range dVth3 of the third cell group G3.

Referring to FIG. 17C and the third program step PGM3 in FIG. 18, in the third program step PGM3, the second forcing voltage VBF2 is applied to the memory cells of the fourth cell group G4 And the third program voltage Vpgm3 may be applied to the memory cells of the fourth and fifth cell groups G4 and G5. Accordingly, the memory cells of the fourth cell group G3 and the fifth cell group G5 may be included in the target spread TP1. At this time, the voltage level of the third program voltage Vpgm3 may be increased from the second program voltage Vpgm2 by the second offset voltage Voff2. The second offset voltage Voff2 may be equal to the sum of the threshold voltage range dVth4 of the fourth cell group G4 and the threshold voltage range dVth3 of the fifth cell group G5, VBLF2 may be equal to the threshold voltage range dVth5 of the fifth cell group G5.

In this way, the memory cells can be programmed to a target program state, e.g., a first program state P1, wherein at least two cell groups can be simultaneously included in a target distribution (TP) in the second and third program steps By programming, the program steps can be reduced.

19 is a flow chart illustrating a method of operating a memory device in accordance with an embodiment of the present disclosure. 19 is a diagram for explaining the operation method of the memory device of FIG. 17 in more detail.

Referring to FIG. 19, a first program is executed by applying a first program voltage, that is, a first program voltage, to a word line to which memory cells are connected (S410). The scattering of a portion of the memory cells may be included in the target scatter.

Thereafter, the memory cells on which the first program has been executed can be divided into three cell groups according to the program speed based on the threshold voltage (S420). For example, the memory cells can be divided into first, second, and remaining cell groups. By validating and reading memory cells based on a preset verify voltage, memory cells can be divided into three cell groups. For example, the memory cells can be divided into three cell groups based on the first and second verify voltages Vrf1 and Vrf2. The threshold voltage of the first cell group may be the highest and the threshold voltage of the remaining cell group may be the lowest. At this time, the higher the threshold voltage of the memory cells, the faster the programming speed of the memory cells may be. Thus, the memory cells can be divided into three cell groups according to the program speed.

Thereafter, a second program may be performed for the second and remaining cell groups (S430). At this time, the first cell group, which is the cell group having the highest threshold voltage, may be included in the target scatter. Accordingly, in order to prevent the program from being executed for the first cell group, an inhigh voltage may be applied to the bit line of the memory cells of the first cell group (S431).

The second program can be performed by applying a first forcing voltage to the bit line of the memory cells of the second cell group (S432) and applying a second program voltage to the word line (S433). The moving width of the scattering of the second cell group should be smaller than the moving width of the scattering of the remaining cell group. Thus, by applying a forcing voltage to the bit lines of the memory cells of the second cell group, the programming speed of the second cell group can be slowed down. Thus, based on the second program voltage, the memory cells of the second cell group and some of the remaining cell groups, such as the third cell group, can be simultaneously programmed into the target program state. The voltage level of the second program voltage may be a level increased from the first program voltage by the first offset voltage. The first offset voltage may be equal to the sum of the threshold voltage range of the second cell group and the threshold voltage range of the third cell group having a relatively high threshold voltage among the remaining cell groups, And may be equal to the threshold voltage range of the three-cell group.

Next, the memory cells may be divided into three cell groups according to the threshold voltage (S440). In the embodiment, the memory cells can be divided into three cell groups based on the above-described first and second verification voltages Vrf1 and Vrf2, for example.

In an embodiment, the remaining cell groups may be divided into the third, fourth, and fifth cell groups by reading out the remaining cell groups. At this time, the memory cells of the third cell group may be included in the target scatter.

The third program may be executed for the memory cells of the fourth and fifth cell groups (S450). In order to prevent the program from being executed on the memory cells of the first cell group, the second cell group and the third cell group already included in the target scatter, the bit line of the memory cells of the first through third cell groups (S451).

A forging voltage is applied to the bit line of the memory cells of the fourth cell group (S452), and a third program voltage is applied to the word line (S453). The moving width of the scattering of the fourth cell group should be smaller than the moving width of the scattering of the fifth cell group. Thus, by applying the forcing voltage to the bit line of the memory cells of the fourth cell group, the programming speed of the fourth cell group can be slowed down. Thus, based on the third program voltage, the memory cells of the fourth cell group and the fifth cell group can be simultaneously programmed into the target program state. The voltage level of the third program voltage may be a level increased from the second program voltage by the second offset voltage. The second offset voltage may be equal to the sum of the threshold voltage range of the fourth cell group and the threshold voltage range of the fifth cell group and the second forcing voltage may be equal to the threshold voltage range of the fifth cell group.

After the first program is executed for all of the memory cells set to be programmed in the first program state, the memory cells are divided into five cell groups according to the program speed, and for the other cell groups except for the first cell group It is possible to perform reprogramming in units of two cell groups.

20 is a flow diagram illustrating a method of operating a memory device in accordance with an embodiment of the present disclosure. 20 shows a programming method when the memory device stores two bits of data in each of the memory cells. Figure 21 shows the threshold voltage distribution of memory cells in accordance with each program state.

Referring to FIG. 20, the memory device 100 (FIG. 1) may perform a program operation according to an embodiment of the present disclosure when receiving multi-bit data and program instructions from an external device, for example, a memory controller (S510).

The memory device may program the memory cells to a first program state based on the first program voltage set (S520). The first program voltage set may comprise first through n th program voltages for programming the memory cells into a first program state. The first program voltage is a first program voltage, and the second through n-th program voltages are a plurality of secondary program voltages. For example, as shown in FIG. 5A, when the memory cells are programmed by dividing into three groups of cells according to the program speed, the first program voltage set may include first to third program voltages. In another embodiment, the first program voltage set may comprise first and second program voltages and a forcing voltage.

At this time, the first program voltage may be a predetermined voltage such that at least some of the memory cells are included in the target distribution of the target programmed state. In one embodiment, when the memory cells are divided into a plurality of cell groups after the primary program is executed, the first program voltage may be pre-programmed such that the memory cells of the top- It may be a set voltage. The second to n-th program voltages may be a voltage set according to a threshold voltage difference between a plurality of cell groups.

When the program for the first program state is completed, the memory device may program the memory cells to a second program state based on the second program voltage set (530). The second program voltage set may comprise first through n th program voltages for programming the memory cells into a second program state.

In one embodiment, the memory device may program memory cells of some of the memory cells programmed into the first program state to a second program state. In another embodiment, the memory device may program memory cells different from the memory cells programmed in the first program state to a second program state.

When the program for the second program state is completed, the memory device may program the memory cells to a third program state based on the third program voltage set (S540). The third program voltage set may comprise first through n th program voltages for programming the memory cells into a third program state.

In one embodiment, the memory device may program memory cells of some of the memory cells programmed into the second program state to a third program state. In another embodiment, the memory device may program memory cells different from the memory cells programmed into the first and second program states into a third program state.

On the other hand, the first program voltage for each program state, i.e., the voltage level of the primary program voltage, can be set by the first program voltage of the previous program state and the program offset.

As shown in FIG. 21, when the threshold voltage difference between the second program state P2 and the first program state P1 is the second program offset VoffP2, the first program for the second program state P2 The voltage level of the voltage Vpgm12 may be set based on the first program voltage Vpgm11 and the second program offset VoffP2 for the first programmed state P1. When the threshold voltage difference between the third program state P3 and the second program state P2 is the third program offset VoffP3, the first program voltage Vpgm13 for the third program state P3 is The first program voltage Vpgm12 and the third program offset VoffP3 for the two program states P2.

Meanwhile, the program method according to the embodiment of the present disclosure described with reference to Figs. 5A to 19 can be applied to each program step (S520, S530, S540). In each of the program stages, the memory cells in which the first program is executed according to the first program voltage, that is, the first program voltage, are divided into a plurality of cell groups according to the program speed, A plurality of secondary program voltages set corresponding to the range may be applied to the memory cell group not included in the target scatter, so that the program can be executed.

When the memory cells are programmed in a plurality of program states and when programming in the ISPP scheme, when the threshold voltage difference between the two program states is relatively large, the program frequency is increased compared to the case where the threshold voltage difference between the two program states is relatively small . However, according to the operation method of the memory device according to the embodiment of the present disclosure, since the program voltage corresponding to each program state is set in advance and the memory cells are programmed in each program state based on the preset program voltage, The memory cells can be programmed according to a preset program number regardless of the threshold voltage difference between states.

22 is an example of a method of operating a memory device according to an embodiment of the present disclosure, and is a waveform showing a voltage pulse applied to a word line.

22 shows how the memory cells are programmed in sequence in the first program state P1, the second program state P2 and the third program state P3 in the case where the memory cell is a multi-bit cell storing two bits of data .

Referring to FIG. 22, the program step of the memory device may include a first program period P1 PGM, a second program period P2 PGM, and a third program period P3 PGM.

When the command for requesting the storage of the multi-bit data and the multi-bit data is received from the outside (for example, the memory controller), the memory cells are programmed to the first program state in the first program period P1 PGM, P2 PGM) may be programmed in the second program state, and the memory cells in the third program period (P3 PGM) may be programmed in the third program state. Thereby, the multi-bit data can be stored in memory cells, e.g., pages, connected to one word line of the memory cell array (110 in FIG. 1).

Each program section, i. E., Each program loop, may include at least two program steps, e. G., A first and a second program step, and a verification read step (VF). FIG. 22 shows, but is not limited to, two program steps and one verification read step in each program section. The program number or the number of verification readout times can be further increased depending on whether the memory cells are divided into several cell groups according to the program speed or whether a bit line forging program is executed for some cell groups.

On the other hand, the program step and the verification reading step, which are performed in each program section, can be performed as described with reference to Figs. 5A to 19. In the verify reading step (VF), the memory cells on which the first program has been executed are divided into a plurality of cell groups according to the program speed based on the primary program voltage, and a plurality of cells (E.g., perform a second program and a third program) based on a plurality of secondary program voltages, e.g., a second and a third program voltage, for which a voltage level is set based on the threshold voltage range of the group, The cells can be programmed to be included in the target distribution of each program state.

On the other hand, in each program period, the voltage levels of the primary program voltages Vpgm11, Vpgm12, and Vpgm13 may be determined according to the primary program voltage of the previous program period and the program offset of each program state. At this time, the program offset means a threshold voltage difference between program states, as shown in FIG. For example, in the second program period P2 PGM, the voltage level of the primary program voltage Vpgm12 is equal to the voltage level of the first program voltage Vpgm11 in the first program period P1 PGM at the second program offset VoffP2 ) May be added. In the third program period P3 PGM, the voltage level of the primary program voltage Vpgm13 is a value obtained by adding the third program offset VoffP3 to the primary program voltage Vpgm12 in the second program period P1 PGM .

On the other hand, after the memory cells are programmed to the third program state, a verify read operation can be performed. It is possible to determine whether the memory cells are normally programmed through the verify read operation. In one embodiment, a verify read operation may be performed on the third program state. If it is determined that the memory cells are normally programmed to the third program state, it can be determined that the other memory cells are also normally programmed to the first program state or the second program state. However, the present invention is not limited thereto, and in another embodiment, a verify read operation may be performed for each of the first to third program states.

23 is an example of a method of operating a memory device according to an embodiment of the present disclosure, and is a waveform showing a voltage pulse applied to a word line.

23 shows how the memory cells are programmed in sequence in a first program state P1, a second program state P2 and a third program state P3 in the case where the memory cell is a multi-bit cell storing two bits of data . The programming method of Fig. 23 is similar to the programming method of Fig. However, in FIG. 23, in the verify reading step VF of the first program period (P1 PGM) for programming the memory cells into the first program state, the memory cells are divided into a plurality of cell groups according to the program speed, The cell group corresponding to each can be stored in the register. For example, when a plurality of cell groups includes first to third cell groups, a first cell group is designated as a fast cell, a second cell group as a normal cell, and a third cell group as a slow cell, Cell, a normal cell, and a slow cell. For example, the information may be stored in a register included in the program controller (e.g., 160 in FIG. 1).

Accordingly, in the second program period P2 PGM and the third program period P3 PGM, the first program voltages Vpgm12 and Vpg12 are applied and then the first program period P1 PGM is performed without the verification readout step. Programmed by applying a second program voltage Vpgm22, Vpgm23 to memory cells other than memory cells classified as a first cell group, e.g., a fast cell.

FIG. 24 is a flow chart showing another example of the programming method according to the embodiment of the present disclosure, and FIGS. 25A to 25C are graphs showing the threshold voltage distribution of the word line according to each step in the flowchart of FIG. 24 shows a programming method for reducing the coupling effect between adjacent word lines in the programming method according to the embodiment of the present disclosure. The program method of Fig. 24 is a modification of the program method of Figs. 5A to 19. Therefore, the contents described with reference to Figs. 5A to 19 can be applied to this embodiment.

Referring to FIG. 24, an initial program (1st PGM) is performed on memory cells of the n-th (n is an integer) word line WLn (S610). At this time, the initial program stage (1st PGM) may include applying a primary programming voltage to the memory cells. Thus, a one-shot dispersion of memory cells according to the primary programming voltage can be formed. At this time, the primary program voltage may include a plurality of first program voltages corresponding to each of a plurality of program states corresponding to the multi-bit data stored in the memory cells. In one embodiment, the plurality of first program voltages may be a voltage that is set such that less than m memory cells having relatively fast program rates among the memory cells of the nth word line are programmed in corresponding program states, respectively. The initial programming step (1st PGM) may include sequentially applying the plurality of first program voltages to the nth word line (WLn). Thus, as shown in Fig. 25A, a one-shot scatter of memory cells for each program state, e.g., the first to third program states P1, P2, and P3, can be formed.

Thereafter, an initial program (1st PGM) is performed on the memory cells of the (n + 1) th word line WLn + 1 (S620). The (n + 1) th word line WLn + 1 may be a word line arranged adjacent to the nth word line WLn and a program line later than the nth word line WLn. a corresponding plurality of first program voltages may be applied to the (n + 1) th word line (WLn + 1), and as shown in FIG. 25A for the A one-shot dispersion of the memory cells of the +1 th word line WLn + 1 may be formed. At this time, coupling of the memory cells of the nth word line WLn may occur by programming the memory cells of the (n + 1) th word line WLn + 1. Accordingly, as shown in Fig. 25B, the one-shot scatter corresponding to each program state of the memory cells of the n-th word line WLn can move to the right.

Next, a secondary program (2nd PGM) is performed on the memory cells of the nth word line WLn (S630). The second program step (2nd PGM) includes a step (VF) of dividing the memory cells of the nth word line (WLn) into a plurality of cell groups having different threshold voltage spreading widths based on the program speed, Based on a plurality of secondary program voltages that are set based on a threshold voltage difference between the cell groups of the plurality of cell groups, for example, among the plurality of cell groups, And reprogramming other cell groups (PGM2). In one embodiment, the first cell group having the highest threshold voltage offset among the plurality of cell groups may include m or m or more memory cells.

In one embodiment, the late program step (2nd PGM) may further comprise a verify read step of determining whether the memory cells of the nth word line WLn are normally programmed to the corresponding program state.

According to the present embodiment, an initial program (1st PGM) is applied to the memory cells of the (n + 1) th word line WLn + 1 before the execution of the second program PGM at the time of executing the program for the nth word line WLn. (2nd PGM) on the memory cells of the n-th word line WLn based on the one-shot dispersion of the memory cells of the n-th word line WLn in which the coupling effect is reflected in advance, It is possible to prevent the shift of the threshold voltage of each program state due to the Wraith human coupling effect.

Figures 26A and 26B are diagrams showing initial programming steps and late programming steps for memory cells of a word line. 2-bit data is stored in the memory cells, and the memory cells are programmed in the first to third program states.

26A and 26B, the first program voltage corresponding to each of the first to third program states is sequentially applied to the memory cells of the word line (e.g., the n-th word line WLn) The initial programs PGM11, PGM12, and PGM13 (1st PGM) corresponding to the respective program states can be performed.

Thereafter, in the memory cells of the word line, the late program (2nd PGM) may be performed. At this time, as shown in FIG. 26A, the verification readout step and the reprogramming step for each program state can be performed in order. For example, the verification readout step (VF_1) for the first program state and the reprogramming step (e.g., the second program step (PGM21)) are performed to complete the program for the memory cells programmed in the first program state, The program for the memory cells programmed in the second program state is completed by performing the verify readout step VF_2 for the second program state and the reprogram step (e.g., the second program step PGM22), and finally, The program for the memory cells programmed in the third program state can be completed by performing the verify readout step VF_3 and the reprogramming step (e.g., the second program step PGM23) for the three program states.

As another embodiment, after the verification read-out step (VF_1, VF2, VF3) for each program state is performed in the late program step (2nd PGM) as shown in Fig. 26B, A program step (e.g., a second program step (PGM21, PGM22, PGM3) for each program state may be performed.

27 is a flowchart showing another example of the program method according to the embodiment of the present disclosure. The programming method of Fig. 27 is similar to that of Figs. 25A to 25C. However, as shown in FIG. 14A, in the step of dividing the memory cells into a plurality of cell groups according to the program speed, when the memory cells are divided into at least five cell groups, as shown in FIG. 27, A plurality of verification readout steps and a plurality of reprogramming steps.

28 shows a programming method of a memory cell array according to an embodiment of the present disclosure. In one embodiment, the memory cell array may comprise a two-dimensional memory cell array.

Referring to FIG. 28, the memory cell array may include a plurality of memory blocks including a plurality of word lines, for example, first to eighth word lines WL1 to WL8. In one embodiment, the first to eighth word lines WL1 to WL8 may be arranged in turn adjacent to each other, and the program may be executed in the order of the first word line WL1 to the eighth word line WL8 have.

At this time, in order to reduce the coupling effect that occurs as the program is executed for the adjacent word lines, as described above with reference to FIG. 24, when a program is executed for one word line, After the initial program (1st PGM) is performed on the word line, a later program (2nd PGM) may be performed on the word line.

For example, the initial program (1st PGM) may be performed on the memory cells of the first word line WL1 and the initial program (1st PGM) may be performed on the memory cells of the second word line WL2. Thereafter, the program for the memory cells of the first word line WL1 can be completed by performing a later program (2nd PGM) on the memory cells of the first word line WL1.

Next, after the initial program (1st PGM) is performed for the third word line WL3 and the latter program (2nd PGM) is performed for the second word line WL2, The program for the memory cells can be completed.

In this way, it is possible to sequentially program all the word lines, for example, the first to eighth word lines WL1 to WL8.

29 is a graph showing the program speed for each word line.

The horizontal axis represents the word line number, and the vertical axis represents the threshold voltage per word line when a one-shot voltage pulse is applied to program the memory cells in a predetermined state, for example, a pre-program state, on each word line. The higher the threshold voltage, the faster the program speed can be determined.

As shown in FIG. 29, the program speed may be different for each word line. In addition, even if the word line is the same, the program speed can be changed according to the program cycle. As shown in FIG. 29, as the number of program cycles, that is, the number of program and erase operations, is increased, the program speed of the word line can be increased.

If the difference in the word line-specific program speed is large, the spread width of each program state of the programmed memory cells may increase. Therefore, it is necessary to compensate the program speed.

30 is a flow diagram illustrating a method of operating a memory device in accordance with an embodiment of the present disclosure.

Referring to FIG. 30, the memory device (100 of FIG. 1) may receive multi-bit data and program instructions from an external, e.g., memory controller (S710). The memory device may sense the program rate of the word line corresponding to the address at which the program is to be performed (S720).

In one embodiment, the memory device may sense the program rate of the word line by applying a pre-program voltage to the word line on which the program is to be programmed and counting the number of off-cells programmed in the pre-programmed state.

The memory device may set the voltage level of the program voltages by compensating the program speed for each word line to reflect the program speed of the sensed word line (S730). For example, if the program rate of the word line differs from the reference value, a compensation voltage set corresponding to the difference between the sensed program speed and the reference value may be added to the default level of the program voltages.

22, the voltage levels of the program voltages are set based on the primary program voltages Vpgm11, Vpgm12, and Vpgm13 of the respective program states, and the voltage levels of the primary program voltages Vpgm12 May be set based on the primary program voltage Vpgm11 for the first programmed state. Therefore, when setting the voltage level of the primary program voltage Vpgm11 for the first program state, the voltage level of the program voltages compensated for the word line-specific program speed can be set by reflecting the compensation voltage according to the program speed. Thus, a program voltage set for each program state can be set. The program voltage set may comprise a primary program voltage and a plurality of secondary program voltages.

Thereafter, a program for each program state can be performed according to the voltage level of the program voltages reflecting the program speed. The memory cells may be programmed to the nth program state based on the nth program voltage set (S740). For example, when the memory cells are programmed in the first to third program states, the memory cells may be programmed to the first to third program states, respectively, based on the first to third program voltage sets.

31 is a diagram illustrating a program speed sensing and program voltage level compensation method of a word line according to an embodiment of the present disclosure;

31, in order to sense the programming speed of the word line, the memory device may program the memory cells of the word line into the pre-programmed state P0 by applying a one-shot pre-program voltage to the word line . At this time, the memory device can sense the program speed of the word line by counting the number of off cells for the memory cells programmed in the pre-programmed state P0, that is, the pre-programmed state P0.

The pre-programmed state P0 may be a state located between the erased state E and the first programmed state P1. The pre-programmed state P0 is not a state corresponding to the multi-bit data stored in the memory cells, and may be any state for detecting the program speed of the word line.

The number of off-cells in the counted pre-programmed state may correspond to the program rate of the word line. The larger the number of off-cells, the faster the program speed. The memory device can determine the program speed based on the number of off-cells and apply the compensation voltage corresponding to the program speed when setting the voltage level of the program voltages.

In one embodiment, a memory device, e.g., a program controller (160 of FIG. 1), may include a table storing a compensation voltage according to the number of off cells. The memory device can select a compensation voltage according to the counted number of off-cells with reference to the table, and apply the compensation voltage when setting the program voltage level.

For example, as shown in FIG. 31, a compensation voltage may be applied in setting the start voltage of the program. For example, the program start voltage may be the primary program voltage Vpgm11 in the first programmed state. The voltage level of the primary program voltage Vpgm11 in the first program state can be set by adding the compensation voltage VoffWL according to the program speed of the word line to the program voltage Vdf1 of the default level.

32 is a diagram illustrating a method of setting a program voltage level to reflect a program speed of a word line according to an embodiment of the present disclosure;

Referring to FIG. 32, in the pre-program step (P0 PGM), the program rate of the word line can be sensed by applying a pre-program voltage to the memory cells and counting the number of off-cells in the pre-programmed state through the verify read . Thereafter, in each of the program stages (P1 PGM, P2 PGM, and P3 PGM), the compensation voltage can be applied when setting the program voltage set corresponding to each program stage. For example, the compensation voltage may be applied when the first program voltages Vpgm11, Vpgm12, and Vpgm13 of the respective program stages are set.

33A-33C are graphs showing the threshold voltage distribution of word lines in stages of the programming method according to an embodiment of the present disclosure;

The program method shown in Figs. 33A to 33C is a modification of the program method of Fig. 33A and 33B, an initial program (1st PGM) is performed on the memory cells of the n-th word line WLn and an initial program (1st PGM) is performed on the memory cells of the (n + 1) 1st PGM) can be performed. At this time, the initial program step may include a pre-program step PGM0, a pre-read verification step (VF0), and a step (PGM1) of applying a primary program voltage corresponding to each program step to the memory cells. In the pre-program stage PGM0, the program rate of the word line can be sensed by applying a pre-program voltage to the memory cells and counting the number of off cells for the pre-program state in the pre-read verify step (VF0) . The voltage level of the program voltage set for each program stage can be set based on the compensation voltage according to the program rate of the sensed word line. For example, a compensation voltage may be added to the voltage level of the primary program voltage corresponding to each program step. Thereafter, by applying a primary programming voltage according to each programming step to which a compensating voltage according to the programming speed of the word line is applied to the memory cells to which the pre-program voltage is applied, a one-shot dispersion corresponding to each of the program states is formed .

Thereafter, as shown in FIG. 33, the program can be completed for the memory cells of the n-th word line WLn by performing the latter program (2nd PGM) for the n-th word line WLn. The second program step (2nd PGM) includes a step (VF) of dividing the memory cells of the nth word line (WLn) into a plurality of cell groups having different threshold voltage spreading widths based on the program speed, Based on a plurality of secondary program voltages that are set based on a threshold voltage difference between the cell groups of the plurality of cell groups, for example, among the plurality of cell groups, And reprogramming other cell groups (PGM2). At this time, the plurality of secondary program voltages may be set based on a threshold voltage difference between the plurality of groups and a compensation voltage according to a program speed of the word line.

34 is a flow chart illustrating a method of operation of a memory device in accordance with an embodiment of the present disclosure.

Referring to FIG. 34, the memory cells may be programmed in the (N-1) th program state (N is an integer of 2 or more) (S810). The (N-1) th program state may be a program state among a plurality of program states except for the topmost program state with the highest threshold voltage.

The program speed of the word line may be detected after the memory cells are programmed to the N-1 < th > program state or the N-1 < th > In one embodiment, during a verify read operation for the (N-l) program state, the program rate may be sensed by counting the number of off cells. By counting the number of memory cells of the first cell group having the highest threshold voltage level among the plurality of cell groups when dividing the memory cells into a plurality of cell groups after performing the primary program for the memory cells, The program speed of the line can be detected.

The program voltage for the N-th program state, for example, the voltage level of the N-th program voltage set, may be set based on the compensation voltage according to the detected program speed of the word line (S830). In other words, the compensation voltage according to the program speed of the word line corresponding to the (N-1) th program state may be reflected in the Nth program voltage set.

Accordingly, the memory cells can be programmed to the N-th program state based on the N-th program voltage set in which the compensation voltage according to the program speed of the word line corresponding to the N-1-th program state is reflected (S840).

In one embodiment, the flowchart of FIG. 34 shows an operation method performed after step S730 of FIG.

According to the steps S720 and S730 of FIG. 30 described above, the program speed of the word line is sensed before the execution of the program for the memory cells, so that the program voltage level compensating the program speed of the word line can be set. Thereafter, in accordance with steps S810 and S840 in FIG. 34, the program speed of the word line can be sensed for each program loop, and the program voltage of the next program loop can be reflected on the basis of the program speed.

Referring to Figure 30, the memory device may sense the program rate of the word line (e.g., the initial program rate) and adjust the voltage level of the program voltages based on the word line-by-word program rate prior to program execution for the memory cells . Thus, the word line-specific program speed can be compensated. However, as the program is executed, the program speed of the word line may be changed and the program spread may be increased. According to the operation method according to the present embodiment, the program spreading characteristic can be improved by sensing the program speed of the word line for each program loop and reflecting the compensation voltage according to the program speed to the program voltage of the next program loop.

35 is a diagram showing a method of detecting a program speed of a word line during program execution.

FIG. 35 is a block diagram of a programming method according to an embodiment of the present disclosure described above with reference to FIGS. 5A to 19, when programming memory cells into a plurality of cell groups according to a program speed, .

35, when the memory cells are programmed in the first program state P1, the primary program voltage Vpgm11 may first be applied to the memory cells. At this time, some of the memory cells, e.g., memory cells in the upper region of the one-shot scatter, may be included in the target distribution of the first program state P1.

To distinguish the memory cells into three cell groups, a verify read can be performed. At this time, the number of off-cells for the first program state P1 may be counted to sense the program speed of the word line. For example, the off cells of the first program state P1 may be cells included in the first cell group MCG1.

Thereafter, the memory cells of the memory cells other than the off-cells, for example the second cell group MCG2 and the third cell group MCG3, are reprogrammed so that all the memory cells are programmed to the first program state P1 , Some of the memory cells may be programmed to the second program state P2. At this time, the program voltage level for the second program state P2 may be set. The voltage level of the program voltages for the second program state P2, for example, the voltage level of the second program voltage set, can be set based on the compensation voltage according to the detected program speed during the programming of the first program state P1 have.

The second program offset VoffP2 may be added to the primary program voltage Vpgm11 of the first program state P1 to set the primary program voltage Vpgm12 of the second program state P2, The compensation voltage VoffWL can be further added. Accordingly, the voltage level of the program voltages of the second program state P2 can reflect the program speed of the detected word line in executing the program for the first program state P1.

According to the operation method according to the above-described embodiment of the present disclosure, that is, according to the program method, the program speed of the word line is detected for every program loop, and the detected program speed is reflected on the program voltage of the next program loop , The scattering characteristic of each program state can be improved.

36 illustrates an embodiment of a method of operating a memory device according to an embodiment of the present disclosure.

Referring to FIG. 36, for each program loop, the program rate of the word line can be sensed. When the memory cell is a multi-level cell storing two bits of data, the memory cell can be programmed to one of the first to third program states P1, P2, and P3.

The primary program speed detection (SPD1) may be performed before the program is executed on the memory cells. The voltage level of the program voltages corresponding to the primary program state P1, for example, the primary program voltage (P1) of the primary program state P1, according to the program speed of the word line in accordance with the primary program speed sensing SPD1 Vpgm11) can be adjusted.

Thereafter, during the execution of the program for the first program state P1, the secondary program speed detection SPD2 is performed in the verify read (VF) step and the program speed of the word line according to the secondary program speed detection (SPD2) Accordingly, the voltage level of the program voltages corresponding to the second program state P2 can be adjusted. For example, the voltage level of the primary program voltage Vpgm12 in the secondary program state P2 can be adjusted.

During program execution for the second program state P2, in the verify read (VF) step, third order program velocity detection SPD3 may be performed. Depending on the programming speed of the word line in accordance with the tertiary program speed sensing SPD3, the voltage level of the program voltages corresponding to the tertiary program state P3 can be adjusted. The voltage level of the primary program voltage Vpgm13 in the third program state P3 can be adjusted.

37 is a flow chart illustrating in greater detail an operation method of a memory device according to an embodiment of the present disclosure.

Referring to FIG. 37, a primary program speed sensing for a word line may be performed (S910). The primary program speed sensing may be performed before the program is executed for the memory cells, and the program voltage level for the first program state may be set based on the sensed program speed (S920).

For example, the first compensation voltage VoffWL1 according to the program speed may be reflected in the primary program voltage Vpgm11 in the first program state P1.

By applying the primary program voltage Vpgm11 of the first program state P1 to the memory cells, the memory cells can be primarily programmed to the first program state (S930).

Thereafter, the memory cells can be divided into three cell groups according to the programming speed based on the threshold voltage of the memory cells (S940). At this time, the secondary program speed sensing for the word line may be performed (S950). When the memory cells are divided into three cell groups according to the program speed, the first cell group corresponding to the highest state in the threshold voltage region may be included in the target scatter of the first program state P1. The number of memory cells included in the first cell group may be counted to detect the program speed.

Thereafter, the program for the first program state P1 is continuously executed. (E.g., a second program, a third program, or the like) may be performed on the memory cells such that the spread of the cell group is included in the target distribution of the first program state P1. Whereby the memory cells can be programmed to the first program state P1.

After the program in the first program state P1 is completed, the voltage level of the program voltages for the second program state may be set based on the program speed of the word line in accordance with the second program speed sensing (S970). For example, the second compensation voltage VoffWL2 according to the program speed may be added to the primary program voltage Vpgm12 in the second program state P2.

By applying the primary program voltage Vpgm12 of the second program state P2 to the memory cells, the memory cells can be primarily programmed to target the second program state P2. Thereafter, as described above, the program speed of the word line is sensed for each program step, so that the voltage level of the program voltages of the next program stage can be adjusted.

38 is a block diagram showing an example of a program control unit according to the embodiment of the present disclosure;

In one embodiment, the program control unit 160a may be included in the control logic (150 in FIG. 1). In another embodiment, the program control section 160a may be implemented as a separate functional block.

Referring to FIG. 38, the program control unit 160a may include a program control logic 160-1 and a register 160-2. The program control logic 160-1 may perform operations to set driving voltages for program operation, and the voltage levels of the set driving voltages may be stored in the register 160-2. In addition, the program control logic 160-1 may perform an operation of setting a compensation voltage according to the program speed of the word line, and store the set compensation voltage for each word line in the register 160-2.

In one embodiment, the driving voltages and the compensation voltage per word line may be stored in register 160-2 in tabular form. The register 160-2 includes a first table TB1 including a voltage level of driving voltages, e.g., a default level of driving voltages, and a second table TB2 including a compensation voltage level according to a programming speed of a word line can do.

In one embodiment, the program control logic 160-1 may set a default level of drive voltages before the write request command is received from the memory controller (e.g., an initialization interval, a softer training interval, or the like, of the memory device). Thereafter, when a program command is received, the program speed of the word line to be programmed can be detected, and the level of the compensation voltage VoffWL can be determined according to the program speed.

The voltage level of the driving voltages stored in the first table TB1 may be a default level. When the program is executed for each word line, the compensation voltage VoffWL is applied to the drive voltages of the default level so that the drive voltages can be compensated.

For example, when a multi-bit data and program instruction is received from the memory controller, the program control unit 160 senses the program speed of the word line, and the control logic 160-1 accesses the register 160-2, The voltage levels of the corresponding driving voltages can be set based on the driving voltages of the first table TB1 and the compensation voltage according to the programming speed of the second table TB2. In accordance with the embodiment of the present disclosure, the program control unit 160 detects the program speed of the word line during program execution, and determines a compensation voltage according to the program speed of the second table TB2 based on the detected program speed , It is possible to set the driving voltages for the next program state, for example, the voltage levels of the program voltages. A program control signal CTRL_PGM indicating the voltage level of the driving voltage may be generated and provided to the voltage generator 140 (FIG. 1).

The configuration and functions of the program control unit provided in the memory device have been described above with reference to FIG. However, the above description is an embodiment, and the technical idea of the present disclosure is not limited thereto. The types of driving voltages and compensation voltages stored in the register 160-2 may vary. In addition, the program control unit may perform more various functions for controlling the memory device so that the program can be executed on the memory cell array according to the programming method according to the embodiments of this disclosure.

39 is a block diagram illustrating a memory system in accordance with an embodiment of the present disclosure.

The memory system 1000 may be a computer, a laptop, a cellular phone, a smart phone, an MP3 player, a personal digital assistant (PDA), a portable multimedia player (PMP) A television, a digital camera, a portable game console, and the like.

39, the memory system 1000 may include a memory device 100 and a memory controller 200. The memory device 100 may include a memory cell array 110, control logic 150, and program control 160.

The memory cell array 110 may include a plurality of memory cell blocks and may store data received from the memory controller.

The control logic 150 can entirely control various operations in the memory device 100 based on the command CMD, the address ADDR and the control signal CTRL received from the memory controller 200. [ For example, the control logic 150 may output various control signals to write data to the memory cell array 110 or to read data from the memory cell array 110. [

The program control unit 160 can control the memory device 100 to store multi-bit data in the memory cell array 110. [ The program controller 160 divides the memory cells set to be programmed into one program state into at least three cell groups according to the program rate and applies different program voltages or program numbers to the respective cell groups, The memory device 100 can be controlled so that the cells can be programmed. The program control unit 160 may also detect the word line-specific program rate and adjust the voltage level of the program voltages of each program state applied to the word line, based on the compensation voltage according to the program speed. The program control unit 160 may sense the program speed for each program loop and adjust the voltage level of the program voltages for the next program loop based on the compensation voltage according to the detected program speed. In addition, the program control unit 160 may perform an initial program for an adjacent word line after performing an initial program for the word line, and then execute a program for performing a later program for the word line, By setting the sequence, the coupling effect between adjacent word lines can be reduced. In addition, the program control unit 160 may control the operation of each component of the memory device 100, for example, the memory device 100, so that the program can be executed in accordance with the programming method of the memory device according to the embodiment of the present disclosure described with reference to Figs. A row decoder, an input / output circuit, a voltage generator, and the like.

The memory controller 200 may control the memory device 100 to read the data stored in the memory device 100 or to write data to the memory device 100 in response to a read / write request from the host (HOST) have. Specifically, the memory controller 200 provides the address (ADDR), the command (CMD) and the control signal (CTRL) to the memory device (100) The operation can be controlled. The memory controller 200 can transmit the data (DATA) for the program operation to the memory device 100. [ The memory controller 200 provides the memory device 100 with data (DATA) of a size corresponding to a program unit of the memory device 100, an address ADDR at which the data is stored and a command CMD indicating a write request can do.

Although not shown, the memory controller 200 may include a RAM, a processing unit, a host interface, and a memory interface. The RAM can be used as an operation memory of the processing unit, and the processing unit can control the operation of the memory controller 200. [ The host interface may include a protocol for performing data exchange between the host and the memory controller 200. For example, the memory controller 200 may include various interface protocols such as USB, MMC, PCI-E, Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, SCSI, ESDI, Lt; RTI ID = 0.0 > (HOST) < / RTI >

On the other hand, in another embodiment, some functions of the program control unit 160 may be performed in the memory controller 200. [ For example, the memory controller 200 can control the program operation for the memory cell array 110 of the memory device 100. [ In one embodiment, memory controller 200 also determines a sequence applying the programming method according to embodiments of the present disclosure, and provides control signal CTRL indicative of the sequence to memory device 100 .

For example, the memory device 100 may be provided with a control signal CTRL for controlling the setting of driving voltages for program operation. In addition, the memory controller 200 may determine scatter characteristics and the like of the memory cell array 110, and determine, based on a determination result, how many cell groups are to be classified according to the program speed during program execution. For example, when it is determined that the memory cells in some areas of the memory cell array 110 deteriorate and the scatter characteristics are bad, when the program operation is performed on the memory cells in the area, the number of cell groups The scattering characteristic of the program state can be improved.

In this way, the memory controller 200 can control the memory device 100 such that the programming characteristics of the memory cells of the programmed speed or programmed state of the memory device 100 are improved.

40 is a block diagram illustrating a memory card system in accordance with one embodiment of the present disclosure;

40, the memory card system 2000 may include a host 2100 and a memory card 2200. The host 2100 may include a host controller 2110 and a host interface 2120. The memory card 2200 may include a card connection 2210, a card controller 2220 and a memory device 2220.

The host 2100 can write data to the memory card 2200 or read data stored in the memory card 2200. [ The host controller 2110 can transmit the command CMD and the clock signal CLK and data DATA generated in the clock generator (not shown) in the host 2100 to the memory card 2200 through the host interface 2120 have.

The card controller 2220 may store data in the memory device 2220 in response to a command received via the card connection 2210 in synchronization with a clock signal generated by a clock generator (not shown) within the card controller 2220 have. The memory device 2220 may store the data transmitted from the host 2100. Memory device 2220 may include the memory device (100 of FIG. 1) described above with reference to FIG. 1, and memory device 2220 may include a program according to the embodiment of this disclosure described with reference to FIGS. 5A- (DATA) received from the card controller 2110 according to a method or an operation method. The time for programming the data can be shortened and the operation speed of the memory card 2200 and the operation speed of the memory card system 2000 can be improved as the program scatter characteristic is improved.

The memory card 2220 may be a compact flash card (CFC), a microdrive, a smart media card (SMC) multimedia card (MMC), a security digital card (SDC) Card, a memory stick, and a USB flash memory driver.

41 is a block diagram illustrating a computing system in accordance with one embodiment of the present disclosure.

41, a computing system 3000 may include a memory system 3100, a processor 3200, a RAM 3300, an input / output device 3400, and a power supply 3500. 19, the computing system 3000 may further include ports capable of communicating with, or communicating with, video cards, sound cards, memory cards, USB devices, and the like . The computing system 3000 may be implemented as a personal computer or a portable electronic device such as a notebook computer, a mobile phone, a personal digital assistant (PDA), a camera, and the like.

Processor 3200 may perform certain calculations or tasks. According to an embodiment, the processor 3200 may be a micro-processor, a central processing unit (CPU). Processor 3200 is coupled to RAM 3300, input / output device 3400 and memory system 3100 via a bus 3600, such as an address bus, a control bus, and a data bus, Communication can be performed. In accordance with an embodiment, processor 3200 may also be coupled to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

Memory system 3100 may communicate with processor 3200, RAM 3300, and input / output device 3500 via bus 3600. Memory system 3100 may store received data or provide stored data to processor 3200, RAM 3300, or input / output device 3400, at the request of processor 3200. Meanwhile, the memory system 3100 can be applied to the memory system 1000 described with reference to FIG. Or the memory system 3100 may include the memory device 100 described with reference to Figure 1 and the memory device 3110 may include a programmable method or operation according to the embodiment of the present disclosure described with reference to Figures 5A- The data (DATA) received from the memory controller 3120 may be stored in the memory cell array according to the method. As a result, the time for programming the data can be shortened and the program scattering characteristics can be improved, so that the operating speed of the memory system 3100 and the operating speed of the computing system 3000 can be improved.

The RAM 3300 may store data necessary for the operation of the computing system 3000. For example, the RAM 3300 may be implemented as a DRAM, a mobile DRAM, an SRAM, a PRAM, an FRAM, an RRAM, and / or an MRAM .

The input / output device 3400 may include an input means such as a keyboard, a keypad, a mouse, etc., and an output means such as a printer, a display, and the like. The power supply 3500 may supply the operating voltage required for operation of the computing system 2000.

42 is a block diagram illustrating an SSD system in accordance with one embodiment of the present disclosure;

Referring to FIG. 42, the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 through a signal connector and receives power through a power connector.

The SSD 4200 may include an SSD controller 4210, an auxiliary power supply 4220 and a plurality of memory devices 4230, 4240 and 4250. The plurality of memory devices 4230, 4240, and 4250 may be vertical stacked NAND flash memory devices. At least one of the plurality of memory devices 4230, 4240, 4250 may include the memory device 100 described with reference to FIG. In particular, at least one of the plurality of memory devices 4230, 4240, 4250 receives from the SSD controller 4210 in accordance with the programming method or operating method according to the embodiment of the present disclosure described with reference to Figures 5A- (DATA) can be stored in the memory cell array. Accordingly, the time for programming the data can be shortened and the program scattering characteristics can be improved, so that the operating characteristics of the SSD 4200 can be improved.

43 is a block diagram illustrating a universal flash storage (UFS) according to an embodiment of the present disclosure.

Referring to FIG. 43, the UFS system 5000 may include a UFS host 5100, UFS devices 5200 and 5300, an embedded UFS device 5400, and a removable UFS card 5500. UFS host 5100 may be an application processor of a mobile device. Each of the UFS host 5100, the UFS devices 5200 and 5300, the embedded UFS device 5400, and the removable UFS card 5500 can communicate with external devices by the UFS protocol. At least one of the UFS devices 5200, 5300, the embedded UFS device 5400, and the removable UFS card 5500 can include the memory device 100 shown in FIG. At least one of the UFS devices 5200 and 5300, the embedded UFS device 5400, and the removable UFS card 5500 may also be implemented by a program method according to embodiments of the present disclosure described with reference to FIGS. 5A through 38 . Accordingly, the operation speed of the UFS system 5000 can be improved.

Meanwhile, the embedded UFS device 5400 and the removable UFS card 5500 can communicate by a protocol other than the UFS protocol. The UFS host 5100 and the removable UFS card 5500 can communicate by various card protocols (e.g., UFDs, MMC, SD, mini SD, Micro SD, etc.).

Memory cards, non-volatile memory devices, and card controllers in accordance with embodiments of the present disclosure may be implemented using various types of packages. For example, the flash memory device and / or the memory controller according to the present disclosure may be implemented as a package on package, ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC) Linear Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-Level Fabricated Package (WFP) WSP), and the like.

Although the present disclosure has been described with reference to the embodiments shown in the drawings, it is to be understood that various modifications and equivalent embodiments may be made by those skilled in the art without departing from the scope and spirit of the present invention. Accordingly, the true scope of protection of the present disclosure should be determined by the technical idea of the appended claims.

1000: Memory system
100: memory device
200: Memory controller
160: Program control section

Claims (10)

A method of programming a non-volatile memory device including memory cells storing multi-bit data,
programming the memory cells of the nth word line based on a primary program voltage corresponding to the nth word line;
programming the memory cells of the (n + 1) th word line based on the primary program voltage corresponding to the (n + 1) th word line; And
Wherein the memory cells of the n-th word line are divided into a plurality of cell groups according to a program rate, and based on a plurality of secondary program voltages set based on a threshold voltage difference between the plurality of cell groups, And reprogramming the memory cells of the line to the target state. 2. The method of claim 1,
And a plurality of first program voltages corresponding to each of a plurality of program states corresponding to the multi-bit data,
Programming the memory cells of the nth word line based on the primary voltage comprises:
And sequentially applying the plurality of first program voltages to the memory cells of the nth word line. 3. The method of claim 2, wherein the plurality of program states include first to third program states,
Wherein the plurality of first program voltages are set corresponding to the first to third program states, respectively. 3. The method of claim 2, wherein programming the memory cells of the nth word line based on the primary voltage comprises:
Applying a first primary voltage corresponding to a first program state to the nth word line; And
And applying a second primary voltage corresponding to a second program state to the nth word line. 2. The method of claim 1, wherein reprogramming the memory cells of the nth word line to the target state comprises:
Dividing memory cells of the nth word line into a plurality of cell groups for each of a plurality of program states corresponding to the multi-bit data; And
Based on a plurality of secondary program voltages for each of the plurality of program states set based on a threshold voltage difference between the plurality of cell groups for each of the plurality of program states, And reprogramming to a target state. 6. The method of claim 5, wherein the dividing into the plurality of cell groups comprises:
Dividing memory cells to which the first primary program voltage corresponding to a first program state among the memory cells of the nth word line is applied into a plurality of cell groups for the first program state;
And dividing memory cells to which a second primary program voltage corresponding to a second program state among the memory cells of the nth word line is applied into a plurality of cell groups for the second program state, Lt; RTI ID = 0.0 > volatile < / RTI > memory device. 2. The method of claim 1, wherein reprogramming the memory cells of the nth word line to the target state comprises:
A first memory cell in which a first program voltage corresponding to a first program state of memory cells of the nth word line is applied is divided into a plurality of cell groups, Re-programming the first memory cells; And
A second memory cell in which a second program voltage corresponding to a second program state of the memory cells of the nth word line is applied is divided into a plurality of cell groups, Lt; RTI ID = 0.0 > 1, < / RTI > 2 memory cells. 3. The method of claim 2,
When the primary program voltage corresponding to the n-th word line is set to program each of the memory cells of the n-th word line with less than m memory cells of relatively fast programming speed,
Wherein among the plurality of cell groups of the nth word line, the first cell group having the highest threshold voltage includes m memory cells. The method according to claim 1,
Detecting an initial program rate of the nth word line; And
And adjusting a voltage level of the primary program voltage corresponding to each of a plurality of program states corresponding to the multi-bit data, based on the initial program rate. 10. The method of claim 9, wherein detecting the initial program rate of the nth word line comprises:
Applying a pre-program voltage to the nth word line; And
And counting the number of memory cells detected as off-cells for the pre-programmed state.

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