It is to be understood that both the foregoing general description and the following detailed description are exemplary and should provide a further description of the claimed invention. Reference numerals are shown in detail in the preferred embodiments of the present invention, examples of which are shown in the drawings. Wherever possible, the same reference numbers are used in the description and drawings to refer to the same or like parts.
In the following, a flash memory device as an example of a non-volatile memory device will be used to illustrate the features and functions of the present invention. However, those skilled in the art will readily appreciate other advantages and capabilities of the present invention in accordance with the teachings herein. The invention may also be embodied or applied in other embodiments. In addition, the detailed description may be modified or modified in accordance with the aspects and applications without departing substantially from the scope, spirit and other objects of the invention.
1 is a block diagram illustrating a computer system in accordance with an embodiment of the present invention. Referring to FIG. 1, a computer system 10 according to an embodiment of the present invention includes a host 100 and a storage device 200.
The host 100 performs an access operation such as a write request and a read request to the storage device 200. The host 100 accesses the physical layer 212 provided in the device controller 210 to write data to the storage device 200. [
The storage device 200 may include a device controller 210, a buffer memory 220, and a nonvolatile memory 230. The device controller 210 includes a physical layer 212 for lower level interfacing with the host 100 and a controller 214 for performing data exchange between the physical layer 212 and the buffer memory 220 and the nonvolatile memory 230 ). The physical layer 212 includes a RAM controller 211 for receiving a RAM command CMD_R, a RAM address ADDR_R, and a clock CLK transmitted from the host 100. The physical layer 212 includes a RAM 213 for exchanging data with the host 100 using the data DQ and the data strobe signal DQS. The host 100 can access the nonvolatile memory 230 or the buffer memory 220 by writing the data CMD_N, ADDR_N, DATA and ST in a specific area of the RAM 213. [ Functional areas of the RAM 213 divided by the host 100 will be described later in detail in FIG.
According to the interfacing protocol defined in the physical layer 212 of the host 100 and the storage device 200, the host 100 transfers data in the RAM 213 as a basic transmission unit when writing data. That is, the host 100 writes the data of the basic transmission unit (for example, 512 bytes) to the RAM 213 of the storage device 200 during one writing operation. In this case, even if data of a relatively small size (for example, 16 bytes) is written, 16 bytes which are substantially meaningful data and dummy data of 496 bytes which are invalid are written into the RAM 213. [
The storage device 200 of the present invention can identify a write request of data smaller than the basic transmission unit of the physical layer 212. [ According to the identification result, the sub data can be stored in the device controller 200 rather than the basic transmission unit. The accumulated sub data will be programmed into the nonvolatile memory 230 according to an instruction from the host 100 or its own judgment. The number of programs to the nonvolatile memory 230 can be drastically reduced according to the functions described above. Therefore, by applying the technique of the present invention, it is expected that the lifetime of the storage device 200, which greatly depends on the life of the nonvolatile memory 230, can be remarkably extended. Herein, the sub-data is referred to as sub-data (SD) in the following description.
Illustratively, the storage device 200 is in the form of a dual in-line memory module (DIMM) and may be mounted to a DIMM socket to communicate with the host 1100. That is, the physical layer 212 may perform the interfacing operation defined according to the dual data rate (DDR, DDR2, DDR3, DDR4) protocol.
Figure 2 is a block diagram illustrating an exemplary software layer of the computer system of Figure 1; Referring to FIG. 2, in the host 100, the host layer software 100 'will be activated. And in the storage device 200 the software or firmware 200 'of the non-volatile memory layer will be driven.
Various layers of software may be present in the host layer 100 '. The application program 101 and the operating system 102 may be included in the host upper layer HL1. The application program 101 is software of an upper layer which is driven as a basic service or driven by a user. The operating system 102 will perform control operations on the overall computing system 10, such as file access, application launch, control of the storage device 200 as well as program execution.
The RAM driver 103 or the DIMM layer driver 104 constitutes a host lower layer HL2 for accessing the storage device 200. [ The RAM driver 103 or the DIMM layer driver 104 may be substantially included in the kernel of the operating system. For the access request provided by the host upper layer HL1, the RAM driver 103 performs a control operation for accessing the RAM 213 'of the storage device 200. [ For example, the RAM driver 103 may be a control module for controlling the RAM 213 'of the storage device 200 at the operating system 102 level. When an access request is made in the application program 101 or the operating system 102 to the RAM 213 ', the RAM driver 103 will be called. In addition, the DIMM layer driver 104 together with the RAM driver 103 will be called to support the physical layer level access to the RAM 213 '.
The non-volatile memory layer 200 'includes a memory upper layer ML1 and a memory lower layer ML2. The upper layer memory ML1 controls the access to the nonvolatile memory 230 according to the upper instruction CMD_N and upper address ADDR_N written in the RAM 213 '. The memory upper layer ML1 will be accessed by the controller layer 214 'and the memory management operation to the nonvolatile memory 230 will be performed. For example, control over garbage collection, wear leveling, stream control, etc., to the non-volatile memory 230 may be performed by the controller layer 214 '. On the other hand, in the memory lower layer ML2, interfacing between the RAM 213 'and the host 100 will be performed. That is, the memory lower layer ML2 will perform an operation of reading or writing data of the RAM 213 'provided for the RAM command CMD_R or the RAM address ADDR_R provided through the RAM controller 211. It will be appreciated that the memory lower layer ML2 may also access the RAM 213 'at the request of the upper layer of memory ML1.
The computing system 10 can access the non-volatile memory 230 by software or firmware having the above described hierarchical structure. That is, access to the nonvolatile memory 230 provided in the storage device 200 configured in the DIMM form will be performed by decoding the command word, the address CMD_N, and the address ADDR_N provided through the RAM 213 as an intermediary.
In the present invention, the host lower layer HL2 may transmit the sub-write command to the storage device 200 when a sub-data SD having a size smaller than the minimum transmission unit of the physical layer is requested to be written. Depending on the configuration of the physical layer, the transfer of write data should be transferred in minimum write units. However, when provided with the sub write command (Sub_W_CMD), the sub data SD can be accumulated in the device controller 213. [ The instructions from the host lower hierarchy HL2 and the accumulated sub data SD according to the controller 214's own judgment can be programmed into the nonvolatile memory.
3 is a view showing the physical or logical area of the RAM of FIG. Referring to FIG. 3, the RAM 213 may physically include a plurality of esrams 213_P1, 213_P2,..., 213_Pn. The SLAMs 213_P1, 213_P2, ..., and 213_Pn may be logically divided into at least four regions 213_L1, 213_L2, 213_L3, and 213_L4.
First, physically, the RAM 213 is configured to include at least one Slam. That is, a plurality of esrams 213_P1, 213_P2, ..., 213_Pn. All access to the storage device 200 occurs primarily through the RAM 213. The SLAMs 213_P1, 213_P2, ..., 213_Pn may be arranged in a physical structure capable of optimal access interfacing with respect to the host 100. For example, each of the plurality of esrams 213_P1, 213_P2, ..., and 213_Pn may be allocated to the input / output pin units DQS and DQ of the DIMM. That is, one esram 213_P1 may be assigned to the data input / output pins DQ0 to DQ7 and DQS0, and one esram 213_P2 may be assigned to the data input / output pins DQ8 to DQ15 and DQS1 .
Under the physical structure of the RAM 213, it is logically divided into at least four regions according to its functions. Logically, the RAM 213 can be divided into an instruction area 213_L1, a writing area 213_L2, a reading area 213_L3, and a status area 213_L4. The host physically writes data to the RAM 213 through the RAM command CMD_R and the RAM address ADDR_R in a DIMM interfacing manner. However, the access command and addresses CMD_N and ADDR_N for the nonvolatile memory 230 are transferred to the data input / output pins DQ and DQS and written in the command area 213_L1. In the writing area 213_L2, data to be programmed in the nonvolatile memory 230 is written. In the reading area 213_L3, data requested to be read by the host is read out from the nonvolatile memory 230 and stored. Thereafter, the host refers to the information in the status area 213_L4 and fetches the data stored in the reading area 213_L3. Various status information of the storage device 200 is stored in the status area 213_L4. The host 100 can check and access the state of the storage device 200 through an access such as polling the status area 213_L4.
The sub-write command (Sub_W_CMD) may be provided in the command area 213_L1 of the RAM 213 of the present invention when a write request is made for small-sized sub data. In the writing area 213_L2, valid data requested to be written out among data of one writing unit is stored. When the optimal write data unit to the non-volatile memory 230 is accumulated, the accumulated data will be programmed into the target area of the non-volatile memory 230. [
4 is a block diagram illustrating a method of writing sub data according to the first embodiment of the present invention. Referring to FIG. 4, the host 100 may transmit sub data to the device controller 210 using a sub-write command (Sub_W_CMD). The sub data SD requested to be written by the sub write command Sub_W_CMD is stored in the RAM 213 and then programmed into the nonvolatile memory 230. [
The host 100 will write a general write command (W_CMD, 120) to the command area 213_L1 when writing the data 121 to the storage device 200. [ The sub-data 121 requested to be written will be transmitted to the device controller 210 together with the dummy data 122 as a write unit. At this time, the device controller 210 reads the data 121 requested to be written by the write command word W_CMD from the write area 213_L2 of the RAM 213 and programs the data 121 in the nonvolatile memory 230. The data 121 requested to be written by the general write command W_CMD will always be transferred to the device controller 210 in the basic transfer unit 121 + 122. This is due to the limitation of the physical layer protocol of the host 100 and the storage device 200.
On the other hand, according to the sub-write command (Sub_W_CMD) of the present invention, the storage device 200 can relatively identify the sub data and store the identified sub data in the RAM 213. [ When the sub data is accumulated in a certain size, it will be programmed in the non-volatile memory 230. More specifically, it is as follows.
The host 100 will transmit a write request for the sub data 131 smaller than the basic transmission unit to the device controller 210 using the sub write command Sub_W_CMD 130. [ The host 100 writes the sub write command Sub_W_CMD 130 in the command area 213_L1 of the RAM 213. [ Sub data (131) included in the basic transmission unit is transmitted to the storage device (200). At this time, in the sub-write command 130 written in the command area 213_L1 of the RAM 213, a data offset indicating the position of the sub data 131 in the basic transmission unit, a size of the sub data 131 Information. The device controller 210 refers to the information written in the command area 213_L1 of the RAM 213 and stores the sub data 131 in the writing area 213_L2 of the RAM 213. [ Then, the device controller 210 will hold the program to the non-volatile memory 230 of the sub data 131 stored in the write area 213_L2.
Subsequently, the host 100 will transmit a write request for the subdata 136 to the device controller 210 using the sub-write command (Sub_W_CMD, 135). The host 100 first writes the sub-write command (Sub_W_CMD, 135) in the command area 213_L1 of the RAM 213. [ Sub data 136 constituting the basic transmission unit is transmitted to the storage device 200. At this time, the sub-write command 135 written in the command area 213_L1 of the RAM 213 includes a data offset indicating the position of the sub-data 136 in the basic transmission unit, Lt; / RTI > The device controller 210 refers to the information written in the command area 213_L1 of the RAM 213 and stores the sub data 136 in the writing area 213_L2 of the RAM 213. [ The device controller 210 may program the sub data 131 and 136 stored in the write area 213_L2 in the nonvolatile memory 230. [
The time at which the device controller 210 programs the accumulated sub data 131, 136 in the nonvolatile memory 230 can be controlled in various ways. For example, the program time point of the accumulated sub data may be determined by providing information about when the host 100 starts accumulating sub data and when it ends. Alternatively, the storage device 100 may program itself into the nonvolatile memory 230 with reference to the size of the accumulated subdata. Hereinafter, the features of the present invention will be described, focusing on embodiments in which the host 100 provides the start and end points of accumulation. However, it will be appreciated that the setting of the accumulation starting and ending points of the present invention is not limited to the disclosure herein.
5 is a diagram illustrating a method of writing the sub data of FIG. Referring to FIG. 5, the host 100 transmits a sub write command (Sub_W_CMD) and a write request for sub data to the device controller 210. Then, the device controller 210 accumulates the sub data and combines the accumulated sub data to program it into the non-volatile memory 230.
The host 100 will monitor the occurrence of a write request for the subdata. The host 100 writes a general write command W_CMD in the command area 213_L1 of the RAM 213 when a write request for data having a size equal to or larger than the basic transfer unit or the write unit occurs , The write requested data will be written in the write area 213_L2. On the other hand, when a write request for the first sub data SD1 having a size smaller than the basic transfer unit or the write unit occurs, the host 100 transfers the sub write command Sub_W_CMD to the command area 213_L1 of the RAM 213 And write-requested first sub data SD1 will be written in the write area 213_L2. The write method of the host 100 is also applied to the case where a write request of the second sub data SD2 occurs. The host 100 writes the sub-write command Sub_W_CMD in the command area 213_L1 of the RAM 213 and writes the second sub data SD2 requested to be written in the write area 213_L2. The sub write command Sub_W_CMD may include information such as a data offset indicating the position of the sub data 136 in the write unit and the size of the sub data 136.
In response to a write request using the sub write command Sub_W_CMD of the host 100, the device controller 210 stores the sub data SD1 and SD2 in the write area 213_L2 of the RAM. And, under certain conditions, the device controller 210 will combine the accumulated sub data (SD1, SD2). And the combined sub data SD1 and SD2 will be programmed into the nonvolatile memory 230. [
4 and 5, the host 100 can transmit sub data having a size smaller than the basic transmission unit to the storage device 200 using the sub-write command Sub_W_CMD. Then, the storage apparatus 200 accumulates the write-requested data in the RAM 213 until it reaches a predetermined size, and programs the accumulated subdata in the nonvolatile memory 230. [ According to the writing method for the sub data, the number of times of writing to the non-volatile memory 230 can be drastically reduced. Therefore, it is possible to extend the service life of the storage device 200 depending on the number of times of writing.
6 is a block diagram illustrating a method of writing sub data according to a second embodiment of the present invention. Referring to FIG. 6, the host 100 can control the accumulation and program timing of sub data using the sublight open command (Sub_W_Open) and the sublight close command (Sub_W_Close).
When the host 100 issues a write request for the sub data, the host 100 will transmit the first sub data 141 together with the sub write open command (Sub_W_Open) to the device controller 210 first. The sublight open command (Sub_W_Open) includes a data offset indicating a position in the writing unit of the first sub data 141, data size information, and the like. The host 100 writes the sublight open command Sub_W_Open in the command area 213_L1 of the RAM 213 via the RAM command CMD_R and the RAM address ADDR_R, (213_L2). The device controller 210 refers to the sublight open command Sub_W_Open written in the command area 213_L1 and writes the first sub data 141 to the nonvolatile memory 230 in the writing area 213_L2, The program operation is suspended.
Subsequently, the host 100 will write the sub-write command (Sub_W_CMD) 142 and the second sub data 143 in the command area 213_L1 and the writing area 213_L2 of the RAM 213, respectively. Of course, the sub-write command (Sub_W_CMD) 142 at this time also includes the data offset for the second sub-data 143, data size information, and the like. The device controller 210 refers to the information written in the command area 213_L1 of the RAM 213 and writes the second sub data 143 written in the write area 213_L2 of the RAM 213 to the nonvolatile The program to the memory 230 will be suspended.
Similarly, the host 100 will write the third sub data 145 to the RAM 213 using the sub write command (Sub_W_CMD, 144). The host 100 also writes the fourth sub data 147 in the RAM 213 using the sub write command Sub_W_CMD 146. The device controller 210 holds the program to the nonvolatile memory 230 for the third sub data 145 and the fourth sub data 147 that have been requested to be written by the sub write commands 144 and 146. [
Subsequently, the host 100 will forward the write request for the fifth sub-data 149 to the device controller 210 using a sublight close command (Sub_W_Close, 148). At this time, the sublight close command 148 written in the command area 213_L1 of the RAM 213 will include the data offset and the size information of the fifth data 149. Then, the device controller 210 refers to the sublight close command (Sub_W_Close) 148 written in the command area 213_L1 of the RAM 213 to read the first to fifth sub data 141, 143 and 145 , 147, 149). Then, a program to the nonvolatile memory 230 for the first through fifth combined data 141, 143, 145, 147, and 149 will be performed.
The device controller 210 may read the data previously existing in the nonvolatile memory 230 by referring to the address information when the sublight close command (Sub_W_Close) 148 is provided. The first to fifth sub data 141, 143, 145, 147, and 149 requested to be written and the read data may be merged and then programmed into the nonvolatile memory 230.
In the above, an embodiment has been described in which information on the start and end points of accumulation of small-sized sub data by the host 100 is controlled by the sub write open command (Sub_W_Open) and the sublight close command (Sub_W_Close).
FIG. 7 is a diagram illustrating a method of writing sub data according to the embodiment of FIG. 7, the host 100 controls the accumulation time of the sub data in the RAM 213 using the sub write open command (Sub_W_Open), the sub write command (Sub_W_CMD) and the sublight close command (Sub_W_Close) can do.
First, the host 100 will monitor the occurrence of a write request for sub data rather than a write unit. When a write request for the first sub data SD1 occurs, the host 100 writes the sub write open command Sub_W_Open in the command area 213_L1 of the RAM 213 and writes the first sub data SD1 will write to the write area 213_L2.
Next, a write request for the second sub data SD2 having a size smaller than the write unit (Write Unit) will be generated. Then, the host 100 writes the sub-write command Sub_W_CMD in the command area 213_L1 of the RAM 213 so as to accumulate the second sub data SD2 in the write area 213_L2 together with the first sub data SD1 being stored ). This writing scheme will continue until a sublight close command (Sub_W_Close) is provided.
The host 100 monitors write requests for subdata that are smaller than the basic transmission unit and judges whether the size of the write requested data is a size that can be programmed into the nonvolatile memory 230. [ If it is determined that the combined size of the write-requested sub data SD1 to SDn has reached the appropriate standard, the host 100 transmits the sub-close command Sub_W_Close and the last sub data SDn to the RAM 213 in the command area 213_L1 and the write area 213_L2.
The device controller 210 will accumulate the first sub data SD1 in the write area 213_L2 of the RAM in response to the sublight open command Sub_W_Open. The device controller 210 holds the program to the nonvolatile memory 230 for the sub data SD1 to SDn-1 provided with the sublight open command Sub_W_Open or the sub write commands Sub_W_CMD.
When the sub-close command (Sub_W_Close) is written in the command area 213_L1 of the RAM 213, the device controller 210 causes the stored sub data (SD1 to SDn-1) and the n-th sub data (SDn) something to do. Then, the device controller 210 will program the combined sub data SD1 to SDn into the nonvolatile memory 230. [ However, the device controller 210 may perform a merge operation with the combined data by performing a read operation on the data to be updated by the combined sub-data. At this time, the device controller 210 may program the merged data into the nonvolatile memory 230. [
8 is a flowchart briefly showing the operation of the host for performing the writing method shown in FIG. Referring to FIG. 8, the host 100 will detect a write request for sub data and issue a write command specific to the sub data.
In step S110, the host 100 will detect whether a write request for sub data smaller than a basic transmission unit (Transmission Unit) limited according to the protocol definition of the physical layer occurs. Such a write request for sub data may occur frequently in situations such as updating metadata or writing data of juggling data.
In step S120, the host 100 will issue a sublight open command (Sub_W_Open) when a write request for such sub data occurs for the first time. The sublight open command (Sub_W_Open) may include the offset of the sub data to be written, the size, the address in the nonvolatile memory 230, and the like. On the other hand, if the write request for the sub data is not the first or the last, the host 100 will issue the sub-write command (Sub_W_CMD). The sublight open command (Sub_W_Open) and the sublight command (Sub_W_CMD) are instructions for holding the program to the nonvolatile memory 230 of the corresponding data.
In step S130, the host 100 will determine whether the accumulated size of the transmitted sub data has reached a reference value. The storage size of the data requested to be written through the most recent sub write command Sub_W_CMD from the data requested to be written by the sub write open command Sub_W_Open is compared with the reference value Threshold. If the size of the cumulated SD data is smaller than the threshold value (No direction), the procedure will return to step S110. On the other hand, if the size of the accumulated sub data (Cumulated SD Size) is equal to or larger than the reference value (Yes direction), the procedure moves to step S140.
In step S140, the host 100 will transmit a sublight close command (Sub_W_Close). The host 100 will send a sublight close command (Sub_W_Close) with the last sub data.
The method of transmitting the write request for the small size sub data in the host 100 has been briefly described above.
FIG. 9 is a flowchart showing operations of a storage device according to a write request for sub data of a host. Referring to FIG. 9, the storage device 200 may manage the sub-data requested to be written according to the type of command provided from the host 100.
In step S210, the storage device 200 receives a write command from the host 100. [ The write command provided from the host 100 will be stored in the command area 213_L1 of the RAM 213. [
In step S220, the storage device 200 decodes or parses a write command stored in the command area 213_L1 of the RAM 213 to determine whether it is a sub-write command (Sub_W_CMD). If the received write command W_CMD is not the sub write command Sub_W_CMD (No direction), the procedure will move to step S270. On the other hand, if the received write command W_CMD is the sub write command Sub_W_CMD (Yes direction), the procedure will move to step S230.
In step S230, the storage device 200 will determine the type of write command for the subdata. There are subwrite open commands (Sub_W_Open), sub write commands (Sub_W_CMD), and sublight close commands (Sub_W_Close) as types of these commands. It is possible to perform three operation branches according to the type of the write command for the sub data written in the command area 213_L1 of the RAM 213. [ In the case of the sublight open command (Sub_W_Open), the procedure moves to step S240. In the case of the sub write command (Sub_W_CMD), the procedure moves to step S250. In the case of the sublight close command (Sub_W_Close), the procedure will move to step S260.
In step S240, the storage apparatus 200 starts accumulating the sub data written in the write area 213_L2 of the RAM 213 together with the sublight open command (Sub_W_Open). That is, the storage apparatus 200 will hold the program to the nonvolatile memory 230 and start accumulating the RAM data in the RAM 213, with the sub data SD1 provided with the sublight open command Sub_W_Open.
In step S250, the storage device 200 manages the sub data written in the write area 213_L2 of the RAM 213 together with the sub write command (Sub_W_CMD) in the same program unit as the previously provided sub data. That is, the storage device 200 will identify the valid data by referring to the data offset and store it in the RAM 213. And the data stored in the RAM 213 will be continuously held in the program to the nonvolatile memory 230 until a sublight close command (Sub_W_Close) is provided.
In step S260, the storage device 200 combines the sub data written in the write area 213_L2 of the RAM 213 together with the sublight close command (Sub_W_Close). The storage device 200 will then program the combined sub-data in the area designated in the non-volatile memory 230. [ The storage device 200 may read the corresponding data from the nonvolatile memory 230 when there is data for updating a specific area of the nonvolatile memory 230 among the sub data stored in the RAM 213 will be. The read data and the accumulated data are merged, and the merged data is finally programmed into the nonvolatile memory 230. [
In step S270, since the storage device 200 does not correspond to the write command for the sub data, the data requested to be written will be immediately stored in the RAM 213 and then programmed in the non-volatile memory 230. [
The operation of the storage device 200 with respect to the instruction including the hint information on the management of the sub data has been described above. The storage device 200 can process the sub data according to at least three identifiable commands of the sublight open command Sub_W_Open, the sublight command Sub_W_CMD, and the sublight close command Sub_W_Close. The storage device 200 can significantly reduce the number of programs to the nonvolatile memory 230 through the instruction including the hint information about the processing method for the subdata.
FIG. 10 is a block diagram illustrating further operation of the second embodiment of FIG. 6 of the present invention. Referring to FIG. 10, there is shown a case where write data and a write command of a general basic transmission unit are received during a storage operation for one sub-data.
The host 100 will transmit write commands 150, 152, 154 and 156 to the device controller 210 for writing the sub data 151, 153, 155 and 157 of small size. Particularly, the host 100 writes the second sub-write command 152 and the sub data 153 into the command area 213_L1 and the write area 213_L2 of the RAM 213, To the command area 213_L1, the write command 158 for writing the command.
The storage device 200 writes data to the nonvolatile memory 230 in response to a write command W_CMD for the write unit data 159 provided during the accumulation of the sub data 151, 153, 155, Data 159 is written. The accumulation or combination of the sub data 155 and 157 after the write unit data 159 is programmed into the nonvolatile memory 230 is performed in response to the sub write command 154 and the sublight close command 156 do. That is, in response to the sublight close command 156, the data accumulation will be terminated and the sub data 151, 153, 155, 157 stored in the nonvolatile memory 230 will be programmed.
11 is a block diagram illustrating a method of writing sub data according to a third embodiment of the present invention. Referring to FIG. 11, the host 100 can use a sub write open command (Sub_W_Open) 160 and a sublight close command (Sub_W_Close) 165 as a write command for sub data.
The host 100 notifies the storage device 200 of the start of writing of the sub-data in the sub write open command (Sub_W_Open) 160. [ The host 100 can instruct the storage device 200 to end the accumulation of the sub-data through the sub-close command (Sub_W_Close) 165. [ The host 100 will transmit only the sub data 161, 162, 163, and 164 without a separate command between the sub write open command (Sub_W_Open) 160 and the sublight close command (Sub_W_Close)
When the host 100 issues a write request to the sub data, the host 100 first transmits the first sub data 161 together with the sub write open command 160 (Sub_W_Open) to the device controller 210. The sublight open command (Sub_W_Open) 161 includes a data offset indicating a position in the writing unit of the first sub data 161, size information of data to be transmitted once, and the like. The host 100 writes the subwrite open command Sub_W_Open 161 in the command area 213_L1 of the RAM 213 via the RAM command CMD_R and the RAM address ADDR_R and the first sub data 161 Writing area 213_L2. Then, the device controller 210 refers to the sub write open command (Sub_W_Open) 161 written in the command area 213_L1 to write the first sub data 161 written in the write area 213_L2 to the nonvolatile memory 230).
Subsequently, when a write request for sub data occurs, the host 100 will write the second sub data 162 into the write area 213_L2 of the RAM 213 without providing a separate command. Data offset and data size information for the second sub data 162 have already been defined by the sublight open command (Sub_W_Open) 161. Accordingly, the device controller 210 refers to the data offset and size provided through the sublight open command (Sub_W_Open) 161 until the sublight close command (Sub_W_Close) 166 is written, and outputs the sub data 162, 163, 164 And accumulates it in the RAM 213. [
The host 100 transmits a sublight close command (Sub_W_Close) 166 and the last sub data 165 when it is determined that the sub data of a specific size or larger is written in the RAM 213. Upon receiving the sub-close command (Sub_W_Close) 166 and the last sub data 165, the device controller 210 stops accumulation of the received sub data 161, 162, 163, 164, and 165, The program to the volatile memory 230 is executed. That is, the device controller 210 can execute the program in the nonvolatile memory 230 by combining the sub data 161, 162, 163, 164, and 165 stored in the RAM 213. If the sub data 161, 162, 163, 164, and 165 are update information for the specific data in the non-volatile memory 230, the data to be updated is read from the non-volatile memory 230 and merged It will be appreciated that operation may be performed additionally.
The states 213a, 213b, 213c, 213d and 213e of the write area 213_L2 of the RAM 213 shown in the device controller 210 are written into the states of the sub data 161, 162, 163, 164 and 165 Show the status sequentially. The device controller 210 can identify the sub data by referring to the data offset or data size information defined in the sub write open command (Sub_W_Open) 161, and store the sub data in the RAM 213.
In the above description, the management information about the sub data 161, 162, 163, 164, and 165 is provided by the host 100 only to the sublight open command Sub_W_Open and the sublight close command Sub_W_Close.
12 is a diagram illustrating a method of writing sub data according to the embodiment of FIG. Referring to FIG. 12, the host 100 can control the accumulation time of the sub data in the RAM 213 by using the sub write open command (Sub_W_Open) and the sublight close command (Sub_W_Close).
First, the host 100 will monitor the occurrence of a write request for subdata of a size smaller than a write unit. When a write request for the first sub data SD1 occurs, the host 100 writes the sub write open command Sub_W_Open in the command area 213_L1 of the RAM 213 and writes the first sub data SD1) in the writing area 213_L2. The sublight open command (Sub_W_Open) includes offset information and size information of subdata to be sequentially transmitted.
Then, a write request for the second sub data SD2 will be generated. Then, the host 100 will write the second sub data SD2 into the write area 213_L2 of the RAM 213 without writing any additional command. At this time, the second sub data SD2 can be identified by the offset information and the size information defined in the sublight open command Sub_W_Open in one writing unit. Similarly, for the third sub data SD3, the host 100 also constitutes one write unit and writes the third sub data SD3 in the RAM 213. [
The host 100 may monitor write requests for subdata that are smaller than the basic transmission unit and detect the size of the accumulated subdata. When the size of the detected sub data reaches a certain size, the host 100 will transmit the sub-close command (Sub_W_Close) and the last sub data (SDn) to the storage device 200.
The device controller 210 will store the first sub data SD1 in the write area 213_L2 of the RAM 213 in response to the sublight open command Sub_W_Open. The device controller 210 controls the nonvolatile memory 230 for the sub data SD2 to SDn-1 stored in the write area 213_L2 of the RAM 213 until the sublight close command Sub_W_Close is provided. The program is suspended. When the sub-close command (Sub_W_Close) and the last sub data (SDn) are written in the command area 213_L1 and the write area 213_L2 of the RAM 213, the device controller 210 stores the accumulated sub data SD1- SDn). Then, the device controller 210 will program the combined data SD1 to SDn into the nonvolatile memory 230. [ Although not shown here, the device controller 210 may perform a read operation on the nonvolatile memory 230 and a read operation on the combined data when the combined subdata is data for updating specific data in the nonvolatile memory 230 A merge operation may be performed. And the device controller 210 may program the merged data into the nonvolatile memory 230. [
13 is a flowchart briefly showing the operation of the host for performing the writing method shown in FIG. Referring to FIG. 13, the host 100 will detect a write request for a sub-data of a small size and issue a write command specific to the sub-data.
In step S310, the host 100 will detect whether a write request for sub data smaller than a basic transmission unit (Transmission Unit) limited according to the definition of the physical layer occurs. Such a write request for sub data may occur frequently in situations such as an update of metadata.
In step S320, the host 100 determines whether the write request for the sub data is generated for the first time or is currently being written to the sub data. If it is the write request of the first sub data (No direction), the procedure moves to step S330. On the other hand, if the write operation for the sub data is in progress, the procedure moves to step S340.
In step S330, the host 100 will issue a sublight open command (Sub_W_Open). The sublight open command (Sub_W_Open) may include an offset of data to be written, a data size, an address in the nonvolatile memory 230, and the like. The offset information and size information of the data indicate the position and size information in the writing unit of the sub data to be stored in the writing area 213_L2 of the RAM 213 thereafter. This is because only the data of the write unit including the sub data will be transmitted to the storage device 200 until the sublight close command (Sub_W_Close) is delivered.
In step S340, the host 100 will transmit only sub data to the storage device 200 as a write unit since the write request for the sub data is not the first or last. The host 100 will write the subdata into the storage device 200 at the offset and size defined in the sublite open command Sub_W_Open. Then, the sub data is stored in the write area 213_L2 of the RAM 213 sequentially.
In step S350, the host 100 will determine whether the accumulated size of the transmitted sub data has reached a threshold value. The accumulation size of the most recently written sub data from the data requested to be written by the sub write open command (Sub_W_Open) is compared with the threshold value. If the size of the cumulated SD data is smaller than the threshold value (No direction), the procedure will return to step S310. On the other hand, if the size of the accumulated data (Cumulated SD Size) is equal to or larger than the threshold value (Yes direction), the procedure moves to step S360.
In step S360, the host 100 will transmit a sublight close command (Sub_W_Close). The host 100 may send the sub-close command (Sub_W_Close) and the last sub data together.
In the foregoing, a method of writing a write request for sub data in the storage device 200 by using the sub write open command (Sub_W_Open) and the sublight close command (Sub_W_Close) has been described in the host 100.
14 is a flowchart showing the operation of a storage device according to a write request for sub data of a host. Referring to FIG. 14, the storage device 200 will manage data requested to be written according to the type of command provided from the host 100.
In step S410, the storage device 200 may receive a write command or sub data from the host 100. [ The write command provided from the host 100 will be stored in the command area 213_L1 of the RAM 213. [ And the sub data SD will be stored in the writing area 213_L2 of the RAM 213. [
In step S420, the storage device 200 decodes or parses a write command stored in the command area 213_L1 of the RAM 213 to determine whether it is a write command for the subdata. The storage device 200 determines whether the received write command is a sublight open command (Sub_W_Open), a sublight close command (Sub_W_Close), or sub data transmitted alone without an instruction. If the received write command W_CMD is not a write command related to the sub data (No direction), the procedure will move to step S470. On the other hand, if the received write command W_CMD is for the sub data (Yes direction), the procedure will move to step S430.
In step S430, the storage device 200 will determine the type of write command for the subdata. Types of these commands include a sublight open command (Sub_W_Open) and a sublight close command (Sub_W_Close). In addition, the sub data may be transmitted alone. The type of the write command for the sub data written in the command area 213_L1 of the RAM 213, and the three-way operation branch depending on whether the sub data is transferred alone. In the case of the sublight open command (Sub_W_Open), the procedure moves to step S440. If the sub data is delivered alone, the procedure moves to step S450. In the case of the sublight close command (Sub_W_Close), the procedure will move to step S460.
In step S440, the storage apparatus 200 starts accumulating the sub data written in the write area 213_L2 of the RAM 213 together with the sublight open command (Sub_W_Open). That is, the storage apparatus 200 suspends the program to the nonvolatile memory 230 of the sub data SD1 provided with the sublight open command (Sub_W_Open) and starts accumulating the program in the RAM 213. [
In step S450, the storage device 200 accumulates the sub data delivered alone without instructions, together with the previously stored sub data. That is, the storage apparatus 200 refers to the data offset transmitted through the sublight open command Sub_W_Open, identifies valid data in the write unit, and stores the data in the RAM 213. And the data stored in the RAM 213 will be continuously held in the program to the nonvolatile memory 230 until a sublight close command (Sub_W_Close) is provided.
In step S460, the storage device 200 combines the sub data written in the write area 213_L2 of the RAM 213 together with the sublight close command (Sub_W_Close). And the storage device 200 will program the combined sub-data in the area designated in the non-volatile memory 230. [ The storage device 200 may read the corresponding data from the nonvolatile memory 230 when there is data for updating a specific area of the nonvolatile memory 230 among the sub data stored in the RAM 213 will be. The read data and the accumulated sub data are merged and the merged data is finally programmed into the nonvolatile memory 230. [
In step S470, since the storage device 200 does not correspond to the write command for the sub data, the data requested to be written will be immediately stored in the RAM 213 and then programmed in the non-volatile memory 230. [
In the foregoing, the response of the storage device 200 to the command including the hint information about the sub data has been examined. The storage apparatus 200 can process the sub data using the sublight open command Sub_W_Open and the sublight close command Sub_W_Close. The storage device 200 can significantly reduce the number of programs to the nonvolatile memory 230 through the instruction including the hint information about the processing method for the subdata.
15 is a block diagram illustrating a method of writing sub data according to a fourth embodiment of the present invention. Referring to FIG. 15, the host 100 uses a sublight open command (Sub_W_Open) and a sublight close command (Sub_W_Close) as a write command for sub data. However, unlike in the third embodiment of FIG. 11, these instructions and subdata can be separated into separate transactions. That is, the sub write open command (Sub_W_Open) and the sublight close command (Sub_W_Close) are respectively written to the storage device (200) independently of the transaction separate from the sub data. More specifically, it is as follows.
When the host 100 detects a write request for sub data, it first writes a sub-write command (Sub_W_Open) 170 to the storage device 200. Specifically, the host 100 will write only the sublight open command (Sub_W_Open) in the command area 213_L1 of the RAM 213. [ Here, the sublight open command (Sub_W_Open) includes a data offset indicating a position in a writing unit of each of the subdata and a size information of the subdata transmitted once. Then, the device controller 210 may grasp the intention of the host 100 and permit transmission to the sub data.
The host 100 writes the sub data 171 in the write area 213_L2 of the RAM 213 following the sublight open command Sub_W_Open. When a write request for additional sub data occurs, the host 100 sequentially writes the sub data 171, 172, 173, 174, and 175 into the write area 213_L2 of the RAM 213 without the configuration of the instruction set something to do. Here, since the sub data 171, 172, 173, 174 and 175 stored in the RAM 213 are written via the physical layer, they will be transmitted as a constituent of a write unit.
The sub data 171, 172, 173, 174, 175 requested to be written by the sub write open command Sub_W_Open will be stored and held in the write area of the RAM 213. [ The program to the nonvolatile memory 230 of these sub data 171, 172, 173, 174, and 175 is suspended.
The host 100 will write the sublight close command (Sub_W_Close) 176 into the command area 213_L1 of the RAM 213 when it is determined that data of a specific size or larger has been written into the RAM 213. [ The device controller 210 then identifies the sublight close command (Sub_W_Close) 176 and combines the subdata (171, 172, 173, 174, 175). The combined subdata (171, 172, 173, 174, 175) will be programmed into the nonvolatile memory (230). It will be appreciated that a merge procedure for the combined subdata 171, 172, 173, 174, 175 may additionally be performed.
The states 213a, 213b, 213c, 213d, 213e and 213f of the write area 213_L2 of the RAM 213 shown in the device controller 210 are sub data 171, 172, 173, 174 and 175 And shows the status to be written sequentially. The device controller 210 may identify the sub data by referring to a data offset or data size information defined in the sub write open command (Sub_W_Open) 170, and store the sub data in the RAM 213.
In the above description, the management information about the sub data 171, 172, 173, 174, and 175 is provided by the host 100 only to the sub write open command (Sub_W_Open) and the sublight close command (Sub_W_Close). Particularly, the sub data provided between the sub write open command (Sub_W_Open) and the sublight close command (Sub_W_Close) can be stored in the write area 213_L2 of the RAM 231 . The accumulated sub data in response to the sublight close command (Sub_W_Close) is programmed into the nonvolatile memory 230.
16 is a diagram showing a method of writing the sub data of FIG. Referring to FIG. 16, the host 100 can control the accumulation time of the sub data in the RAM 213 by using the sub write open command (Sub_W_Open) and the sublight close command (Sub_W_Close).
First, the host 100 will monitor the occurrence of a write request for subdata of a size smaller than the basic transmission unit (Transmission Unit). When a write request for the first sub data SD1 occurs, the host 100 writes a sublight open command Sub_W_Open to the storage device 200 first. The sublight open command (Sub_W_Open) includes offset information and size information of subdata to be sequentially transmitted. Although not shown, the host 100 may receive a Permission message from the storage device 200 with respect to the sublight open command Sub_W_Open.
Subsequently, the host 100 will write the first sub data SD1 requested to be written into the write area 213_L2. When a write request for additional sub data occurs, the host 100 transmits the second sub data SD2 in units of writing without an instruction. Then, the second sub data SD2 is stored in the writing area 213_L2 of the RAM 213. [ The sub data SD3, ..., SDn will be sequentially stored in the write area 213_L2 of the RAM 213 in this manner.
The host 100 can monitor the write requests for the sub data smaller than the basic transmission unit and detect the size of the accumulated sub data. When the size of the detected sub data reaches a certain size, the host 100 will transmit the sub-close command (Sub_W_Close) and the last sub data (SDn) to the storage device 200.
The device controller 210 will store the first sub data SD1 in the write area 213_L2 of the RAM 213 in response to the sublight open command Sub_W_Open. The device controller 210 controls the nonvolatile memory 230 for the sub data SD2 to SDn-1 stored in the write area 213_L2 of the RAM 213 until the sublight close command Sub_W_Close is provided. The program is suspended. When the sub-close command (Sub_W_Close) and the last sub data (SDn) are written in the command area 213_L1 and the write area 213_L2 of the RAM 213, the device controller 210 stores the accumulated sub data SD1- SDn). Then, the device controller 210 will program the combined data SD1 to SDn into the nonvolatile memory 230. [ Although not shown here, the device controller 210 may perform a read operation on the nonvolatile memory 230 and a read operation on the combined data when the combined subdata is data for updating specific data in the nonvolatile memory 230 A merge operation may be performed. In this case, the device controller 210 will be able to program the merged data into the non-volatile memory 230.
17 is a block diagram showing a case where a merge operation is added in the embodiment of FIG. Referring to FIG. 17, the host 100 uses a sublight open command (Sub_W_Open) and a sublight close command (Sub_W_Close) as a write command for sub data.
When a write request for sub data is detected, the host 100 first writes the sub write open command (Sub_W_Open, 180) in the storage device 200. Specifically, the host 100 will write the sublight open command (Sub_W_Open, 180) in the command area 213_L1 of the RAM 213. [ Here, the sublight open command (Sub_W_Open) 180 includes a data offset indicating a position in each basic transmission unit of the sub data, size information of the sub data to be transmitted once, and the like.
The host 100 writes the sub data 181 in the write area 213_L2 of the RAM 213 following the sublight open command Sub_W_Open 180. [ When a write request for additional sub data occurs, the host 100 sequentially writes the sub data 181, 182, 183, and 184 in the write area 213_L2 of the RAM 213 without configuring the instruction set . Here, since the sub data 181, 182, 183, and 184 stored in the RAM 213 are written via the physical layer, they will be transmitted as a basic transmission unit.
The sub data 181, 182, 183, and 184 requested to be written by the sub write open command (Sub_W_Open) 180 will be stored and held in the write area of the RAM 213. The program to the nonvolatile memory 230 of these sub data 181, 182, 183 and 184 is held.
The host 100 will write the sublight close command (Sub_W_Close) 185 to the command area 213_L1 of the RAM 213 if it is determined that data of a specific size or larger is written in the RAM 213. [ Then, the device controller 210 can identify the sublight close command (Sub_W_Close) 185 and read the data to be updated by the sub data 181, 182, 183, and 184 from the nonvolatile memory 230. The data read from the nonvolatile memory 230 and the data stored in the RAM 213 will be subjected to a merge operation. The merged data will then be programmed into non-volatile memory 230 again.
In the above description, the management information about the sub data 181, 182, 183, and 184 is provided by the host 100 as the sub write open command (Sub_W_Open) and the sublight close command (Sub_W_Close). In particular, it has been described that the data to be updated by the sub data 181, 182, 183, and 184 stored in the RAM 213 may be programmed after being read from the nonvolatile memory 230 and merged.
18 is a diagram showing a method of writing the sub data of FIG. Referring to FIG. 18, the host 100 can control the accumulation time of the sub data in the RAM 213 by using the sub write open command (Sub_W_Open) and the sublight close command (Sub_W_Close).
First, the host 100 will monitor the occurrence of a write request for subdata of a size smaller than the basic transmission unit. When a write request for the first sub data SD1 occurs, the host 100 writes a sublight open command Sub_W_Open to the storage device 200 first. The sublight open command (Sub_W_Open) includes offset information and size information of subdata to be sequentially transmitted. Although not shown, the host 100 may receive a Permission message from the storage device 200 with respect to the sublight open command Sub_W_Open.
Subsequently, the host 100 will write the first sub data SD1 requested to be written into the write area 213_L2. When a write request for additional sub data occurs, the host 100 transmits the second sub data SD2 in units of writing without an instruction. Then, the second sub data SD2 is stored in the writing area 213_L2 of the RAM 213. [ The sub data SD3, ..., SDn will be sequentially stored in the write area 213_L2 of the RAM 213 in this manner.
The host 100 may monitor the write requests for the sub data rather than the write unit to detect the size of the accumulated sub data. When the size of the detected sub data reaches a certain size, the host 100 will transmit a sublight close command (Sub_W_Close) to the storage device 200.
The device controller 210 will store the first sub data SD1 in the write area 213_L2 of the RAM 213 in response to the sublight open command Sub_W_Open. The device controller 210 stores the program to the nonvolatile memory 230 for the sub data SD2 to SDn stored in the write area 213_L2 of the RAM 213 until the sublight close command Sub_W_Close is provided, . When the sub-close command (Sub_W_Close) is written in the command area 213_L1 of the RAM 213, the device controller 210 can read the data for updating the accumulated sub-data from the nonvolatile memory 230 .
The read data and the accumulated sub data SD1 to SDn will be merged. And the device controller 210 will program the merged data into the non-volatile memory 230. [
FIG. 19 is a block diagram illustrating one of the nonvolatile memories of FIG. 1; FIG. 19, the nonvolatile memory device 230 includes a memory cell array 231, an address decoder 232, a page buffer 233, an input / output circuit 234, and a control logic and voltage generation circuit 235 .
The memory cell array 231 may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings. Each of the plurality of cell strings includes a plurality of memory cells. The plurality of memory cells may be connected to a plurality of word lines WL. Each of the plurality of memory cells may include a single level cell (SLC) storing one bit or a multi level cell (MLC) storing at least two bits.
The address decoder 232 is connected to the memory cell array 231 through a plurality of word lines WL, string selection lines SSL, and ground selection lines GSL. The address decoder 232 can receive the physical address ADDR_P from the external device and decode the received physical address ADDR to drive the plurality of word lines WL. For example, the address decoder 232 decodes the physical address ADDR_P received from the external device and generates at least one word line of the plurality of word lines WL based on the decoded physical address ADDR_P And may drive at least one selected word line. Illustratively, the physical address ADDR_P indicates the physical address of the nonvolatile memory 230 to which the storage address ADDR_S (see FIG. 1) has been converted. The address translation operation described above may be performed by a flash translation layer (FTL) driven by the device controller 210 or the device controller 210. [
The page buffer 233 is connected to the memory cell array 231 through a plurality of bit lines BL. The page buffer 233 controls the bit lines BL so that data (DATA) received from the input / output circuit 234 is stored in the memory cell array 231 under the control of the control logic and voltage generation circuit 235 . The page buffer 233 may read data stored in the memory cell array 110 and transmit the read data to the input / output circuit 234 under the control of the control logic and the voltage generation circuit 235. [ The page buffer 233 can receive data on a page basis from the input / output circuit 234 or read data on a page basis from the memory cell array 231. [
The input / output circuit 234 can receive data (DATA) from an external device and transfer the received data (DATA) to the page buffer 233. Or input / output circuit 234 may receive data (DATA) from page buffer 233 and transfer the received data (DATA) to an external device (e.g., device controller 110). Illustratively, the input / output circuit 160 can transmit and receive data (DATA) with an external device in synchronization with the control signal CTRL.
The control logic and the voltage generating circuit 235 receive the storage command CMD_S and the control signal CTRL from the external device and respond to the received signals by the address decoder 232, the page buffer 233, Lt; RTI ID = 0.0 > 234 < / RTI > For example, control logic and voltage generation circuit 235 may control other components so that data (DATA) is stored in memory cell array 231 in response to signals CMD_S, CTRL. Or the control logic and voltage generation circuit 235 may control other components such that the data (DATA) stored in the memory cell array 231 is transferred to the external device in response to the signals CMD_S and CTRL. Illustratively, the storage command CMD_S received from the external device may be a modified command of the storage command CMD_S of FIG. The control signal CTRL may be a signal that the device controller 110 provides to control the nonvolatile memory 131. [
The control logic and voltage generation circuit 235 may generate various voltages required for the non-volatile memory 131 to operate. For example, the control logic and voltage generation circuit 235 may include a plurality of programmable voltages, a plurality of pass voltages, a plurality of selected read voltages, a plurality of unselected read voltages, a plurality of erase voltages, Can generate various voltages such as voltages. The control logic and voltage generation circuit 235 may provide the various voltages generated to the address decoder 232 or to the substrate of the memory cell array 231.
FIG. 20 is a circuit diagram showing an example of any one of memory blocks included in the memory cell array of FIG. 19; FIG. Illustratively, a memory block BLK1 of a three-dimensional structure will be described with reference to Fig. However, the scope of the present invention is not limited thereto, and other memory blocks included in each of the plurality of nonvolatile memory devices 230 may also have a structure similar to that of the memory block BLK1.
Referring to FIG. 20, the memory block BLK1 includes a plurality of cell strings CS11, CS12, CS21, and CS22. A plurality of cell strings CS11, CS12, CS21, and CS22 may be arranged along a row direction and a column direction to form rows and columns.
For example, the cell strings CS11 and CS12 may be connected to the string selection lines SSL1a and SSL1b to form a first row. The cell strings CS21 and CS22 may be connected to the string selection lines SSL2a and SSL2b to form a second row.
For example, the cell strings CS11 and CS21 may be connected to the first bit line BL1 to form a first column. The cell strings CS12 and CS22 may be connected to the second bit line BL2 to form a second column.
Each of the plurality of cell strings CS11, CS12, CS21, and CS22 includes a plurality of cell transistors. For example, each of the plurality of cell strings CS11, CS12, CS21, and CS22 includes the string selected transistors SSTa and SSTb, the plurality of memory cells MC1 to MC8, the ground selected transistors GSTa and GSTb, And dummy memory cells DMC1, DMC2. Illustratively, each of the plurality of cell transistors included in the plurality of cell strings CS11, CS12, CS21, CS22 may be a charge trap flash (CTF) memory cell.
The plurality of memory cells MC1 to MC8 are connected in series and are stacked in a height direction perpendicular to the plane formed by the row direction and the column direction. The string selected transistors SSTa and SSTb are connected in series and the strings of selected transistors SSTa and SSTb connected in series are provided between the plurality of memory cells MC1 to MC8 and the bit line BL. The ground selected transistors GSTa and GSTb are connected in series and the grounded selected transistors GSTa and GSTb connected in series are provided between the plurality of memory cells MC1 to MC8 and the common source line CSL.
Illustratively, a first dummy memory cell DMC1 may be provided between a plurality of memory cells MC1 to MC8 and ground selected transistors GSTa and GSTb. Illustratively, a second dummy memory cell DMC2 may be provided between the plurality of memory cells MC1 to MC8 and the string selected transistors SSTa and SSTb.
The ground selected transistors GSTa and GSTb of the cell strings CS11, CS12, CS21 and CS22 can be connected in common to the ground selection line GSL. By way of example, the ground selected transistors in the same row can be connected to the same ground select line, and the ground selected transistors in the other row can be connected to different ground select lines. For example, the first ground selected transistors GSTa of the cell strings CS11, CS12 of the first row may be connected to the first ground selection line and the first ground selected transistors GSTa of the cell strings CS21, CS12 of the second row The first ground selected transistors (GSTa) may be connected to the second ground selection line.
Illustratively, although not shown in the drawings, the ground selected transistors provided at the same height from the substrate (not shown) may be connected to the same ground select line, and the ground selected transistors provided at different heights may be connected to another ground select line Can be connected. For example, the first ground selected transistors (GSTa) of the cell strings (CS11, CS12, CS21, CS22) are connected to a first ground selection line and the second ground selection transistors (GSTb) Line. ≪ / RTI >
Memory cells of the same height from the substrate (or ground selected transistors GSTa, GSTb) are commonly connected to the same word line, and memory cells of different heights are connected to different word lines. For example, cell strings The first to eighth memory cells MC8 of the memory cells CS11, CS12, CS21, and CS22 are commonly connected to the first to eighth word lines WL1 to WL8, respectively.
Strings of the same row among the first string selected transistors (SSTa) of the same height are connected to the same string selection line, and the other strings of string selected transistors are connected to another string selection line. For example, the first string selected transistors SSTa of the cell strings CS11 and CS12 of the first row are connected in common with the string selection line SSL1a and the cell strings CS21 and CS22 of the second row ) Are connected in common with the string selection line SSL1a.
Likewise, string selected transistors of the same row of the second string selected transistors (SSTb) of the same height are connected to the same string select line, and the other strings of string selected transistors are connected to different string select lines. For example, the second string selected transistors SSTb of the cell strings CS11, CS12 of the first row are connected in common with the string selection line SSL1b and the cell strings CS21, CS22 of the second row ) Are connected in common with the string selection line SSL2b.
Although not shown in the figure, string selected transistors of cell strings in the same row may be connected in common to the same string select line. For example, the first and second string selected transistors (SSTa, SSTb) of the cell strings CS11, CS12 of the first row may be connected in common to the same string selection line. The first and second string selected transistors (SSTa, SSTb) of the cell strings CS21, CS22 of the second row may be connected in common to the same string selection line.
Illustratively, dummy memory cells of the same height are connected to the same dummy word line, and dummy memory cells of different heights are connected to another dummy word line. For example, the first dummy memory cells DMC1 are connected to the first dummy word line DWL1, and the second dummy memory cells DMC2 are connected to the second dummy word line DWL2.
In the memory block BLK1, reading and writing can be performed line by line. For example, one row of the memory block BLKa may be selected by the string selection lines SSL1a, SSL1b, SSL2a, and SSL2b.
For example, when the string selection lines SSL1a and SSL1b are supplied with the turn-on voltage and the turn-off voltage is supplied to the string selection lines SSL2a and SSL2b, the cell strings CS11, CS12 are connected to the bit lines BL1, BL2. When the turn-on voltage is supplied to the string selection lines SSL2a and SSL2b and the turn-off voltage is supplied to the string selection lines SSL1a and SSL1B, the cell strings CS21 and CS22 of the second row are supplied with bit Connected to the lines BL1 and BL2 and driven. Memory cells of the same height among the memory cells of the cell strings of the row driven by driving the word lines are selected. Read and write operations can be performed on selected memory cells. Selected memory cells may form a physical page unit.
In the first memory block BLK1, erasing may be performed in units of memory blocks or units of subblocks. When erasing is performed in units of memory blocks, all the memory cells MC of the first memory block BLK1 can be erased simultaneously according to one erase request. When performed in units of sub-blocks, some of the memory cells MC of the first memory block BLK1 may be simultaneously erased in response to one erase request, and some of the memory cells MC of the first memory block BLK1 may be erased. A low voltage (e. G., Ground voltage) is applied to the word line connected to the erased memory cells, and the word line connected to the erased memory cells can be floated.
Illustratively, the illustrated memory block BLK1 is exemplary and the number of cell strings may be increased or decreased, and the number of rows and columns comprised by the cell strings may be increased or decreased depending on the number of cell strings have. The number of the cell transistors GST, MC, DMC, SST, etc. of the first memory block BLK1 may be increased or decreased, and the height of the memory block BLK1 may be increased according to the number of cell transistors Or may be reduced. Also, the number of lines (GSL, WL, DWL, SSL, etc.) connected to the cell transistors may be increased or decreased according to the number of cell transistors.
FIG. 21 is a block diagram illustrating a computing system to which a non-volatile memory module according to the present invention is applied. 21, a computing system 1000 includes a processor 1100, RAM modules 1200 and 1250, non-volatile memory modules 1300 and 1305, a chipset 1400, a GPU 1500, an input / 1600, and a storage device 1700.
The processor 1100 may control all operations of the computing system 1000. The processor 1100 may perform various operations performed in the computing system 1000.
The RAM modules 1200 and 1250 and the non-volatile memory modules 1300 and 1305 may be directly connected to the processor 1100. For example, each of the RAM modules 1200 and 1250 and the non-volatile memory modules 1300 and 1305 may have the form of a dual in-line memory module (DIMM). Each of the RAM modules 1200 and 1250 and the non-volatile memory modules 1300 and 1305 may be mounted on a DIMM socket directly connected to the processor 1100 to communicate with the processor 1100. Illustratively, the non-volatile memory modules 1300 and 1305 may be the storage device 200 described with reference to FIGS.
The RAM modules 1200 and 1250 and the non-volatile memory modules 1300 and 1305 can communicate with the processor 1100 through the same interface 1150. [ For example, the non-volatile memory modules 1300 and 1305 and the RAM modules 1200 and 1250 can communicate through the DDR (Double Data Rate) interface 1150. Illustratively, processor 1100 may use RAM modules 1200 and 1250 as operational memory, buffer memory, or cache memory of computing system 1000.
The chipset 1400 is electrically connected to the processor 1100 and can control the hardware of the computing system 1000 under the control of the processor 1100. [ For example, the chipset 1400 may be connected to the GPU 1500, the input / output device 1600, and the storage device 1700 via the main buses, respectively, and may serve as a bridge to the main buses.
The GPU 1500 may perform a series of arithmetic operations to output image data of the computing system 1000. Illustratively, GPU 1500 may be implemented within processor 1100 in a system-on-chip form.
The input / output device 1600 includes various devices that input data or instructions to the computing system 1000 or output data to the outside. For example, the input / output device 1600 may include a user input device such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, Liquid Crystal Display), OLED (Organic Light Emitting Diode) display device, AMOLED (Active Matrix OLED) display device, LED, speaker, motor and the like.
The storage device 1700 may be used as a storage medium of the computing system 1000. Storage device 1600 may include mass storage media such as hard disk drives, SSDs, memory cards, memory sticks, and the like.
Illustratively, non-volatile memory modules 1300 and 1305 may be used by the processor 1100 as a storage medium of the computing system 1000. The interface 1150 between the non-volatile memory modules 1300 and 1305 and the processor 1100 may be a higher speed interface than the interface between the storage device 1700 and the processor 1100. [ That is, the performance of the computing system is improved by the processor 1100 using the nonvolatile memory modules 1300 and 1305 as the storage medium.
FIG. 22 is a block diagram illustrating one of the nonvolatile memory modules of FIG. 21 by way of example. Illustratively, FIG. 22 shows a non-volatile memory module 1300 in the form of a Load Reduced DIMM (LRDIMM). 22 is in the form of a dual in-line memory module (DIMM) and is mounted in a DIMM socket to communicate with the processor 1100 .
22, the non-volatile memory module 1300 includes a device controller 1310, a buffer memory 1320, a non-volatile memory device 1330, and a serial presence detect chip 1340 (SPD) . The device controller 1310 may include a RAM 1311. Illustratively, non-volatile memory device 1330 may include a plurality of non-volatile memories (NVM). Each of the plurality of nonvolatile memories included in the nonvolatile memory device 1330 may be implemented as a separate chip, a separate package, a separate device, or a separate module, respectively. Or non-volatile memory device 1330 may be implemented as a single chip or as a single package.
By way of example, the device controller 1310, the RAM 1311, the buffer memory 1320, and the non-volatile memory device 1330 may include the device controller 210, RAM 213, The buffer memory 220, and the plurality of non-volatile memories 230. [0050]
Illustratively, the device controller 1310 can send and receive a plurality of data signals DQ and a plurality of data strobe signals DQS to and from the processor 1100, and receives a RAM command CMD_R via separate signal lines, The RAM address ADDR_R, and the clock CK.
SPD 1340 may be a programmable read only memory (EEPROM). SPD 1340 may include initial information or device information of non-volatile memory module 1300. Illustratively, SPD 1340 may include initial information or device information such as module type, module configuration, storage capacity, module type, execution environment, etc. of non-volatile memory module 1300. When the computing system including the non-volatile memory module 1300 is booted, the processor 1100 of the computing system can read the SPD 1340 and recognize the non-volatile memory module 1300 based on the SPD 1340. The processor 1100 may use the nonvolatile memory module 1300 as a storage medium based on the SPD 1340.
Illustratively, the SPD 1340 may communicate with the processor 1100 via a Side-Band Communication Channel. The processor 1100 can exchange a side-band signal (SBS) with the SPD 1340 through an additional communication channel. By way of example, the SPD 1340 may communicate with the device controller 1310 via an additional communication channel. Illustratively, the supplemental communication channel may be a channel based on I2C communication. Illustratively, SPD 1340, device controller 1310, and processor 1100 may communicate with each other or exchange information based on I2C communications.
FIG. 23 is a block diagram illustrating one of the nonvolatile memory modules of FIG. 21 by way of example. Illustratively, FIG. 23 is a block diagram of a non-volatile memory module 2300 in the form of a Registered DIMM (RDIMM). Illustratively, the non-volatile memory module 2300 shown in FIG. 23 has the form of a dual in-line memory module (DIMM) and is mounted in a DIMM socket to communicate with the processor 1100 .
23, the non-volatile memory module 2300 includes a device controller 2310, a buffer memory 2320, a non-volatile memory device 2330, a serial presence detect chip 2340 (SPD) And a data buffer circuit 2350. The device controller 2310 includes a RAM 2311. Since the device controller 2310, the RAM 2311, the nonvolatile memory device 2330, and the SPD 2340 have been described with reference to FIGS. 1 and 22, a detailed description thereof will be omitted.
The data buffer circuit 2350 receives information or data from the processor 1100 (see FIG. 21) via the data signal DQ and the data strobe signal DQS and forwards the received information or data to the device controller 2350 . Or the data buffer circuit 2350 may receive information or data from the device controller 2310 and transfer the received information or data to the processor 1100 via the data signal DQ and the data strobe signal DQS.
Illustratively, the data buffer circuit 2350 may include a plurality of data buffers. Each of the plurality of data buffers can exchange data signals DQ and data strobe signals DQS with the processor 1100. Or each of the plurality of data buffers can exchange signals with the device controller 2310. [ Illustratively, each of the plurality of data buffers may operate under the control of a device controller 2310.
Illustratively, the device controller 2310 can manage subdata according to the operating method described with reference to Figs.
24 is a block diagram illustrating another example of a computing system to which the nonvolatile memory module according to the present invention is applied. For the sake of brevity, a detailed description of the components described above is omitted. 24, a computing system 3000 includes a processor 3100, a non-volatile memory module 3200, a chipset 3400, a GPU 3500, an input / output device 3600, and a storage device 3700 . The processor 3100, the chipset 3400, the GPU 3500, the input / output device 3600, and the storage device 3700 are substantially the same as those of FIG. 21, and thus a detailed description thereof will be omitted.
The non-volatile memory module 3200 may be directly coupled to the processor 3100. For example, the non-volatile memory module 3200 may take the form of a dual in-line memory module (DIMM) and may be mounted to a DIMM socket to communicate with the processor 3100.
The non-volatile memory module 3200 may include a control circuit 3210, a non-volatile memory device 3220, and a ram device 3230. Unlike the non-volatile memory modules 1300 and 2300 of FIGS. 21-23, the processor 3100 can access the non-volatile memory device 3220 and the ram device 3230 of the non-volatile memory module 3200, have. As a more detailed example, the control circuit 3210 may store the received data in the non-volatile memory device 3220 or in the RAM device 3230 under the control of the processor 3100. Or control circuitry 3210 may transfer data stored in non-volatile memory device 3220 to processor 3100 or transmit data stored in ram device 3230 to processor 3100 under the control of processor 3100 have. That is, the processor 3100 can recognize the nonvolatile memory device 3220 and the RAM device 3230 included in the nonvolatile memory module 3200, respectively. The processor 3100 may store data in the non-volatile memory device 3220 of the non-volatile memory module 3200 or may read the stored data. Or processor 3100 may store data to or read data from RAM device 3230. [
The processor 3100 may use the non-volatile memory module 3200 of the non-volatile memory module 3200 as a storage medium of the computing system 3000, The RAM device 3230 of the computing system 3000 can be used as the main memory of the computing system 3000. That is, the processor 3100 can selectively access the nonvolatile memory device or the RAM device included in one memory module mounted on one DIMM socket, respectively.
Illustratively, processor 3100 may communicate with non-volatile memory module 3200 via a double data rate (DDR) interface 3300.
25 is a block diagram exemplarily showing the nonvolatile memory module of FIG. Referring to Figure 25, a non-volatile memory module 3200 includes a control circuit 3210, a non-volatile memory device 3220, and a ram device 3220. By way of example, non-volatile memory device 3220 may comprise a plurality of non-volatile memories, and RAM device 3230 may comprise a plurality of DRAMs. By way of example, a plurality of non-volatile memories may be used by the processor 3100 as storage for the computing system 3000. Illustratively, each of the plurality of nonvolatile memories (NVMs) may be implemented as an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase change RAM (PRAM), a ReRAM ), STT-MRAM (Spin-Torque Magnetic RAM), and the like.
The plurality of DRAMs may be used by the processor 3100 as the main memory of the computing system 3000. By way of example, RAM device 3230 may include random access memory devices such as DRAM, SRAM, SDRAM, PRAM, ReRAM, FRAM, MRAM, and the like.
The control circuit 3210 includes a device controller 3211 and an SPD 3212. The device controller 3211 can receive the command CMD, the address ADDR, and the clock CK from the processor 3100. [ The device controller 3211 responds to signals received from the processor 3100 to transfer data received via the data signal DQ and the data strobe signal DQS to the non-volatile memory device 3220 or to the ram device 3230. [ As shown in FIG. Or device controller 3211 responds to signals received from processor 3100 to transfer data stored in non-volatile memory device 3220 or RAM device 3230 to data signal DQ and data strobe signal DQS Lt; RTI ID = 0.0 > 3100 < / RTI >
Illustratively, the processor 3100 may optionally access the non-volatile memory device 3220 or the RAM device 3230 via a command CMD, an address ADDR, or a separate signal or separate information. That is, the processor 3100 can selectively access the non-volatile memory device 3220 or the RAM device 3230 included in the non-volatile memory module 3200. [ By way of example, the device controller 3211 may store subdata in a RAM (not shown) in accordance with the operating method described in FIGS. 1-18, and store the subdata in nonvolatile memory device 3220 Can be programmed.
26 is a block diagram illustrating an exemplary nonvolatile memory module of FIG. Illustratively, the non-volatile memory module 4200 of FIG. 26 has the form of a dual in-line memory module (DIMM) and may be mounted in a DIMM socket to communicate with the processor 3100.
Referring to Figures 24 and 26, the non-volatile memory module 4200 includes a control circuit 4100, a non-volatile memory device 4220, and a ram device 4230. The control circuit 4210 includes a device controller 4211, an SPD 4212, and a data buffer circuit 4213.
The device controller 4211 receives the command CMD, the address ADDR, and the clock CK from the processor 3100. The device controller 4211 may control the non-volatile memory device 4220 or the RAM device 4230 in response to the received signals. For example, as described with reference to FIG. 18, the processor 3100 may selectively access each of the non-volatile memory device 4220 or the RAM device 4230. The device controller 4231 can control the nonvolatile memory device 4220 or the RAM device 4230 under the control of the processor 3100. [
The data buffer circuit 4213 may receive the data signal DQ and the data strobe signal DQS from the processor 3100 and provide the received signals to the device controller 4211 and the RAM device 4230. Or the data buffer circuit 4213 may provide the data received from the device controller 4211 or the RAM device 4230 to the processor 3100 through the data signal DQ and the data strobe signal DQS.
Illustratively, when the processor 3100 stores data in the nonvolatile memory device 4220, the data received via the data signal DQ and the data strobe signal DQS is provided to the device controller 4211, The device controller 4211 can process the received data and provide it to the nonvolatile memory device 4220. [ Or the processor 3100 reads data stored in the nonvolatile memory device 4220, the data buffer circuit 4213 supplies the data provided from the device controller 4211 to the data signal DQ and the data strobe signal DQS, Lt; / RTI > to the processor 3100 via the network interface. Or the processor 3100 stores data in the RAM device 4230 the data received by the data buffer circuit 4213 is provided to the RAM device 4230 and the device controller 4231 receives the received command CMD, The address ADDR, and the clock CK to the RAM device 4230. Or when the processor 3100 reads data stored in the RAM device 4230, the device controller 4231 transfers the received command CMD, the address ADDR and the clock CK to the RAM device 4230 , The RAM device 4230 provides the data to the data buffer circuit 4213 in response to the transmitted signals and the data buffer circuit 4213 supplies the data signal DQ and the data strobe signal DQS, And may provide data to the processor 3100. Illustratively, the device controller 3211 stores the subdata in a RAM (not shown) according to the operating method described in Figures 1-18, and stores the subdata in a non-volatile memory device 4220 Can be programmed. .
FIG. 27 is a block diagram illustrating the nonvolatile memory module of FIG. 24 by way of example. 27, the non-volatile memory module 5200 includes a control circuit 5210, a non-volatile memory device 5220, and a ram device 5230. The control circuit 5210 includes a device controller 5211 and an SPD 5212. The non-volatile memory module 5200 may operate similarly to the non-volatile memory module 4200 of Fig. However, the non-volatile memory module 5200 does not include the data buffer circuit 4213 unlike the non-volatile memory module 4200 of Fig. That is, the nonvolatile memory module 5200 in FIG. 27 directly supplies the data received from the processor 3100 via the data signal DQ and the data strobe signal DQS to the device controller 5211 or the RAM device 5230 can do. The data from the device controller 5211 of the nonvolatile memory module 5200 in FIG. 27 or the data from the RAM device 5230 are supplied to the processor 3100 (FIG. 27) via the data signal DQ and the data strobe signal DQS. ).
Illustratively, the non-volatile memory module 4200 in FIG. 26 is a memory module in the form of an LRDIMM (Load Reduced DIMM), and the non-volatile memory module 5200 in FIG. 27 may be a memory module in the form of a Registered DIMM .
Illustratively, the device controller 5211 stores the subdata in a RAM (not shown) in accordance with the operating method described in FIGS. 1-18, and stores the subdata in nonvolatile memory device 5220 Can be programmed.
28 is a diagram illustrating a server system to which a nonvolatile memory system according to an embodiment of the present invention is applied. Referring to FIG. 28, the server system 6000 may include a plurality of server racks 6100. Each of the plurality of server racks 6100 may include a plurality of non-volatile memory modules 6200. The plurality of non-volatile memory modules 6200 may be directly connected to the processors included in each of the plurality of server racks 6100. For example, the plurality of non-volatile memory modules 6200 may take the form of a dual in-line memory module and may be mounted in a DIMM socket electrically coupled to the processor to communicate with the processor. Illustratively, a plurality of non-volatile memory modules 6200 may be used as storage for the server system 6000. Illustratively, the plurality of non-volatile memory modules 6200 may operate in accordance with the method described with reference to Figs. 1-18.
The nonvolatile memory and / or device controller according to the present invention can be mounted using various types of packages. For example, the non-volatile memory and / or the device controller according to the present invention may be implemented as package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC) Linear Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-Level Fabricated Package (WFP) WSP), and the like.
The embodiments have been disclosed in the drawings and specification as described above. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.