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KR20160116838A - Semiconductor package - Google Patents

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Publication number
KR20160116838A
KR20160116838A KR1020150045141A KR20150045141A KR20160116838A KR 20160116838 A KR20160116838 A KR 20160116838A KR 1020150045141 A KR1020150045141 A KR 1020150045141A KR 20150045141 A KR20150045141 A KR 20150045141A KR 20160116838 A KR20160116838 A KR 20160116838A
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South Korea
Prior art keywords
package
opening
stepped portion
lower package
present
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KR1020150045141A
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Korean (ko)
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KR102382076B1 (en
Inventor
이지행
김동선
류성욱
서현석
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엘지이노텍 주식회사
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Priority to KR1020150045141A priority Critical patent/KR102382076B1/en
Publication of KR20160116838A publication Critical patent/KR20160116838A/en
Priority to KR1020220039119A priority patent/KR20220045128A/en
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Publication of KR102382076B1 publication Critical patent/KR102382076B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/175—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2225/06503—Stacked arrangements of devices
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    • H—ELECTRICITY
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention relates to a semiconductor package which comprises: a lower package; a protection layer including an opening having a step formed on the lower package; a conductive unit formed on a circuit pattern of the lower package exposed through the opening; and an upper package connected to the conductive unit. Therefore, the semiconductor package can reduce manufacturing costs.

Description

반도체 패키지{SEMICONDUCTOR PACKAGE}[0001] SEMICONDUCTOR PACKAGE [0002]

본 발명의 실시예는 반도체 패키지에 관한 것이다.An embodiment of the present invention relates to a semiconductor package.

반도체 기술의 발전과 함께 사용자의 요구에 따라 전자기기는 더욱 소형화/경량화하고 있으며, 이에 따라 동일 또는 이종의 반도체 칩들을 하나의 단위 패키지로 구현하는 멀티칩 패키징(Multi-Chip Packing) 기술이 사용되고 있다.[0003] Along with the development of semiconductor technology, electronic devices have become smaller and lighter in accordance with the demand of users. Accordingly, a multi-chip packaging technology for implementing the same or different kinds of semiconductor chips in one unit package has been used .

이러한 멀티칩 패키징 중 패키지 기판 위에 패키지 기판을 적층하는 스택(stack) 타입을 패키지 온 패키지(Package on Package: PoP)라고 하며, 일반적으로 프로세서 다이가 실장된 하부 패키지와 메모리 다이가 실장된 상부 패키지가 솔더볼 부착(Solder Ball Attach) 방식 등을 통해 상호 접속되는 패키지를 말한다.A stack type in which a package substrate is stacked on a package substrate in a multi-chip package is called a package on package (PoP). In general, a lower package having a processor die mounted thereon and an upper package A solder ball attachment method, or the like.

종래의 패키지 온 패키지형 반도체 패키지는 솔더볼 인쇄 및 리플로우 공정을 통해 두 개의 패키지를 연결하거나, 먼저 하부 패키지를 몰딩한 후 몰딩 부위에 비아(Via)를 형성하고, 솔더볼을 비아 내 인쇄하여 메모리 다이가 실장된 상부 패키지를 리플로우 공정을 통해 연결하는 방식을 적용하고 있다.The conventional package-on-package type semiconductor package has a structure in which two packages are connected through a solder ball printing and reflow process, vias are formed in a molding region after the lower package is first molded, Is connected to the upper package through a reflow process.

종래 기술에 따른 패키지 온 패키지형 반도체 패키지는 고집적 및 고성능 구현을 위해 Die의 실장 개수를 늘리거나 수동소자를 탑재하기 위한 시도가 이루어 지고 있으며, 이를 구현하기 위해서는 패키지 간의 간격을 넓혀야 한다.In the package-on-package type semiconductor package according to the related art, attempts have been made to increase the number of the die or to mount the passive elements in order to realize high integration and high performance.

그러나, 종래 기술에 따른 반도체 패키지는 패키지 간의 간격을 넓히기 위하여 솔더 볼(solder ball)의 크기 또는 높이를 크게 하는 경우에는, 솔더 볼에 크랙(crack) 또는 붕괴가 발생하는 문제점이 있었다.However, in the conventional semiconductor package, when the size or height of the solder ball is increased in order to widen the gap between the packages, cracks or collapse occur in the solder balls.

본 발명은 전술한 문제를 해결하기 위해 안출된 것으로서, 하부 패키지 상의 단차가 생성된 보호층을 통해 미세 피치(pitch)의 인쇄회로기판 및 반도체 패키지를 제공하고, 종래 기술에 비해 구조를 단순화하여 구조적 견고성을 높이고 제조 비용을 절감하고자 한다.SUMMARY OF THE INVENTION The present invention has been conceived to solve the above-mentioned problems, and it is an object of the present invention to provide a printed circuit board and a semiconductor package of fine pitch through a protection layer on which a stepped portion on a lower package is formed, To increase robustness and reduce manufacturing cost.

또한, 본 발명은 상부 패키지와 하부 패키지 간의 간격을 증가시켜 실장되는 칩의 개수를 증가시켜 고밀도를 실현하고, 상부 패키지와 하부 패키지 간의 접합 신뢰성이 우수한 반도체 패키지를 제공하고, 상부 패키지의 적층 시에 안정적인 공정 수율을 확보하고자 한다.It is another object of the present invention to provide a semiconductor package that increases the distance between upper and lower packages to increase the number of mounted chips to realize high density and has excellent bonding reliability between the upper package and the lower package, And to secure stable process yield.

전술한 문제를 해결하기 위한 본 실시예에 따른 반도체 패키지는 하부 패키지; 상기 하부 패키지 상의 단차가 생성된 개구부를 포함하는 보호층; 상기 개구부를 통해 노출되는 상기 하부 패키지의 회로 패턴 상에 형성되는 도전부; 및 상기 도전부와 접속되는 상부 패키지;를 포함한다.A semiconductor package according to this embodiment for solving the above-mentioned problems includes a lower package; A protective layer including an opening in which a step on the lower package is formed; A conductive part formed on a circuit pattern of the lower package exposed through the opening; And an upper package connected to the conductive portion.

본 발명의 다른 일실시예에 따르면, 상기 개구부의 단차는 상기 하부 패키지 측의 제1 단차부; 및 상기 제1 단차부 상의 제2 단차부;를 포함할 수 있다.According to another embodiment of the present invention, the stepped portion of the opening may include a first stepped portion on the side of the lower package; And a second stepped portion on the first stepped portion.

본 발명의 다른 일실시예에 따르면, 상기 제1 단차부의 개구부의 폭은 상기 제2 단차부의 개구부의 폭보다 작게 형성될 수 있다.According to another embodiment of the present invention, the width of the opening of the first step portion may be smaller than the width of the opening portion of the second step portion.

본 발명의 다른 일실시예에 따르면, 상기 도전부는 금속 재료의 범프(bump) 형태로 형성될 수 있다.According to another embodiment of the present invention, the conductive portion may be formed in the form of a bump of a metal material.

본 발명의 다른 일실시예에 따르면, 상기 도전부는 구리(Cu)를 포함할 수 있다.According to another embodiment of the present invention, the conductive portion may include copper (Cu).

본 발명의 다른 일실시예에 따르면, 상기 회로 패턴과 상기 도전부 사이에 형성되는 회로 패턴 연장부;를 더 포함할 수 있다.According to another embodiment of the present invention, a circuit pattern extension portion may be formed between the circuit pattern and the conductive portion.

본 발명의 다른 일실시예에 따르면, 상기 도전부의 높이는 상기 하부 패키지에 실장되는 반도체 칩의 높이보다 크게 형성될 수 있다.According to another embodiment of the present invention, the height of the conductive part may be greater than the height of the semiconductor chip mounted on the lower package.

본 발명의 다른 일실시예에 따르면, 상기 하부 패키지 및 상기 상부 패키지 중 적어도 어느 하나는, 반도체 칩이 실장된 인쇄회로기판을 포함하여 구성될 수 있다.According to another embodiment of the present invention, at least one of the lower package and the upper package may include a printed circuit board on which the semiconductor chip is mounted.

본 발명의 실시예에 따르면, 하부 패키지 상의 단차가 생성된 보호층을 통해 미세 피치(pitch)의 인쇄회로기판 및 반도체 패키지를 제공하고, 종래 기술에 비해 구조를 단순화하여 구조적 견고성을 높이고 제조 비용을 절감할 수 있다.According to the embodiment of the present invention, it is possible to provide a fine pitch printed circuit board and a semiconductor package through the protection layer on which the stepped portion is formed on the lower package, simplify the structure compared to the prior art, Can be saved.

또한, 본 발명의 실시예에 따르면, 상부 패키지와 하부 패키지 간의 간격을 증가시켜 실장되는 칩의 개수를 증가시켜 고밀도를 실현하고, 상부 패키지와 하부 패키지 간의 접합 신뢰성이 우수한 반도체 패키지를 제공할 수 있으며, 상부 패키지의 적층 시에 안정적인 공정 수율을 확보할 수 있다.Also, according to the embodiment of the present invention, it is possible to provide a semiconductor package which realizes high density by increasing the number of chips mounted by increasing the interval between the upper package and the lower package, and having excellent bonding reliability between the upper package and the lower package , It is possible to secure a stable process yield at the time of stacking the upper package.

도 1은 본 발명의 일실시예에 따른 반도체 패키지를 도시한 도면이다.
도 2는 본 발명의 다른 일실시예에 따른 반도체 패키지의 보호층과 도전부를 도시한 도면이다.
도 3 내지 도 6은 본 발명의 일실시예에 따른 반도체 패키지의 제조 방법을 설명하기 위한 도면이다.1 is a view illustrating a semiconductor package according to an embodiment of the present invention.
2 is a view showing a protective layer and a conductive part of a semiconductor package according to another embodiment of the present invention.
3 to 6 are views for explaining a method of manufacturing a semiconductor package according to an embodiment of the present invention.

이하에서는 첨부한 도면을 참조하여 바람직한 본 발명의 일실시예에 대해서 상세히 설명한다. 다만, 실시형태를 설명함에 있어서, 관련된 공지 기능 혹은 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그에 대한 상세한 설명은 생략한다. 또한, 도면에서의 각 구성요소들의 크기는 설명을 위하여 과장될 수 있으며, 실제로 적용되는 크기를 의미하는 것은 아니다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail to avoid unnecessarily obscuring the subject matter of the present invention. In addition, the size of each component in the drawings may be exaggerated for the sake of explanation and does not mean a size actually applied.

도 1은 본 발명의 일실시예에 따른 반도체 패키지를 도시한 도면이다.1 is a view illustrating a semiconductor package according to an embodiment of the present invention.

도 1을 참조하여 본 발명의 일실시예에 따른 반도체 패키지의 구성을 설명하기로 한다.The structure of a semiconductor package according to an embodiment of the present invention will be described with reference to FIG.

도 1에 도시된 바와 같이 본 발명의 일실시예에 따른 반도체 패키지는 상부 패키지(400)가 하부 패키지(300) 상에 적층되어 이들이 서로 전기적으로 연결된 패키지 온 패키지(Package On Package: POP) 타입의 패키지로 구성될 수 있다.As shown in FIG. 1, a semiconductor package according to an embodiment of the present invention includes a package on package (POP) type in which an upper package 400 is stacked on a lower package 300 and electrically connected to each other. Package.

본 발명의 일실시예에 따른 반도체 패키지는 하부 패키지(300), 상부 패키지(400) 및 도전부(500)를 포함하여 구성된다.A semiconductor package according to an embodiment of the present invention includes a lower package 300, an upper package 400, and a conductive part 500.

하부 패키지(300)는 하부 패키지 기판(310) 상에 적어도 하나의 하부 소자(370)가 실장되며, 상부 패키지(400)는 상부 패키지 기판(410) 상에 적어도 하나의 상부 소자(430)가 실장된다. 한편, 상기 소자(340)는 반도체로 구성될 수 있다.The lower package 300 includes at least one lower element 370 mounted on the lower package substrate 310 and the upper package 400 includes at least one upper element 430 mounted on the upper package substrate 410, do. Meanwhile, the device 340 may be formed of a semiconductor.

이때, 상기 하부 패키지 기판(310)과 상부 패키지 기판(410) 중에서 적어도 어느 하나는 인쇄회로기판(PCB)으로 구성될 수 있다.At this time, at least one of the lower package substrate 310 and the upper package substrate 410 may be a printed circuit board (PCB).

일례로서, 하부 패키지(300)는 하부 패키지 기판(310)과, 하부 패키지 기판 상에 실장된 하부 소자(370)를 포함할 수 있다. 하부 소자(370)가 복수개로 구성되는 경우에는 절연 물질층의 개재하에 적층될 수 있다.As an example, the lower package 300 may include a lower package substrate 310 and a lower element 370 mounted on the lower package substrate. When the lower element 370 is composed of a plurality of elements, it may be stacked under the interposition of the insulating material layer.

하부 패키지 기판(310)의 하면에는 반도체 패키지를 외부 장치와 전기적으로 연결시키는 솔더볼 형태의 외부 단자(350)들이 구비될 수 있다.On the lower surface of the lower package substrate 310, solder ball-shaped external terminals 350 for electrically connecting the semiconductor package to an external device may be provided.

유사하게, 상부 패키지(400)는 상부 패키지 기판(410)과, 그리고 상부 패키지 기판(410)의 상면 상에 실장된 상부 소자(430)를 포함할 수 있다. 상기 상부 소자(430)가 복수개로 구성되는 경우에는 절연성 물질막의 개재하에 적층될 수 있다.Similarly, the top package 400 may include an upper package substrate 410 and an upper element 430 mounted on the upper surface of the upper package substrate 410. When the upper elements 430 are constituted by a plurality of elements, they may be stacked under an insulating material layer.

상부 소자(430)와 상부 패키지 기판(410)은 복수개의 본딩 와이어(442)를 통해 서로 전기적으로 연결될 수 있다.The upper element 430 and the upper package substrate 410 may be electrically connected to each other through a plurality of bonding wires 442.

도전부(500)는 상기와 같이 구성되는 하부 패키지(300)에 접속된다.The conductive part 500 is connected to the lower package 300 configured as described above.

이때, 상기 하부 패키지(300)의 기판(310) 상에 회로 패턴(530)이 형성되고, 상기 도전부(510)는 상기 회로 패턴(530) 상에 형성될 수 있다.At this time, a circuit pattern 530 is formed on the substrate 310 of the lower package 300, and the conductive part 510 may be formed on the circuit pattern 530.

보다 상세하게 설명하면, 도 1에 도시된 바와 같이 하부 패키지(300) 상에 보호층(505)이 형성되며, 상기 보호층(505)에는 단차가 형성된 개구부가 형성된다.More specifically, as shown in FIG. 1, a protection layer 505 is formed on the lower package 300, and an opening having a step is formed in the protection layer 505.

이때, 상기 보호층(505)의 개구부의 단차는 제1 단차부(511)와 제2 단차부(512)를 포함하여 구성될 수 있으며, 상기 제1 단차부(511)는 하부 패키지(300) 측에 형성되고, 상기 제2 단차부(512)는 상기 제1 단차부(511) 상에 형성될 수 있다.The opening of the protection layer 505 may include a first stepped portion 511 and a second stepped portion 512. The first stepped portion 511 may be formed on the lower package 300, And the second stepped portion 512 may be formed on the first stepped portion 511. In addition,

한편, 도 1에 도시된 바와 같이 상기 제1 단차부(511)의 개구부의 폭은 상기 제2 단차부(512)의 개구부의 폭보다 작게 형성될 수 있다.1, the width of the opening of the first stepped portion 511 may be smaller than the width of the opening of the second stepped portion 512. Referring to FIG.

상기 도전부(500)는 상기 개구부를 통해 노출되는 회로 패턴(530) 상에 형성될 수 있으며, 상기 도전부(500)의 높이는 상기 하부 패키지(300)에 실장되는 소자(370)의 높이보다 크게 형성될 수 있다.The conductive part 500 may be formed on the circuit pattern 530 exposed through the opening and the height of the conductive part 500 may be greater than the height of the device 370 mounted on the lower package 300 .

이때, 상기 도전부(510)는 금속 재료를 이용해 범프(bump) 형태로 형성될 수 있으며, 상기 금속 재료로는 구리(Cu)를 사용할 수 있다.
At this time, the conductive part 510 may be formed in a bump form using a metal material, and copper (Cu) may be used as the metal material.

도 2는 본 발명의 다른 일실시예에 따른 반도체 패키지의 보호층과 도전부를 도시한 도면이다.2 is a view showing a protective layer and a conductive part of a semiconductor package according to another embodiment of the present invention.

도 2에 도시된 바와 같이 본 발명의 다른 일실시예에 따른 반도체 패키지는 회로 패턴(530), 보호층(505), 회로 패턴 연장부(535) 및 도전부(500)를 포함한다.2, a semiconductor package according to another embodiment of the present invention includes a circuit pattern 530, a protective layer 505, a circuit pattern extension portion 535, and a conductive portion 500.

도 2의 실시예에서는 회로 패턴(530) 상에 보호층(505)이 형성되며, 상기 보호층(505)의 개구부(501)의 단차는 상기 하부 패키지 측의 제1 단차부(511)와 상기 제1 단차부(511) 상의 제2 단차부(512)로 형성된다.2, the protection layer 505 is formed on the circuit pattern 530 and the stepped portion of the opening 501 of the protection layer 505 is separated from the first stepped portion 511 of the lower package side, And a second step 512 on the first step 511.

이때, 상기 제1 단차부(511)의 개구부의 폭은 상기 제2 단차부(512)의 개구부의 폭보다 작게 형성될 수 있다.At this time, the width of the opening of the first stepped portion 511 may be smaller than the width of the opening of the second stepped portion 512.

또한, 상기 회로 패턴(530)에는 회로 패턴 연장부(535)가 형성되어 도전부(500)와 연결될 수 있다.The circuit pattern 530 may include a circuit pattern extension portion 535 and may be connected to the conductive portion 500.

또한, 도 1의 실시예와 마찬가지로 상기 도전부(510)는 금속 재료를 이용해 범프(bump) 형태로 형성될 수 있으며, 상기 금속 재료로는 구리(Cu)를 사용할 수 있다.
Also, as in the embodiment of FIG. 1, the conductive portion 510 may be formed in a bump shape using a metal material, and copper (Cu) may be used as the metal material.

도 3 내지 도 6은 본 발명의 일실시예에 따른 반도체 패키지의 제조 방법을 설명하기 위한 도면이다.3 to 6 are views for explaining a method of manufacturing a semiconductor package according to an embodiment of the present invention.

이후부터는 도 3 내지 도 6을 참조하여 본 발명의 일실시예에 따른 반도체 패키지의 제조 방법을 설명하기 한다.Hereinafter, a method of manufacturing a semiconductor package according to an embodiment of the present invention will be described with reference to FIGS. 3 to 6. FIG.

먼저, 도 3에 도시된 바와 같이 회로 패턴(530)이 형성된 하부 패키지 상에 제1 보호 재료층(510)을 형성한 후, 도 4에 도시된 바와 같이 상기 제1 보호 재료층(510)을 패터닝하여 제1 단차부(511)를 형성한다.First, a first protective material layer 510 is formed on a lower package on which a circuit pattern 530 is formed as shown in FIG. 3, and then the first protective material layer 510 is formed as shown in FIG. And the first stepped portion 511 is formed by patterning.

이후에는, 도 5에 도시된 바와 같이 상기 제1 단차부(511) 상에 제2 보호 재료층(520)을 형성하고, 도 6에 도시된 바와 같이 상기 제2 보호 재료층(520)을 패터닝하여 제2 단차부(521)를 형성하여 개구부(501)에 단차가 형성된 보호층(505)을 완성한다.5, a second protective material layer 520 is formed on the first stepped portion 511, and the second protective material layer 520 is patterned, as shown in FIG. 6, The second stepped portion 521 is formed to complete the protective layer 505 having the stepped portion formed in the opening portion 501.

도 6에 도시된 바와 같이 상기 제1 단차부(511)의 개구부의 폭(d1)은 상기 제2 단차부(512)의 개구부의 폭(d2)보다 작게 형성될 수 있다.The width d1 of the opening of the first stepped portion 511 may be smaller than the width d2 of the opening of the second stepped portion 512 as shown in FIG.

이상에서 설명한 바와 같이, 본 발명의 실시예에 따르면, 하부 패키지 상의 단차가 생성된 보호층을 통해 미세 피치(pitch)의 인쇄회로기판 및 반도체 패키지를 제공하고, 종래 기술에 비해 구조를 단순화하여 구조적 견고성을 높이고 제조 비용을 절감할 수 있다.As described above, according to the embodiment of the present invention, it is possible to provide a fine pitch printed circuit board and a semiconductor package through the protection layer on which the stepped portion on the lower package is formed, It is possible to increase the robustness and reduce the manufacturing cost.

또한, 본 발명의 실시예에 따르면, 상부 패키지와 하부 패키지 간의 간격을 증가시켜 실장되는 칩의 개수를 증가시켜 고밀도를 실현하고, 상부 패키지와 하부 패키지 간의 접합 신뢰성이 우수한 반도체 패키지를 제공할 수 있으며, 상부 패키지의 적층 시에 안정적인 공정 수율을 확보할 수 있다.Also, according to the embodiment of the present invention, it is possible to provide a semiconductor package which realizes high density by increasing the number of chips mounted by increasing the interval between the upper package and the lower package, and having excellent bonding reliability between the upper package and the lower package , It is possible to secure a stable process yield at the time of stacking the upper package.

전술한 바와 같은 본 발명의 상세한 설명에서는 구체적인 실시예에 관해 설명하였다. 그러나 본 발명의 범주에서 벗어나지 않는 한도 내에서는 여러 가지 변형이 가능하다. 본 발명의 기술적 사상은 본 발명의 전술한 실시예에 국한되어 정해져서는 안 되며, 특허청구범위뿐만 아니라 이 특허청구범위와 균등한 것들에 의해 정해져야 한다.In the foregoing detailed description of the present invention, specific examples have been described. However, various modifications are possible within the scope of the present invention. The technical spirit of the present invention should not be limited to the above-described embodiments of the present invention, but should be determined by the claims and equivalents thereof.

300: 하부 패키지
310: 하부 패키지 기판
350: 외부 단자
370: 하부 소자
400: 상부 패키지
410: 상부 패키지 기판
430: 상부 소자
442: 본딩 와이어
501: 개구부
505: 보호층
511: 제1 단차부
521: 제2 단차부
530: 회로 패턴
535: 회로 패턴 연장부300: Lower package
310: Lower package substrate
350: external terminal
370: Lower element
400: upper package
410: upper package substrate
430: upper element
442: Bonding wire
501: opening
505: Protective layer
511: First step
521: Second step
530: Circuit pattern
535: circuit pattern extension part

Claims (8)

하부 패키지;
상기 하부 패키지 상의 단차가 생성된 개구부를 포함하는 보호층;
상기 개구부를 통해 노출되는 상기 하부 패키지의 회로 패턴 상에 형성되는 도전부; 및
상기 도전부와 접속되는 상부 패키지;
를 포함하는 반도체 패키지.Lower package;
A protective layer including an opening in which a step on the lower package is formed;
A conductive part formed on a circuit pattern of the lower package exposed through the opening; And
An upper package connected to the conductive portion;
≪ / RTI > 청구항 1에 있어서,
상기 개구부의 단차는,
상기 하부 패키지 측의 제1 단차부; 및
상기 제1 단차부 상의 제2 단차부;
를 포함하는 반도체 패키지.The method according to claim 1,
The stepped portion of the opening
A first stepped portion on the side of the lower package; And
A second stepped portion on the first stepped portion;
≪ / RTI > 청구항 2에 있어서,
상기 제1 단차부의 개구부의 폭은,
상기 제2 단차부의 개구부의 폭보다 작게 형성되는 반도체 패키지.The method of claim 2,
Wherein a width of the opening of the first step
And the width of the opening of the second step is smaller than the width of the opening of the second step. 청구항 1에 있어서,
상기 도전부는,
금속 재료의 범프(bump) 형태로 형성되는 반도체 패키지.The method according to claim 1,
The conductive part
A semiconductor package formed in a bump shape of a metal material. 청구항 1에 있어서,
상기 도전부는,
구리(Cu)를 포함하는 반도체 패키지.The method according to claim 1,
The conductive part
A semiconductor package comprising copper (Cu). 청구항 1에 있어서,
상기 회로 패턴과 상기 도전부 사이에 형성되는 회로 패턴 연장부;
를 더 포함하는 반도체 패키지.The method according to claim 1,
A circuit pattern extending portion formed between the circuit pattern and the conductive portion;
Further comprising: 청구항 1에 있어서,
상기 도전부의 높이는,
상기 하부 패키지에 실장되는 반도체 칩의 높이보다 크게 형성되는 반도체 패키지.The method according to claim 1,
The height of the conductive portion
Wherein a height of the semiconductor chip mounted on the lower package is greater than a height of the semiconductor chip mounted on the lower package. 청구항 1에 있어서,
상기 하부 패키지 및 상기 상부 패키지 중 적어도 어느 하나는,
반도체 칩이 실장된 인쇄회로기판을 포함하여 구성되는 반도체 패키지.
The method according to claim 1,
Wherein at least one of the lower package and the upper package includes:
A semiconductor package comprising a printed circuit board on which a semiconductor chip is mounted.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11075183B2 (en) 2018-07-05 2021-07-27 Samsung Electronics Co., Ltd. Semiconductor chip and semiconductor package including the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110174527A1 (en) * 2008-06-30 2011-07-21 Masayuki Nagamatsu Element mounting board, semiconductor module, semiconductor device, method for fabricating the element mounting board, and method for fabricating semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110174527A1 (en) * 2008-06-30 2011-07-21 Masayuki Nagamatsu Element mounting board, semiconductor module, semiconductor device, method for fabricating the element mounting board, and method for fabricating semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11075183B2 (en) 2018-07-05 2021-07-27 Samsung Electronics Co., Ltd. Semiconductor chip and semiconductor package including the same
US11764180B2 (en) 2018-07-05 2023-09-19 Samsung Electronics Co., Ltd. Semiconductor device including base pillar, connection pad, and insulation layer disposed on a substrate

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