KR20160111624A - Solar cell and method for manufacturing the same - Google Patents

Abstract

According to an embodiment of the present invention, a solar cell includes: a semiconductor substrate; a tunneling layer including a first part disposed on the semiconductor substrate and a second part partially disposed on the first part; and a semiconductor layer disposed on the tunneling layer. The semiconductor layer includes a concave unit disposed on the second part. The present invention increases efficiency.

Description

SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell and a manufacturing method thereof, and more particularly, to a solar cell having a rear electrode structure and a manufacturing method thereof.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

In such solar cells, various layers and electrodes can be fabricated by design. However, solar cell efficiency can be determined by the design of these various layers and electrodes. In order to commercialize a solar cell, it is required to overcome low efficiency, and a solar cell and a manufacturing method thereof that can maximize the efficiency of the solar cell are required.

The present invention provides a solar cell capable of improving efficiency and a manufacturing method thereof.

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate; A tunneling layer comprising a first portion located on the semiconductor substrate and a second portion located partially on the first portion; And a semiconductor layer overlying the tunneling layer. The semiconductor layer has a concave portion located on the second portion.

A method of manufacturing a solar cell according to an embodiment of the present invention includes: forming a tunneling layer on a semiconductor substrate, the tunneling layer including a first portion and a second portion that is partially located on the first portion; Forming a semiconductor layer overlying the tunneling layer; And partially etching the semiconductor layer located over the second portion to form a recess in the semiconductor layer corresponding to the second portion. In the step of forming the concave portion, an etching solution having a selective etching ratio with respect to the second portion and the semiconductor layer is used.

In the solar cell and the manufacturing method thereof according to the present embodiment, the leakage current flowing between the first conductivity type region and the second conductivity type region is separated and separated by the recesses from the first conductivity type region and the second conductivity type region Can be minimized. Thus, the efficiency of the solar cell can be improved by improving the filling density of the solar cell.

At this time, it is possible to prevent the tunneling layer and the semiconductor substrate from being etched when the recesses are formed by the second portion partially provided in the tunneling layer, thereby preventing the tunneling layer and the semiconductor substrate from being damaged. Thus, a solar cell having excellent efficiency can be manufactured by a simple method.

1 is a cross-sectional view of a solar cell according to an embodiment of the present invention.
2 is a partial rear plan view of the solar cell shown in Fig.
3A to 3M are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
4A and 4B are cross-sectional views illustrating some steps of a method of manufacturing a solar cell according to a modification of the present invention.
5A and 5B are cross-sectional views illustrating some steps of a method of manufacturing a solar cell according to another modification of the present invention.
6 is a cross-sectional view illustrating a solar cell according to another embodiment of the present invention.
7 is a partial cross-sectional view illustrating a solar cell according to another embodiment of the present invention.
8 is a partial cross-sectional view of a solar cell according to a modification of FIG.
9 is a cross-sectional view of a state including a semiconductor layer before forming a recess in the method of manufacturing a solar cell according to the embodiment shown in Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

Hereinafter, a solar cell according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view of a solar cell according to an embodiment of the present invention, and FIG. 2 is a partial rear plan view of the solar cell shown in FIG.

1 and 2, a solar cell 100 according to the present embodiment includes a semiconductor substrate 10 including a base region 110, a tunneling layer 20 formed on one surface of the semiconductor substrate 10, And a semiconductor layer 30 overlying the tunneling layer 20. [ Here, the tunneling layer 20 includes a first portion 201 located on a semiconductor substrate and a second portion 202 partially located on the first portion 201. And the semiconductor layer 30 has a recess 36 located above the second portion 202. [ The recess 36 may be located between the first conductive type region 32 and the second conductive type region 34 constituting the semiconductor layer 30. [ The solar cell 100 may further include a passivation film 24, an antireflection film 26, an insulating layer 40, and the like. This will be explained in more detail.

The semiconductor substrate 10 may include a base region 110 having a second conductivity type including a second conductivity type dopant at a relatively low doping concentration. The base region 110 may be formed of a crystalline semiconductor including a second conductive dopant. In one example, the base region 110 may be composed of a single crystal or a polycrystalline semiconductor (e.g., single crystal or polycrystalline silicon) including a second conductive type dopant. In particular, the base region 110 may be comprised of a single crystal semiconductor (e.g., a single crystal semiconductor wafer, more specifically a semiconductor silicon wafer) comprising a second conductive dopant. Thus, when the base region 110 is made of monocrystalline silicon, the solar cell 100 constitutes a single crystal silicon solar cell. Since the solar cell 100 having a single crystal semiconductor has high crystallinity and is based on the base region 110 or the semiconductor substrate 10 having few defects, the electrical characteristics are excellent.

The second conductivity type may be p-type or n-type. For example, if the base region 110 has an n-type, a p-type (e.g., p-type) layer which forms a junction with the base region 110 by photoelectric conversion The first conductivity type region 32 can be formed wide to increase the photoelectric conversion area. In this case, the first conductivity type region 32 having a large area can effectively collect holes having a relatively low moving speed, thereby contributing to the improvement of photoelectric conversion efficiency. However, the present invention is not limited thereto.

The semiconductor substrate 10 may include a front electric field area 130 located on the front side. The front field region 130 may have a doping concentration higher than that of the base region 110 while having the same conductivity type as that of the base region 110. [

In this embodiment, the front electric field region 130 is formed in the semiconductor substrate 10 as a doped region formed by doping the second conductive type dopant with a relatively high doping concentration. Accordingly, the front electric field area 130 includes a crystalline (single crystal or polycrystalline) semiconductor having a second conductivity type to constitute a part of the semiconductor substrate 10. For example, the front electric field area 130 can form a part of a single crystal semiconductor substrate having a second conductivity type (for example, a single crystal silicon wafer substrate). However, the present invention is not limited thereto. Therefore, it is also possible to form the front electric field area 130 by doping a second conductive type dopant to a semiconductor layer other than the semiconductor substrate 10 (for example, an amorphous semiconductor layer, a microcrystalline semiconductor layer, or a polycrystalline semiconductor layer) have. Or the front electric field area 130 is similar to that doped by the fixed electric charge of the layer (for example, the passivation film 24 and / or the antireflection film 26) formed adjacent to the semiconductor substrate 10 Or an electric field area. For example, when the base region 110 is n-type, the passivation film 24 may be formed of an oxide (for example, aluminum oxide) having a fixed negative charge to form an inversion layer on the surface of the base region 110. [ So that it can be used as an electric field area. In this case, the semiconductor substrate 10 does not have a separate doping region but consists only of the base region 110, thereby minimizing defects in the semiconductor substrate 10. [ The front electric field area 130 having various structures can be formed by various other methods.

In the present embodiment, the front surface of the semiconductor substrate 10 may be textured to have irregularities such as pyramids. If the surface roughness of the semiconductor substrate 10 is increased by forming concavities and convexities on the front surface of the semiconductor substrate 10 by such texturing, the reflectance of light incident through the front surface of the semiconductor substrate 10 can be reduced. Accordingly, the amount of light reaching the pn junction formed by the base region 110 and the first conductivity type region 32 can be increased, and the light loss can be minimized.

The rear surface of the semiconductor substrate 10 may be made of a relatively smooth and flat surface having a surface roughness lower than that of the front surface by mirror polishing or the like. When the first and second conductivity type regions 32 and 34 are formed together on the rear side of the semiconductor substrate 10 as in the present embodiment, the characteristics of the solar cell 100 This can vary greatly. As a result, unevenness due to texturing is not formed on the rear surface of the semiconductor substrate 10, so that passivation characteristics can be improved and the characteristics of the solar cell 100 can be improved. However, the present invention is not limited thereto, and it is also possible to form concavities and convexities by texturing on the rear surface of the semiconductor substrate 10 according to circumstances. Various other variations are possible.

A tunneling layer 20 may be formed on the rear surface of the semiconductor substrate 10. For example, the tunneling layer 20 may be formed in contact with the rear surface of the semiconductor substrate 10 to simplify the structure and improve the tunneling effect. However, the present invention is not limited thereto.

The tunneling layer 20 acts as a kind of barrier to electrons and holes to prevent the minority carriers from passing therethrough and to prevent the majority carriers from being accumulated in the portion adjacent to the tunneling layer 20, so that only the majority carriers can pass through the tunneling layer 20. At this time, a plurality of carriers having energy above a certain level can easily pass through the tunneling layer 20 by the tunneling effect. The tunneling layer 20 may also serve as a diffusion barrier to prevent the dopants of the conductive regions 32 and 34 from diffusing into the semiconductor substrate 10. [ The tunneling layer 20 may include various materials through which a plurality of carriers can be tunneled. For example, the tunneling layer 20 may include an oxide, a nitride, a semiconductor, a conductive polymer, and the like. For example, the tunneling layer 20 may comprise silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, and the like. In particular, the tunneling layer 20 may be comprised of a silicon oxide layer comprising silicon oxide. This is because the silicon oxide layer is a film which has excellent passivation characteristics and is susceptible to tunneling of the carrier.

The tunneling layer 20 in this embodiment includes a first portion 201 that is formed entirely on the rear surface of the semiconductor substrate 10 and a second portion 202 that is partially formed on the first portion 201 . For the tunneling layer 20, the semiconductor layer 30 including the conductive regions 32 and 34 will be described in more detail.

On the tunneling layer 20, a semiconductor layer 30 including conductive regions 32 and 34 may be located. For example, the semiconductor layer 30 may be formed in contact with the tunneling layer 20 to simplify the structure and maximize the tunneling effect. However, the present invention is not limited thereto.

In this embodiment, the semiconductor layer 30 includes a first conductivity type region 32 having a first conductivity type dopant and exhibiting a first conductivity type, a second conductivity type region 32 having a second conductivity type dopant and exhibiting a second conductivity type, Type region 34. [0040] The first conductive type region 32 and the second conductive type region 34 may be coplanar on the tunneling layer 20. That is, no other layer is located between the first and second conductivity type regions 32 and 34 and the tunneling layer 20, or the first and second conductivity type regions 32 and 34 and the tunneling layer 20 20, the other layers may have the same lamination structure. And the concave portion 36 may be positioned between the first conductivity type region 32 and the second conductivity type region 34 on the same plane.

The first conductive type region 32 forms a pn junction (or a pn tunnel junction) between the base region 110 and the tunneling layer 20 to form an emitter region for generating carriers by photoelectric conversion.

At this time, the first conductive type region 32 may include a semiconductor (for example, silicon) including a first conductive type dopant opposite to the base region 110. The first conductive type region 32 is formed separately from the semiconductor substrate 10 on the semiconductor substrate 10 (more specifically, on the tunneling layer 20) and the first conductive type dopant is doped As shown in Fig. Accordingly, the first conductive type region 32 may be formed of a semiconductor layer having a crystal structure different from that of the semiconductor substrate 10 so that the first conductive type region 32 can be easily formed on the semiconductor substrate 10. For example, the first conductivity type region 32 may be an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor (e.g., amorphous silicon, microcrystalline silicon, or polycrystalline silicon) that can be easily fabricated by various methods, And the first conductive type dopant. The first conductive dopant may be included in the semiconductor layer in the step of forming the semiconductor layer or may be included in the semiconductor layer by various doping methods such as a heat diffusion method and an ion implantation method after forming the semiconductor layer.

At this time, the first conductive type region 32 may include a first conductive type dopant that can exhibit a conductive type opposite to the base region 110. That is, when the first conductivity type dopant is a p-type, a Group 3 element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used. When the first conductivity type dopant is n-type, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) may be used. In one example, the first conductivity type dopant may have a p-type.

The second conductivity type region 34 forms a back surface field to prevent carriers from being lost by recombination on the surface of the semiconductor substrate 10 (more precisely, the back surface of the semiconductor substrate 10) Thereby constituting a rear electric field area.

At this time, the second conductive type region 34 may include a semiconductor (e.g., silicon) including the same second conductive type dopant as the base region 110. In this embodiment, the second conductivity type region 34 is formed separately from the semiconductor substrate 10 on the semiconductor substrate 10 (more specifically on the tunneling layer 20) and the second conductivity type dopant is doped As shown in Fig. Accordingly, the second conductive type region 34 may be formed of a semiconductor layer having a crystal structure different from that of the semiconductor substrate 10 so that the second conductive type region 34 can be easily formed on the semiconductor substrate 10. For example, the second conductivity type region 34 may be an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor (e.g., amorphous silicon, microcrystalline silicon, or polycrystalline silicon) that can be easily fabricated by various methods, And the second conductive type dopant. The second conductive dopant may be included in the semiconductor layer in the step of forming the semiconductor layer or may be included in the semiconductor layer by various doping methods such as a thermal diffusion method and an ion implantation method after forming the semiconductor layer.

At this time, the second conductive type region 34 may include a second conductive type dopant that can exhibit the same conductivity type as the base region 110. That is, when the second conductivity type dopant is n-type, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) can be used. When the second conductivity type dopant is p-type, a group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used. As an example, the second conductivity type dopant may be n-type.

In this embodiment, the recess 36 is formed between the first conductivity type region 32 and the second conductivity type region 34 and is formed as a spacing space portion. More specifically, the concave portion 36 composed of the spacing space portion may be a portion of the semiconductor layer 30 where some portion is removed so that the semiconductor layer 30 is not located. Thus, the first conductive type region 32 and the second conductive type region 34 are spaced apart from each other with the concave portion 36 formed as the spacing space therebetween. When the first conductive type region 32 and the second conductive type region 34 are in contact with each other, a shunt may be generated to deteriorate the performance of the solar cell 100. Accordingly, in the present embodiment, unnecessary shunts can be prevented by positioning the concave portion 36 constituted by the spaced space portions separating or separating the first conductive type region 32 and the second conductive type region 34 from each other .

In this embodiment, the recess 36 is entirely separated between the first conductivity type region 32 and the second conductivity type region 34. [ However, the present invention is not limited thereto. Therefore, the recesses 36 may be formed so as to separate only a part of the boundary portions of the first conductive type region 32 and the second conductive type region 34. According to this, other portions of the boundaries of the first conductivity type region 32 and the second conductivity type region 34 may be in contact with each other or may be separated by a barrier region (reference numeral 38 in FIG. 7 or 8). Various other variations are possible.

Here, the area of the first conductivity type region 32 having a conductivity type different from that of the base region 110 can be wider than the area of the second conductivity type region 34 having the same conductivity type as that of the base region 110 have. Accordingly, the pn junction formed through the tunneling layer 20 between the base region 110 and the first conductive type region 32 can be made wider. At this time, when the base region 110 and the second conductivity type region 34 have the n-type conductivity and the first conductivity type region 32 has the p-type conductivity, the first conductivity type region It is possible to effectively collect holes having a relatively slow moving speed by the electron beam 32. [ The planar structure of the first conductive type region 32, the second conductive type region 34, and the concave portion 36 will be described later in more detail with reference to FIG.

An insulating layer 40 may be formed over the first and second conductivity type regions 32 and 34. For example, the insulating layer 40 may be formed while covering the upper surface (bottom surface) and side surfaces of the first and second conductive type regions 32 and 34 and also inside the recessed portion 36. More specifically, the insulating layer 40 is formed on the upper surface of the first and second conductive type regions 32 and 34, the side surfaces of the first and second conductive type regions 32 and 34 or the concave portion 36, (E.g., on the depression 204) at a portion corresponding to the recess 36 located between the first and second conductive regions 32 and 34 (e.g., over the second portion 202) Contact). Thus, the passivation characteristics of the first and second conductivity type regions 32 and 34 can be improved and the shunt between the first and second conductivity type regions 32 and 34 can be prevented more effectively.

The insulating layer 40 may be located on the semiconductor layer 30 at a portion not located at the electrodes 42 and 44. [ The insulating layer 40 may have a greater thickness than the tunneling layer 20 (more precisely, the first portion 201 and the second portion 202 of the tunneling layer 20). As a result, the insulating characteristics and the passivation characteristics can be improved. However, the present invention is not limited thereto, and the thickness of the insulating layer 40 may be larger than the first portion 201 and smaller than the second portion 202. Various other variations are possible.

The insulating layer 40 may be made of various insulating materials (e.g., oxides, nitrides, etc.). For example, the insulating layer 40 may be formed of any one selected from the group consisting of a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, a silicon carbide film, Al ₂ O ₃ , MgF ₂ , ZnS, TiO _2, and CeO ₂ A single film or a multilayer film structure in which two or more films are combined. However, the present invention is not limited thereto, and it goes without saying that the insulating layer 40 may include various materials.

For example, in this embodiment, the passivation film 24, the antireflection film 26, and / or the insulating layer 40 may not include a dopant or the like so as to have excellent insulating properties, passivation properties, and the like.

Electrodes 42 and 44 located on the rear surface of the semiconductor substrate 10 include a first electrode 42 electrically and physically connected to the first conductivity type region 32 and a second electrode 42 electrically connected to the second conductivity type region 34 And a second electrode 44 electrically and physically connected.

The first electrode 42 is connected to the first conductive type region 32 through the first opening portion 402 of the insulating layer 40 and the second electrode 44 is connected to the first conductive type region 32 of the insulating layer 40. In this case, 2 opening 404 and is connected to the second conductivity type region 34. The first and second electrodes 42 and 44 may include various metal materials. The first and second electrodes 42 and 44 are connected to the first conductive type region 32 and the second conductive type region 34 without being electrically connected to each other, And can have a variety of planar shapes. That is, the present invention is not limited to the planar shapes of the first and second electrodes 42 and 44.

1 and 2, the first conductive type region 32 and the second conductive type region 34, the barrier region 38, and the planar shape of the first and second electrodes 42 and 44 Will be described in detail.

1 and 2, in the present embodiment, the first conductive type region 32 and the second conductive type region 34 are formed to be long in a stripe shape, and alternate with each other in the direction crossing the longitudinal direction Respectively. A recess 36 may be located between the first conductivity type region 32 and the second conductivity type region 34 to isolate them. Although not shown, a plurality of first conductive regions 32 spaced apart from each other may be connected to each other at one edge, and a plurality of second conductive regions 34 separated from each other may be connected to each other at the other edge. However, the present invention is not limited thereto.

At this time, the area of the first conductivity type region 32 may be larger than the area of the second conductivity type region 34. In one example, the areas of the first conductivity type region 32 and the second conductivity type region 34 can be adjusted by varying their widths. That is, the width W1 of the first conductivity type region 32 may be greater than the width W2 of the second conductivity type region 34. [

The first electrode 42 may be formed in a stripe shape corresponding to the first conductivity type region 32 and the second electrode 44 may be formed in a stripe shape corresponding to the second conductivity type region 34 . The first and second openings (402 and 404 in FIG. 1, respectively, the same reference numerals) are formed on the entire length of the first and second electrodes 42 and 44 corresponding to the first and second electrodes 42 and 44, . The contact area between the first and second electrodes 42 and 44 and the first conductivity type region 32 and the second conductivity type region 34 can be maximized to improve the carrier collection efficiency. However, the present invention is not limited thereto. The first and second openings 402 and 404 are formed so as to connect only a part of the first and second electrodes 42 and 44 to the first conductivity type region 32 and the second conductivity type region 34 Of course it is possible. For example, the first and second openings 402 and 404 may be formed of a plurality of contact holes. Although not shown in the figure, the first electrodes 42 may be connected to each other at one edge, and the second electrodes 44 may be connected to each other at the other edge. However, the present invention is not limited thereto.

Referring again to FIG. 1, a passivation film 24 and / or an antireflection film 26 (not shown) are formed on the front surface of the semiconductor substrate 10 (more precisely, on the front electric field area 130 formed on the front surface of the semiconductor substrate 10) ) Can be located. Only the passivation film 24 may be formed on the semiconductor substrate 10 or only the antireflection film 26 may be formed on the semiconductor substrate 10 or the passivation film 24 And the antireflection film 26 may be disposed one after the other. In the figure, a passivation film 24 and an antireflection film 26 are sequentially formed on a semiconductor substrate 10, and the semiconductor substrate 10 is contacted with the passivation film 24. However, the present invention is not limited thereto, and the semiconductor substrate 10 may be formed in contact with the anti-reflection film 26, and various other modifications are possible.

The passivation film 24 and the antireflection film 26 may be formed entirely on the front surface of the semiconductor substrate 10 substantially. Here, the term " formed as a whole " includes not only completely formed physically but also includes cases where there are inevitably some exclusion parts.

The passivation film 24 is formed in contact with the front surface of the semiconductor substrate 10 to passivate the defects existing in the front surface or the bulk of the semiconductor substrate 10. [ Thus, the recombination site of the minority carriers can be removed to increase the open-circuit voltage of the solar cell 100. The antireflection film 26 reduces the reflectance of light incident on the front surface of the semiconductor substrate 10. The amount of light reaching the pn junction formed at the interface between the base region 110 and the first conductive type region 32 can be increased. Accordingly, the short circuit current Isc of the solar cell 100 can be increased. In this way, the efficiency of the solar cell 100 can be improved by increasing the open-circuit voltage and the short-circuit current of the solar cell 100 by the passivation film 24 and the antireflection film 26.

The passivation film 24 and / or the antireflection film 26 may be formed of various materials. In one example, the passivation film 24 and / or the anti-reflection film 26 is a silicon nitride film, a silicon nitride film containing hydrogen, silicon oxide, silicon nitride oxide, aluminum oxide film, a silicon carbide film, MgF _2, ZnS, TiO ₂ and CeO ₂ , Or a multilayer structure in which two or more films are combined. As an example, the passivation film 24 may comprise silicon oxide and the antireflective film 26 may comprise silicon nitride.

Referring again to the tunneling layer 20 and the recess 36, the recess 36 in this embodiment can be formed by etching. At this time, the second portion 202 functions as an etch stop layer. That is, when the concave portion 36 is formed by etching, the second portion 202 serves to stop the etching. Accordingly, the concave portion 36 can be formed by a simple process without damaging the first portion 201 of the tunneling layer 20.

The tunneling layer 20 may include a first portion 201 that is formed entirely on the backside of the semiconductor substrate 10 and a second portion 202 that is partially formed on the first portion 201.

Since the first portion 201 is continuously and completely formed on the rear surface of the semiconductor substrate 10, the first portion 201 can be easily formed without additional patterning. In this case, the term " totally formed " includes cases where both of them are physically completely formed, and inevitably they are not formed in some regions.

The first portion 201 may have an overall uniform thickness (e.g., a thickness having a difference within 20%). Thus, the carrier can uniformly reach the first or second conductivity type regions 32 and 34 through the first portion 201 as a whole.

The first thickness T1 of the first portion 201 may be smaller than the thickness of the semiconductor layer 30, the insulating layer 40 and the like so that the tunneling effect can be sufficiently realized. In one example, the first thickness T1 of the first portion 201 may be less than or equal to 2 nm, and may be, for example, from 0.1 nm to 1.8 nm (more specifically, 0.5 nm to 1.5 nm). If the first thickness T1 of the first portion 201 exceeds 2 nm, the efficiency of the solar cell 100 may deteriorate due to no smooth tunneling, and the first thickness T1 of the first portion 201 may be reduced, Is less than 0.1 nm, it may be difficult to form the first portion 201 of desired quality. In order to further improve the tunneling effect, the first thickness T1 of the first portion 201 may be 0.1 nm to 1.8 nm (more specifically, 0.5 nm to 1.5 nm). However, the present invention is not limited thereto, and the first thickness T1 of the first portion 201 may have various values.

The second portion 202 partially located over the first portion 201 functions as an etch stop layer in the formation of the recess 36 and forms a part of the first conductivity type region 32 and the second conductivity type region 34 The carrier moves to the boundary portion to prevent the leakage current. The second portion 202 may be provided at a position corresponding to the concave portion 36 located at the boundary portion between the first conductive type region 32 and the second conductive type region 34. [ The second portion 202 may be formed corresponding to at least the concave portion 36. That is, the second portion 202 is located corresponding to the portion where the concave portion 36 is formed. In particular, the second portion 202 may be positioned so as to correspond to the recess 36 in a one-to-one correspondence.

At this time, the width W4 of the second portion 202 may be larger than the width W3 of the concave portion 36. The width W3 of the concave portion 36 is equal to the width W2 of the concave portion 36 on the surface of the second portion 202 on which the concave portion 36 is not formed (i.e., on the opposite surface of the first portion 201 in the second portion 202) The width of the concave portion 36 at the surface on which the light-emitting portion 36 is located).

If the width W4 of the second portion 202 is larger than the width W3 of the concave portion 36 as described above, the entire portion of the concave portion 36 (particularly, the second portion 202) The entire portion of the concave portion 36 in the adjacent portion) is located above the second portion 202 and the first portion 201 can be maintained without the portion to be etched. When the neck portion 36 is removed from the second portion 202, the first portion 201 having the thinner thickness of the recessed portion 36 is damaged, so that the passivation property is lowered and the carrier movement due to tunneling may not be smooth.

The width W3 of the concave portion 36 may be smaller than the width of the first conductivity type region 32 and smaller than the width of the second conductivity type region 34. [ For example, the width W3 of the concave portion 36: the width W4 of the second portion 202 may be 1: 1.12 to 1: 3. If the ratio is less than 1: 1.12, the width of the second portion 202 is not sufficient and the first portion 201 may be damaged when there is a process error or the like. If the ratio exceeds 1: 3, the region where the second portion 202 overlaps with the first and second conductivity type regions 32 and 34 is large, so that the carriers are electrically connected to the first and second conductivity type regions 32 and 34 Tunneling can be prevented. For smooth tunneling, the ratio may be 1: 1.12 to 1.5. However, the present invention is not limited thereto, and the ratio may have various values.

The virtual center line CL of the second portion 202 and the imaginary center line CL of the concave portion 36 coincide with each other in the present embodiment so that the second portion 202 is symmetrical with respect to the concave portion 36 As shown in FIG. More specifically, the virtual center line CL of the concave portion 36 as viewed from the virtual center line CL of the second portion 202 and the surface of the second portion 202 may coincide with each other . However, the present invention is not limited thereto. Another modification will be described later with reference to Fig.

In this embodiment, the second portion 202 is partially located corresponding to the concave portion 36, and is not formed in the other portion. The portion where the second portion 202 is located may have a shape protruding toward the rear side of the solar cell 100 than the portion where only the first portion 201 is located. That is, a step may be provided between the portion where the second portion 202 is located and the portion where the first portion 201 is located. The one surface of the second portion 202 opposite to the semiconductor substrate 10 may be located at a position more projected toward the rear than the one surface of the first portion 201 opposite to the semiconductor substrate 10. [

(I.e., the thickness protruding from the first portion 201) (T2) of the second portion 202 so that the second portion 202 can sufficiently perform the role of preventing the etching stop layer and the leakage current May be greater than the first thickness (T1) of the first portion (201). As an example, the second thickness T2 of the second portion 202 may be greater than or equal to 3 nm. If the second thickness T2 of the second portion 202 is less than 3 nm, the effect of the second portion 202 may not be sufficient. For example, the second thickness T2 of the second portion 202 may be between 3 nm and 30 nm. If the second thickness T2 exceeds 30 nm, the process time for forming the second portion 202 may be long and the volume of the first and second conductivity type regions 32 and 34 may be reduced, There is a limit to increase the efficiency of the apparatus. Particularly, the second thickness T2 may be 5 nm or more (for example, 5 nm to 30 nm). According to this, the effect of the second portion 202 can be sufficiently exerted. However, the present invention is not limited thereto, and the second portion 202 may have a different thickness.

In this embodiment, the first portion 201 and the second portion 202 have the same material and composition, and the first portion 201 and the second portion 202 may be formed in contact with each other. For example, it has been illustrated that the first portion 201 and the second portion 202 are comprised of a single layer formed in the same process. However, the present invention is not limited thereto. Thus, the first portion 201 and the second portion 202 may be comprised of discrete layers formed in different processes. And the second portion 202 may comprise a different material than the first portion 201 and the second portion 202 may comprise the same material as the first portion 201 but have a different composition. Alternatively, the portion of the first portion 201 adjacent to the second portion 202 has the same material and composition as the second portion 202, and the portion of the first portion 201 that is not adjacent to the second portion 202 May have a different material or composition than the second portion 202. It is also possible that the second portion 202 and the first portion 201 are not in contact with each other and a separate layer is positioned between the first portion 201 and the second portion 202. Various other variations are possible.

The second portion 202 can use a variety of materials that can be used as etch stop layers. In this embodiment, the second portion 202 may comprise an oxide. The oxide differs greatly from the semiconductor material in the etching ratio to the etching solution for etching the semiconductor material (in particular, silicon). More specifically, since the etch rate of the oxide is much less than the etch rate of the semiconductor material, the oxide is etched slowly or is not substantially etched when the semiconductor material is etched. Thus, the second portion 202 containing oxide can fully perform its role as a etch stop layer.

In this embodiment, the second portion 202 may be a silicon oxide layer comprising silicon oxide. The silicon oxide layer can sufficiently perform its role as the etch stop layer. If the first portion 201 and the second portion 202 are made of a silicon oxide layer, the first portion 201 and the second portion 202 may have the same or similar characteristics, The problem can be avoided.

More specifically, the second portion 202 has an amorphous structure having the same or similar to SiO ₂ or a similar formula (e.g., SiO x where x is 1.9 to 2.1) Lt; / RTI > The second portion 202 composed of the silicon oxide layer having the above-described chemical formula can effectively perform the role of the etch stop layer. Alternatively, the second portion 202 may be composed of a silicon oxide layer having the formula SiOy (y is 0.2 to 1.5, especially y is 1.0 to 1.5). In this case, the second portion 202 may have an amorphous structure or a polycrystalline structure. At this time, if the first portion 201 has approximately the same chemical composition as SiO ₂ or a similar chemical formula (e.g., SiO x where x is 1.9 to 2.1), then the second portion 202 is the same as the first portion 201 The material has different composition and crystal structure.

A recess 36 may be formed in the semiconductor layer 30 over the tunneling layer 20 over the second portion 202 between the first and second conductivity type regions 32 and 34 . In this embodiment, the concave portion 36 may be constituted by a space portion in which a part of the semiconductor layer 30 is entirely removed in the thickness direction to expose the second portion 202. The first conductive type region 32 and the second conductive type region 34 are completely separated from each other with the concave portion 36 therebetween to form the first conductive type region 32 and the second conductive type region 34, It is possible to eliminate the path of the leakage current flowing between the electrodes. Thus, the leakage current can be minimized and the filling density of the solar cell 100 can be improved.

As described above, the concave portion 36 is formed by using an etching solution having different etching ratios in the semiconductor layer 30 and the second portion 202, and the second portion 202 is used as an etching stop layer. Accordingly, shapes, characteristics, and the like that can be exhibited when the concave portion 36 and the second portion 202 are formed by etching are provided.

That is, the first side adjacent to the first conductive type region 32 in the concave portion 36 and the second side adjacent to the second conductive type region 34 in the concave portion 36 may have different slopes. That is, since the etching solution has different etching rates in the first conductivity type region 32 and the second conductivity type region 34 having different conductivity types, the first conductivity type region 32 and the second conductivity type region 34 have different etching rates. The sides formed by the etching in the second conductivity type region 34 have different shapes. For example, when potassium hydroxide (KOH) is used as the etching solution, the etch ratio of the p-type region (for example, the first conductivity type region 32) is 3 nm / min to 4 nm / For example, the second conductive type region 34 may have an etch rate of 12 nm / min to 13 nm / min. As a result, the n-type region is etched at a high speed and an undercut is formed in the concave portion 36 at a portion adjacent to the n-type region. Therefore, the side surface of the concave portion 36 adjacent to the n-type region can be etched so as to have a smooth inclination. That is, the side surface of the concave portion 36 in the portion adjacent to the n-type region due to the undercut can be formed into a curved surface or a rounded surface with a generally smooth slope. the p-type region can not be etched well, and the side surface of the concave portion 36 adjacent to the p-type region can have a large inclination (for example, a slope close to about 90 degrees) and a plane or a surface having a relatively large radius of curvature. Thus, the side surface of the concave portion 36 adjacent to the n-type region can be positioned to have a larger width and a relatively small curvature radius and a lower slope than the side surface of the concave portion 36 adjacent to the p-type region. It can be seen that the concave portion 36 is formed by etching by the shape of the concave portion 36.

A depression 204 may be formed in the second portion 202 at a portion corresponding to the depression 36 of the semiconductor layer 30. The depression 204 formed toward the semiconductor substrate 10 is located on the surface of the second portion 202 opposite to the semiconductor substrate 10 so that the portion where the depression 204 is formed is located on the second portion 202, Of the other surface. And the portion where the depression 204 is formed may have a smaller thickness than the other portion of the second portion 202. [ The depressed portion 204 may have a rounded shape or a curved shape in which the center portion is recessed more than the edge portion. These depressions 204 can be formed by a slight etching of the second portion 202 in the etching process to form the recesses 36. The dimples 204 are not necessarily formed and may not be formed. Alternatively, the second portion 202 may be formed with various marks or the like due to etching in addition to the depressed portion 204.

It can be seen that the concave portion 36 is formed by etching and the second portion 202 is used as the etching stop layer by the shape of the concave portion 36 and the depressed portion 204 of the second portion 202 .

When light is incident on the solar cell 100 according to the present embodiment, electrons and holes are generated by the photoelectric conversion at the pn junction formed between the base region 110 and the first conductivity type region 32, And electrons tunnel to the tunneling layer 20 to move to the first and second electrodes 42 and 44 after moving to the first conductivity type region 32 and the second conductivity type region 34, respectively. Thereby generating electrical energy.

In the solar cell 100 having the rear electrode structure in which the electrodes 42 and 44 are formed on the rear surface of the semiconductor substrate 10 and electrodes are not formed on the front surface of the semiconductor substrate 10 as in the present embodiment, The shading loss can be minimized at the front of the display device. Thus, the efficiency of the solar cell 100 can be improved. However, the present invention is not limited thereto.

Since the first and second conductive regions 32 and 34 are formed on the semiconductor substrate 10 with the tunneling layer 20 interposed therebetween, the first and second conductive type regions 32 and 34 are formed of different layers from the semiconductor substrate 10. As a result, the loss due to the recombination can be minimized as compared with the case where the doped region formed by doping the semiconductor substrate 10 with the dopant is used as the conductive type region.

Since the tunneling layer 20 and the semiconductor substrate 10 are not etched when the recesses 36 are formed by forming the recesses 36 with the second portion 202 as an etch stop layer, And the semiconductor substrate 10 can be prevented from being damaged. Since the second portion 202 is partially formed corresponding to the concave portion 36, tunneling to the first and second conductive type regions 32 and 34 is smoothly performed through the first portion 201 . The first conductive type region 32 and the second conductive type region 34 are separated and separated from each other by the concave portion 36 to form a gap between the first conductive type region 32 and the second conductive type region 34 The leakage current flowing can be minimized. Thus, the filling density of the solar cell 100 can be improved and the efficiency of the solar cell 100 can be improved.

A manufacturing method of the solar cell 100 having the above-described structure will be described in detail with reference to FIGS. 3A to 3M. 3A to 3M are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.

First, as shown in FIG. 3A, a semiconductor substrate 10 composed of a base region 110 having a second conductive dopant is prepared. In this embodiment, the semiconductor substrate 10 may be formed of a silicon substrate (for example, a silicon wafer) having an n-type dopant. As the n-type dopant, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) may be used. However, the present invention is not limited thereto, and the base region 110 may have a p-type dopant.

At this time, at least one of the front surface and the rear surface of the semiconductor substrate 10 may be textured so as to have irregularities. Wet or dry texturing may be used for texturing the surface of the semiconductor substrate 10. [ The wet texturing can be performed by immersing the semiconductor substrate 10 in the texturing solution, and has a short process time. In dry texturing, the surface of the semiconductor substrate 10 is cut by using a diamond grill or a laser, so that irregularities can be uniformly formed, but the processing time is long and damage to the semiconductor substrate 10 may occur. Alternatively, the semiconductor substrate 10 may be textured by reactive ion etching (RIE) or the like. As described above, the semiconductor substrate 10 can be textured in various ways in the present invention.

For example, the front surface of the semiconductor substrate 10 is textured so as to have irregularities, and the rear surface of the semiconductor substrate 10 is processed by mirror polishing or the like to be a flat surface having a surface roughness smaller than that of the front surface of the semiconductor substrate 10 . However, the present invention is not limited thereto, and the semiconductor substrate 10 having various structures can be used. The texturing of the semiconductor substrate 10 using the untextured semiconductor substrate 10 may be performed later by another process.

Subsequently, as shown in FIGS. 3B to 3D, a tunneling layer (reference numeral 20 in FIG. 3D, the same applies hereinafter) is formed on the rear surface of the semiconductor substrate 10. This will be explained in more detail.

First, as shown in FIG. 3B, a tunneling layer 20 having a second thickness (reference symbol T2 in FIG. 1, hereinafter the same) corresponding to a second portion of the tunneling layer 20 (reference numeral 202 in FIG. Forming layer 202a is formed entirely on the rear surface of the semiconductor substrate 10. [ The tunneling layer 202a may be formed by various methods, for example, thermal growth, evaporation (for example, chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like). However, the present invention is not limited thereto, and the tunneling layer 202a may be formed by various methods.

Then, as shown in FIG. 3C, the tunneling layer 202a is patterned to leave the portion 202b corresponding to the second portion 202, and the other portions are entirely removed. Thus, only the portion 202b corresponding to the second portion 202 having the second thickness T2 is located on the rear surface of the semiconductor substrate 10. [ Various methods known as a patterning method, for example, an etching paste, etching using photolithography, a laser, and the like can be applied. In this embodiment, the tunneling layer 202a is formed as a whole, and then the tunneling layer 202a is patterned. However, the present invention is not limited thereto. Therefore, the tunneling layer 202a may be formed only on the portion corresponding to the second portion 202 by using a mask, a mask layer, or the like, and may be used as the portion 202b corresponding to the second portion 202 as it is. Various other variations are possible.

3D, a layer corresponding to the tunneling is formed in a portion where the second portion 202 is not formed, and a tunneling layer 20 (having a first portion 201 and a second portion 202) ). For example, when the semiconductor substrate 10 is heat-treated at a predetermined temperature, a semiconductor material (for example, silicon) of the semiconductor substrate 10 is chemically reacted with oxygen outside the semiconductor substrate 10 by thermal oxidation, A silicon oxide layer may be formed on the rear surface of the semiconductor substrate 10 where the portion 202b corresponding to the second portion 201 is not formed, . When a part of the first portion 201 is formed by thermal oxidation as described above, the first portion 201 having a thin overall thickness can be formed by a simple process without using a mask, patterning, or the like.

The tunneling layer 20 having the first and second portions 201 and 202 may be formed by various methods other than the above-described method.

4A, a tunneling layer 202a having a second thickness T2 is formed on the rear surface of the semiconductor substrate 10 as a whole. Thereafter, as shown in FIG. 4B, the portion corresponding to the first portion 201 is etched while having the first thickness (T1 of FIG. 1, the same applies hereinafter) 1 portion 201 can be formed. This can be implemented by adjusting the etching rate of the portion corresponding to the first portion 201 while preventing the portion corresponding to the second portion 202 from being etched using a mask or a mask layer . Accordingly, the tunneling layer 20 having the first and second portions 201 and 202 may be formed by a simple process. In this case, since the first and second portions 201 and 202 are formed of the same tunneling layer 202a, the first and second portions 201 and 202 are formed of a single layer having the same material and having an integral structure Can be configured. Various other variations are possible.

5A, a first portion 201 having a first thickness T1 is formed as a whole on the rear surface of the semiconductor substrate 10. [ Thereafter, as shown in Fig. 5B, the second portion 202 having the second thickness T2 can be formed. The second portion 202 may be formed by forming a layer for forming the second portion 202 and patterning the same to form the second portion 202. Alternatively, the second portion 202 may be formed only by using a mask or a mask layer, Two portions 202 may be formed. In this case, the first and second parts 201 and 202 may comprise the same material or may comprise different materials or different compositions. Various other variations are possible.

Next, as shown in FIGS. 3E and 3K, a semiconductor layer (not shown) including a first conductive type region 32 and a second conductive type region 34 and having a concave portion 36 is formed on the tunneling layer 20 30). This will be described in more detail as follows.

The intrinsic semiconductor layer 300 having intrinsic (i-type) is formed on the tunneling layer 20, as shown in Fig. 3E. The intrinsic semiconductor layer 300 may be composed of microcrystalline, amorphous, or polycrystalline semiconductor (for example, silicon). The intrinsic semiconductor layer 300 may be formed, for example, by a thermal growth method, a deposition method (for example, chemical vapor deposition (PECVD)), or the like. However, the present invention is not limited thereto, and the intrinsic semiconductor layer 300 may be formed by various methods.

Then, as shown in FIG. 3F, a first doping layer 322 and an undoped layer 324 are formed at portions corresponding to the first conductivity type region 32.

The first doping layer 322 may be a variety of layers having second conductivity type impurities and may be boron silicate glass (BSG). The first doping layer 322 can be easily formed by forming boron silicate glass as the first doping layer 322. At this time, the first doping layer 322 may include a plurality of doped portions corresponding to the plurality of first conductivity type regions 32. The plurality of doped portions may have a shape corresponding to the first conductivity type region 32.

The undoped layer 324 formed on the first doped layer 322 is made of a material that does not include the first and second conductivity type impurities. As an example, the undoped layer 324 may be composed of an undoped silicate or an insulating film. The undoped layer 324 may prevent the first conductive impurity contained in the first doped layer 322 from being out-diffused.

The first doping layer 322 and the undoped layer 324 may be formed on the intrinsic semiconductor layer 300 with a shape corresponding to the first conductivity type region 32 using a mask. Or may be formed on the intrinsic semiconductor layer 300 with a shape corresponding to the first conductivity type region 32 by a method such as inkjet or screen printing. Alternatively, the first doping layer 322 and the undoped layer 324 may be entirely formed on the semiconductor layer 30, and then a portion where the first conductivity type region 32 is not formed may be removed by an etching solution, an etching paste, or the like A first doped layer 322 may be formed.

Then, as shown in Fig. 3G, an opening 326a (see Fig. 3C) is formed on the first doped layer 322 at a position corresponding to the second conductive type region (reference numeral 34 in Fig. 3K) and the concave portion A mask layer 326 may be formed. At this time, the mask layer 326 may be formed corresponding to the first doping layer 322 and the undoped layer 324.

This mask layer 326 is composed of an undoped material that does not contain the first and second conductive impurities. In one example, the mask layer 326 may be a silicon carbide layer comprised of silicon carbide. The silicon carbide layer can be easily patterned by a laser, effectively prevent doping of the dopant, and can be easily removed later by a simple process.

This mask layer 326 may be formed on the first doped layer 322, the undoped layer 324, and the semiconductor layer 30 with a desired shape using a mask. Alternatively, it may be formed on the semiconductor layer 30 with a desired shape by a method such as inkjet or screen printing. Alternatively, a material corresponding to the mask layer 326 may be entirely formed in the first doping layer 322, the undoped layer 324, and the semiconductor layer 30, and then a portion corresponding to the opening 326a may be etched by an etching solution, The mask layer 326 may be formed by removing it by a paste or the like. Alternatively, when the mask layer 326 is formed of a silicon carbide layer as in the present embodiment, the opening portion 326a can be formed by irradiating the laser 310. [

Next, as shown in FIG. 3H, the first conductivity type semiconductor layer 320 (or the first conductivity type region 32) and the second conductivity type semiconductor layer 340 are formed by heat treatment. At this time, heat treatment can be performed in an atmosphere of a gas containing a second conductive type dopant (for example, a gas including phosphorus, for example, POCl ₃ ).

The first conductivity type semiconductor layer 320 is formed by diffusing the first conductivity type dopant into the intrinsic semiconductor layer 300 adjacent to the first doping layer 322. The second conductive dopant is diffused through the opening 326a by a thermal diffusion method, and the second conductive type semiconductor layer 340 is formed at a portion corresponding to the opening 326a. Thus, the second conductivity type semiconductor layer 340 is formed in a region corresponding to the second conductivity type region 34 and the concave portion 36.

At this time, the second conductive dopant may be diffused to the front surface of the semiconductor substrate 10 by a thermal diffusion method to form the front electric field area 130 together. However, the present invention is not limited thereto, and the front electric field area 130 may be separately formed in a separate process.

In this embodiment, the first conductive semiconductor layer 320 having a relatively large area is formed using the first doping layer 322, the second conductive type region 34 having a relatively narrow area, An opening 326a is formed in the mask layer 326 in the region corresponding to the first conductive semiconductor layer 36 to form the second conductive semiconductor layer 340 by thermal diffusion. Accordingly, the first conductivity type semiconductor layer 320 having a large area can be formed stably, the opening 326a can be formed with a narrow area, and then the second conductivity type semiconductor layer 340 can be formed by a thermal diffusion method to simplify the process .

However, the present invention is not limited thereto, and various methods known as a method of forming the first and second conductivity type semiconductor layers 320 and 340 (ion implantation, laser doping, etc.) may be used. The front electric field region 130 formed on the entire surface of the semiconductor substrate 10 may be formed by various methods such as ion implantation, laser doping, and the like. It is also possible that the front electric field area 130 is not formed separately.

Next, as shown in FIG. 3I, a mask layer 328 having an opening portion 328a corresponding to a portion where the concave portion 36 is to be formed is formed.

This mask layer 328 is composed of an undoped material that does not contain the first and second conductive impurities. In one example, the mask layer 328 may be a silicon carbide layer comprised of silicon carbide. The silicon carbide layer can be easily patterned by a laser, effectively prevent doping of the dopant, and can be easily removed later by a simple process.

The mask layer 328 may be formed on the first doped layer 322, the undoped layer 324, and the semiconductor layer 30 with a desired shape using a mask. Alternatively, it may be formed on the semiconductor layer 30 with a desired shape by a method such as inkjet or screen printing. Alternatively, a material corresponding to the mask layer 328 may be formed entirely in the first doping layer 322, the undoped layer 324, and the semiconductor layer 30, and then a portion corresponding to the opening 328a may be etched by an etching solution, The mask layer 328 may be formed by removing it by a paste or the like. Alternatively, when the mask layer 328 is formed of a silicon carbide layer as in the present embodiment, the opening 328a can be formed by irradiating a laser beam.

Next, as shown in FIG. 3J, the recessed portion 36 can be formed by etching the semiconductor layer 30 exposed by the opening portion 328a with the etching solution. The etching solution may be a material having an etch rate different from that of the semiconductor layer 30 and the second portion 202 or a material having a selective etch rate. For example, when an alkali solution (for example, a potassium hydroxide solution) is used as the etching solution, the semiconductor layer 30 has a low etch rate in the second portion 202 having a high etch rate and composed of oxide. Then, since the semiconductor layer 30 is easily etched and the second portion 202 is not easily etched, the etching stops when the semiconductor layer 30 is etched and the etching solution reaches the second portion 202. Thus, the concave portion 36 can be formed by a simple and stable method.

A part of the second conductivity type semiconductor layer 340 is removed by the etching solution and the concave portion 36 is formed in the second conductivity type semiconductor layer 340. In this case, Is formed. since the etch ratio of the n-type second conductivity type semiconductor layer 340 is greater than the etch rate of the p-type first conductivity type semiconductor layer 30 or the intrinsic semiconductor layer 300, The concave portion 36 can be easily formed at a higher speed. For example, when potassium hydroxide is used as the etching solution, the etching ratio of the n-type region is 12 nm / min to 13 nm / min, the etching rate of the p-type region is 3 nm / min to 4 nm / min, The etch rate can be approximately 10 nm / min. Accordingly, in this embodiment, the recessed portion 36 is formed by etching the n-type second conductive semiconductor layer 340 to improve the etching rate and form the concave portion 36 stably by the etching ratio difference .

In this embodiment, it is exemplified that the first conductivity type region 32 and the second conductivity type region 34 are in contact with each other in the process (for example, the process shown in Fig. 3H) before the recess 36 is formed Respectively. However, the present invention is not limited thereto. It is also possible to form the semiconductor layer 30 in which the barrier region 38 is located between the first conductivity type region 32 and the second conductivity type region 34 as shown in Fig. This will be described in more detail later. In the case where the semiconductor layer 30 in which the barrier region 38 is located is formed before the recess 36 is formed, the recess region 36 can be formed by removing the barrier region 38 as a whole have.

Then, as shown in FIG. 3K, the mask layer 328 can be removed. In one example, the mask layer 328 can be easily removed using an etching solution (e.g., diluted hydrofluoric acid (HF)) to remove it.

Next, as shown in FIG. 31, a passivation film 24 and an antireflection film 26 are sequentially formed on the entire surface of the semiconductor substrate 10, and an insulating layer 40 is formed on the rear surface of the semiconductor substrate 10 . That is, the passivation film 24 and the antireflection film 26 are entirely formed on the front surface of the semiconductor substrate 10 and the first and second conductivity type regions 32 and 34 are covered on the rear surface of the semiconductor substrate 10 The insulating layer 40 is formed as a whole. The passivation film 24, the antireflection film 26 and the insulating layer 40 may be formed by various methods such as a vacuum deposition method, a chemical vapor deposition method, a spin coating method, a screen printing method or a spray coating method. The order of forming the passivation film 24 and the antireflection film 26, and the insulating layer 40 may be variously modified.

Subsequently, first and second electrodes 42 and 44 connected to the first and second conductivity type regions 32 and 34 are formed, respectively, as shown in FIG. 3M.

For example, the first and second openings 402 and 404 may be formed in the insulating layer 40 and the first and second openings 402 and 404 may be formed by various methods such as a plating method and a vapor deposition method. (42, 44) can be formed. Alternatively, the first and second electrode-forming paste may be applied on the insulating layer 40 by screen printing or the like, and then fired-through or laser firing contact may be performed to form the above- It is also possible to form the first and second electrodes 42 and 44 of the shape. In this case, since the first and second openings 402 and 404 are formed when the first and second electrodes 42 and 44 are formed, the process of forming the first and second openings 402 and 404 separately You do not need to add it.

According to the present embodiment, the tunneling layer 20 having the first and second portions 201 and 202 and the semiconductor layer 30 having the concave portion 36 are manufactured by a simple process to form the solar cell 100 ) Efficiency and productivity can be improved at the same time.

Hereinafter, a solar cell according to another embodiment of the present invention will be described in detail with reference to FIGS. 6 to 9. FIG. The same or similar portions as those described in the above-mentioned portions will not be described in detail, and the different portions will be described in detail. It is to be understood that both the foregoing description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

6 is a cross-sectional view illustrating a solar cell according to another embodiment of the present invention.

6, the width W5 of the overlapping portion of the second portion 202 and the first conductivity type region 32 is greater than the width W5 of the overlapping portion of the second portion 202 and the second conductivity type region 34 (W6) may be different from each other. More specifically, the width W5 of the first conductive type region 32 having a different conductivity type from that of the semiconductor substrate 10 and the second portion 202 overlap with each other, 2 conductivity type region 34 and the second portion 202 overlap with each other. The virtual center line CL1 of the concave portion 36 (particularly, the imaginary center line of the concave portion 36 when the surface of the second portion 202 where the concave portion 36 is not located is referred to) And may be located closer to the second conductivity type region 34 than the imaginary center line CL2 of the second portion 202. [

When the second portion 202 is biased toward the first conductivity type region 32, the majority carriers of the semiconductor substrate 10 are tunneled to the vicinity of the concave portion 36 to form a plurality of first conductivity type regions 32 It is possible to effectively prevent recombination that may occur in combination with the carrier. The characteristics of the solar cell 100 do not deteriorate even when a large number of carriers of the semiconductor substrate 10 move toward the second conductivity type region 34 and the second portion 202 is located in the second conductivity type region 34 Can be sprung less.

However, the present invention is not limited thereto. The second portion 202 is biased toward the second conductivity type region 34 so that the width of the portion of the second portion 202 located on the side of the first conductivity type region 32 becomes the second conductivity type May be less than the width of the portion of the second portion 202 located on the region 34 side. Various other variations are possible.

Such a structure may be intentionally formed or may be formed by a process error or the like.

7 is a partial cross-sectional view illustrating a solar cell according to another embodiment of the present invention. 8 is a partial cross-sectional view of a solar cell according to a modification of FIG. Here, in Figs. 7 and 8, a portion corresponding to the enlargement circle in Fig. 1 is shown. 9 is a sectional view of a state including the semiconductor layer 30 before forming the concave portion 36 in the method of manufacturing the solar cell according to the embodiment shown in FIG. 9 is a cross-sectional view showing a process corresponding to FIG. 3K.

Referring to FIG. 7, in the present embodiment, the recesses 36 may not be formed in the entire thickness of the semiconductor layer 30 but may be formed only in a part of the semiconductor layer 30. A part of the semiconductor layer 30 is present under the recess 36 and the thickness of the portion where the recess 36 is formed may be smaller than the thickness of the portion where the recess 36 is not formed. As such, the recess 36 can be formed intentionally or by a process error.

Even if the concave portion 36 is not formed in the entire thickness and a part of the semiconductor layer 30 remains between the concave portion 36 and the second portion 202, the first conductive type region 32 and the second The area or the volume of the semiconductor layer 30 at the boundary portion of the conductive type region 34 can be reduced to reduce the occurrence of leakage current.

In this embodiment, the barrier region 38 is located at the boundary between the first conductivity type region 32 and the second conductivity type region 34 in this embodiment. That is, the barrier region 38 may be located between the recess 36 and the second portion 202, as shown in FIGS. Then, the leakage current can be further minimized when the barrier region 38 remains under the concave portion 36.

At this time, as shown in Fig. 7, the barrier region 38 may have a smaller width than the width of the concave portion 36 (in particular, the smallest width in the portion adjacent to the second portion 202). According to this, the area of the first and second conductivity type regions 32 and 34 can be maximized to improve the photoelectric conversion efficiency.

Alternatively, as shown in Fig. 8, the barrier region 38 may have a width larger than the width of the concave portion 36 (in particular, the largest width in the surface opposite to the second portion 202). In this case, a barrier region 38 may be additionally located between the first conductivity type region 32 and the recess 36 and a barrier region 38 may be formed between the second conductivity type region 34 and the recess 36 38) can be located. Thus, the barrier region 38 may be additionally disposed around the recess 36 to minimize the leakage current generated between the first conductive type region 32 and the second conductive type region 34. At this time, the width of the barrier region 38 may be larger or smaller than the width of the second portion 202, or may be the same.

In FIG. 8, the concave portion 38 is formed only in a part of the thickness of the semiconductor layer 30, but the present invention is not limited thereto. Therefore, as shown in Fig. 1, the concave portion 38 may be formed over the entire thickness of the semiconductor layer 30 so as to touch the second portion 202. The first conductive type region 32 and the second conductive type region 34 are entirely spaced and the barrier region 38 is formed between the recess 36 and the first and second conductive type regions 32 and 34, .

8 illustrates that the barrier region 38 is located between the first conductive type region 32 and the recessed portion 36 and between the second conductive type region 34 and the recessed portion 36, respectively. However, the present invention is not limited thereto, and the barrier region 38 may be formed only between the first conductive type region 32 and the concave portion 36, or between the second conductive type region 34 and the concave portion 36 . In particular, the barrier region 38 may be located only between the first conductive type region 32 and the recess 36 where there may be more problems due to recombination. At this time, the recesses 36 may be formed so as to correspond to all or a part of the thickness of the semiconductor layer 30.

The barrier region 38 may comprise a variety of materials capable of substantially insulating them between the first and second conductivity type regions 32 and 34. That is, an undoped (i.e., unshown) insulating material (e.g., oxide, nitride) or the like may be used for the barrier region 38. Alternatively, the barrier region 38 may comprise an intrinsic semiconductor. At this time, the first conductive type region 32, the second conductive type region 34, and the barrier region 38 are formed of the same semiconductor (for example, amorphous silicon, microcrystalline silicon, polycrystalline silicon, ), While the barrier region 38 may be substantially free of dopants. For example, a semiconductor layer containing a semiconductor material may be formed, and then a first conductive type dopant may be doped in a part of the semiconductor layer to form a first conductive type region 32, and a second conductive type dopant A region where the first conductivity type region 32 and the second conductivity type region 34 are not formed may constitute the barrier region 38. In this case, This makes it possible to simplify the manufacturing method of the first conductivity type region 32, the second conductivity type region 34, and the barrier region 38.

The semiconductor layer 30 having the concave portion 36 and the barrier region 38 of the above-described structure can be formed by various methods. For example, as shown in Fig. 9, in the step of forming the semiconductor layer 30 (the step corresponding to Fig. 3H) before forming the concave portion 38, the first and second conductivity type regions 32, 34, and a barrier region 38 can be formed. 3G, the semiconductor layer 30 includes a first doping layer 322 and a second semiconductor layer 322 located in the periphery of the undoped layer 324 when the opening 326a is formed in the mask layer 326. [ The mask layer 326 may be partially formed on the substrate 30, and may be formed by heat treatment as in the process shown in FIG. 3H. Next, as shown in FIG. 3I, when the concave portion 36 is formed in the portion where the barrier region 38 is located, a solar cell as shown in FIG. 7 or 8 can be manufactured.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
10: semiconductor substrate
20: Tunneling layer
201: First part
202: second part
204: depression
24: Passivation film
26: Antireflection film
30: semiconductor layer
32: first conductivity type region
34: second conductivity type region
36:
40: Insulating layer
42: first electrode
44: Second electrode

Claims (20)

A semiconductor substrate;
A tunneling layer comprising a first portion located on the semiconductor substrate and a second portion located partially on the first portion; And
The semiconductor layer located above the tunneling layer
/ RTI >
And the semiconductor layer has a concave portion located on the second portion. The method according to claim 1,
Wherein the semiconductor layer comprises a first conductive type region and a second conductive type region which are co-located on the tunneling layer,
Wherein the concave portion is located on the second portion between the first conductive type region and the second conductive type region. The method according to claim 1,
Wherein the concave portion is constituted by a spaced-apart space portion in which the semiconductor layer is not formed, or has a thickness less than other portions of the semiconductor layer. The method according to claim 1,
And the width of the second portion is larger than the width of the concave portion. 5. The method of claim 4,
The width of the concave portion: the width of the second portion is from 1: 1.12 to 1: 3. The method according to claim 1,
And the thickness of the second portion is larger than the thickness of the first portion. The method according to claim 6,
Wherein the first portion has a thickness of 2 nm or less,
And the thickness of the second portion is 3 nm or more. The method according to claim 1,
And the entire portion of the concave portion is located above the second portion. The method according to claim 1,
And the second portion is used as an etch stop layer. 3. The method of claim 2,
The first side adjacent to the first conductivity type region in the concave portion and the second side adjacent to the second conductivity type region in the concave portion have different slopes. 9. The method of claim 8,
Wherein the first conductivity type region has a p-type,
The second conductivity type region having n-type conductivity,
Wherein a slope of the second side is smaller than a slope of the first side. The method according to claim 1,
And a depression is formed in a portion corresponding to the concave portion in the second portion. The method according to claim 1,
Wherein the first portion and the second portion have the same material and composition and constitute a single layer. The method according to claim 1,
Wherein the first portion and the second portion have different materials or different compositions. The method according to claim 1,
And the second portion comprises an oxide. 3. The method of claim 2,
Wherein the first conductivity type region has a conductivity type different from that of the semiconductor substrate,
Wherein a width of a region where the second portion and the first conductivity type region overlap is larger than a width of an area where the second portion and the second conductivity type region overlap. Forming a tunneling layer on the semiconductor substrate, the tunneling layer comprising a first portion and a second portion that is partially over the first portion;
Forming a semiconductor layer overlying the tunneling layer; And
Forming a recess in the semiconductor layer corresponding to the second portion by partially etching the semiconductor layer located on the second portion
Lt; / RTI >
Wherein the step of forming the concave portion uses an etching solution having a selective etching ratio with respect to the second portion and the semiconductor layer. 18. The method of claim 17,
And the second portion is used as an etch stop layer in the step of forming the concave portion. 18. The method of claim 17,
Wherein in the step of forming the semiconductor layer, a p-type region and an n-type region which are located together on the tunneling layer and the n-type region is formed in a region where the recess is to be formed,
And forming the concave portion by etching the n-type region in the step of forming the concave portion. 18. The method of claim 17,
Wherein the semiconductor layer comprises silicon,
Said second portion comprising an oxide,
Wherein the etching solution comprises a potassium hydroxide solution.

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