KR20160040085A - Scan flop flop and Scan test circuit including the scan flip flip - Google Patents

Abstract

To improve space efficiency, a scan flip flop according to the present disclosure includes: an input part which selects any one of a data input signal and a scan input signal according to an operation mode and provides it as an internal signal; and a flip flop which has a cross couple structure which includes a first and a second tri-state inverters sharing a first output node and facing each other, and latches the internal signal according to a clock signal.

Description

A scan flip flop and a scan test circuit including the scan flip flop,

Technical aspects of the present disclosure relate to a flip-flop, and more particularly, to a scan test circuit including a scan flip-flop and a scan flip-flop.

As semiconductor chips are highly integrated, it takes a lot of time and resources to test semiconductor chips. Desing For Testability (DFT) technology is widely used to maintain the quality of semiconductor chips and improve test efficiency, among which scan test technology is a very important part.

A problem to be solved by the technical idea of the present disclosure is to provide a scan flip flop capable of improving space efficiency and a scan test circuit including the scan flip flop.

According to an aspect of the present invention, there is provided a scan flip flop including: an input unit for selecting one of a data input signal and a scan input signal according to an operation mode and providing the selected data as an internal signal; 2 < / RTI > tri-state inverters, and latches the internal signals according to a clock signal.

Also, a scan test circuit according to another aspect of the present disclosure includes first and second scan flip-flops, wherein at least one of the first and second scan flip-flops share a first output node, And a first and a second combinational logic circuit, the first combinational logic circuit including a flip flop having a cross-coupled structure including first and second three-phase inverters, Flop, wherein the second combinational logic circuit provides a second data input signal generated by a logical operation of an output signal of the first scan flip-flop to the first scan flip- 2 < / RTI > scan flip-flop.

According to the technical idea of the present disclosure, the scan flip-flop can improve the space efficiency by including the flip-flop circuit suitable for the cross-coupling structure. Specifically, the scan flip-flop has a cross-coupled structure including two three-phase inverters sharing the output node, thereby reducing the size of the cell in which the scan flip-flop is implemented. The cell in which the scan flip-flop is implemented can be divided into a plurality of units, wherein at least one unit has the cross-coupled structure so that two adjacent units can share the power terminal / ground terminal, Can be reduced.

1A is a block diagram that schematically illustrates a scan flip-flop in accordance with one embodiment of the present disclosure;
FIG. 1B is a logic symbol representing the scan flip flop of FIG. 1A.
2 is a block diagram illustrating a scan flip flop in accordance with one embodiment of the present disclosure.
3 is a circuit diagram showing a cross-coupled circuit according to an embodiment of the present disclosure;
4 is a layout showing the cross-coupled circuit of Fig.
5 is a circuit diagram illustrating a scan flip-flop according to one embodiment of the present disclosure;
FIG. 6 schematically shows a standard cell in which the scan flip-flop of FIG. 5 is implemented.
7 is a circuit diagram showing a scan flip-flop according to an embodiment of the present disclosure;
8 is a circuit diagram showing a modification of the scan flip-flop of FIG.
9 is a circuit diagram illustrating a scan flip-flop according to one embodiment of the present disclosure.
10 is a circuit diagram showing a modification of the scan flip-flop of FIG.
11 is a circuit diagram showing a scan flip-flop according to an embodiment of the present disclosure;
12 is a circuit diagram showing a modification of the scan flip-flop of Fig.
13 is a block diagram illustrating a scan chain including a scan flip-flop in accordance with one embodiment of the present disclosure;
14 is a block diagram illustrating a data processing apparatus including a scan flip-flop according to one embodiment of the present disclosure;
15 is a block diagram illustrating a scan test circuit including a scan flip flop in accordance with one embodiment of the present disclosure;
16 is a block diagram illustrating a computing system including a scan flip flop in accordance with one embodiment of the present disclosure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Also, the terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

The integrated circuit can be defined as a plurality of cells, and specifically, can be designed using a cell library including characteristic information of a plurality of cells. Here, the cell library may be defined with a cell name, a dimension, a gate width, a pin, a delay characteristic, a leakage current, a threshold voltage, and a function. A typical cell library set includes basic cells such as AND, OR, NOR, and inverters, complex cells such as OAI (OR / AND / INVERTER) and AOI (AND / OR / INVERTER) And a storage element such as a master-slave flip-flop and a latch.

In the embodiments of the present invention described below, a cell may be a standard cell, and a cell library may be a standard cell library. The standard cell method is a method of designing a dedicated large-scale integrated circuit (LSI) according to the specifications of a customer or a user by preparing standard cells having various functions in advance and arbitrarily combining standard cells. Standard cells are pre-designed and verified and registered on a computer. Logic design, placement, and routing are performed using a combination of standard cells using computer aided design (CAD).

Specifically, when a large-scale integrated circuit is designed / manufactured, if standardized logic circuit blocks (or cells) of a certain size are already stored in the library, a logic circuit block suited to the current design purpose is taken out of the library, And the entire circuit can be made by performing the optimum wiring in which the wiring length is the shortest in the wiring space between the cell and the cell. The more kinds of cells stored in the library, the more flexible the design and the more likely the optimum design of the chip.

FIG. 1A is a block diagram schematically illustrating a scan flip flop (SFF) according to one embodiment of the present disclosure, and FIG. 1B is a logic symbol showing the scan flip flop of FIG. 1A.

Referring to FIGS. 1A and 1B, the scan flip flop SFF may include an input unit IU and a flip flop FF. The input unit IU receives the data input signal D and the scan input signal SI and selects one of the data input signal D and the scan input signal SI according to the operation mode, . The flip-flop FF can latch the internal signal IS based on the clock signal CLK.

Specifically, the input unit 100 selects the data input signal D in the first operation mode and provides the internal signal IS based on the data input signal D, and in the second operation mode, the scan input signal SI And provides the internal signal IS based on the scan input signal SI. For example, the first mode of operation may be a normal operation mode for performing data transfer and the second mode of operation may be a scan test mode for performing a test operation.

In one embodiment, the operating mode may be determined according to the logic level of the scan enable signal SE. For example, the operation mode is a normal operation mode when the scan enable signal SE is at a first logic level (e. G., Logic low level) and the scan enable signal SE is at a second logic level For example, a logic high level), the present invention is not limited thereto.

In normal operating mode, input IU provides the data input signal D as an internal signal IS and the flip-flop FF can perform normal operation to latch the data input signal D. Meanwhile, in the scan test mode, the input unit IU may provide the scan input signal SI as an internal signal IS, and the flip-flop FF may perform a scan operation to latch the scan input signal SI .

2 is a block diagram showing the scan flip flop 10 in detail according to an embodiment of the present disclosure.

Referring to FIG. 2, the scan flip flop 10 may include a multiplexer 100, a master latch 200, and a slave latch 300. The scan flip flop 10 according to the present embodiment may be an embodiment of the scan flip flop SFF of FIG. Therefore, the above description with reference to FIG. 1 can also be applied to this embodiment, and a duplicated description will be omitted.

The multiplexer 100 may correspond to the input IU of FIG. However, the present invention is not limited to this, and the input unit IU of FIG. 1 may further include other components besides the multiplexer 100. The multiplexer 100 may select one of the data input signal D and the scan input signal SI according to the scan enable signal SE and provide the internal signal IS based on the selected signal. Multiplexer 100 may be referred to as a mux, a scan mux, or a selection unit. In one embodiment, the multiplexer 100 may be implemented to include a cross couple structure. The cross-coupling structure will be described in detail below with reference to Fig.

The master latch 200 and the slave latch 300 may correspond to the flip-flop FF of FIG. However, the present invention is not limited to this, and the flip-flop FF of FIG. 1 may further include other components besides the master latch 200 and the slave latch 300. The master latch 200 latches the internal signal IS based on the clock signal CLK and the slave latch 300 latches the output of the master latch 200 based on the clock signal CLK to generate an output signal OUT).

In one embodiment, the master latch 200 may be implemented to include a cross-coupled structure. In one embodiment, the slave latch 300 may be implemented to include a cross-coupled structure. In one embodiment, master latch 200 and slave latch 300 may both be implemented to include a cross-coupled structure.

3 is a circuit diagram showing a cross-coupled circuit (XCC) according to one embodiment of the present disclosure.

Referring to FIG. 3, the cross-coupled circuit XCC is a circuit having a cross-coupled structure, and may include a first tri-state inverter TIVTa and a second three-phase inverter TIVTb. In this embodiment, the first and second three-phase inverters TIVTa and TIVITb share the output node Y and can be arranged to face each other. This cross-coupled circuit XCC may be included as a component of the scan flip flop 10 of FIG. For example, the multiplexer 100, master latch 200, or slave latch 300 of FIG. 2 may include a cross-coupled circuit XCC.

The first three-phase inverter TIVTa may include a first pull-up unit PU1, a first PMOS transistor PM1, a first NMOS transistor NM1, and a first pull-down unit PD1. Specifically, the first pull-up unit PU1 may include a first pull-up transistor PU1a including a source connected to the power supply terminal VDD and a gate to which the first input signal IO is applied, The part PD1 may include a first pull-down transistor PD1a including a source connected to the ground terminal GND and a gate connected to the first input terminal IO.

The first PMOS transistor PM1 may include a source connected to the drain of the first pull-up transistor PU1a, a gate to which the first control signal A is applied, and a drain connected to the output node Y. [ The first NMOS transistor NM1 includes a drain coupled to the first PMOS transistor PM1 and the output node Y, a gate to which the second control signal B is applied, and a source coupled to the first pull- can do.

The second three-phase inverter TIVTb may include a second pull-up unit PU2, a second PMOS transistor PM2, a second NMOS transistor NM2, and a second pull-down unit PD2. Specifically, the second pull-up unit PU2 may include a second pull-up transistor PU2a including a source connected to the power supply terminal VDD and a gate to which the second input signal I1 is applied, The portion PD2 may include a second pull down transistor PD2a including a source connected to the ground terminal GND and a gate to which the second input signal I1 is applied.

The second PMOS transistor PM2 may include a source connected to the drain of the second pull-up transistor PU2a, a gate to which the second control signal B is applied, and a drain connected to the output node Y. [ The second NMOS transistor NM2 includes a drain connected to the second PMOS transistor PM2 and the output node Y, a gate to which the first control signal A is applied, and a source connected to the second pull-down transistor PD2a can do.

As described above, according to this embodiment, the first control signal A is applied to the gates of the first PMOS transistor PM1 and the second NMOS transistor NM2, and the first NMOS transistor NM1 and the second PMOS transistor NM2 And the second control signal B may be applied to the gates of the transistor PM2. Therefore, the first and second PMOS transistors PM1 and PM2 and the first and second NMOS transistors NM1 and NM2 may constitute a cross-coupling part XC.

Fig. 4 is a layout showing the cross-coupled circuit XCC of Fig.

4, the cross-coupled circuit XCC includes a first and a second active areas AR1 and AR2 as a part of a standard cell, a plurality of conductive lines CL, Drain contacts CA and a plurality of gate contacts CB. The standard cell including the cross-coupled circuit XCC can be defined by an upper boundary line UBL and a lower boundary line LBL and different circuits on the left and right sides .

The first active region AR1 and the second active region AR2 extend in a first direction (e.g., the X direction) and in a second direction substantially perpendicular to the first direction (e.g., in the Y direction As shown in FIG. At this time, the first active area AR1 may be disposed adjacent to the upper boundary line UBL, and the second active area AR2 may be disposed adjacent to the lower boundary line LBL.

The first active region AR1 and the second active region AR2 may have different conductivity types. The first and second active regions AR1 and AR2 may be referred to as diffusion regions. In one embodiment, the first active region AR1 may correspond to an N-type well and the second active region AR2 may correspond to a P-type well. In one embodiment, the substrate may be a P-type substrate and the substrate may be used as a second active region AR2.

Although not shown, the first active area AR1 may be provided with a plurality of first active pins extending along the first direction and arranged parallel to each other in the second direction, and the first active pins may be, for example, , A PMOS transistor can be constructed. Also, a plurality of second active pins extending in the first direction and arranged parallel to each other in the second direction may be disposed in the second active area AR2, and the second active pins may be disposed in the second active area AR2, for example, .

A dummy region DR may be disposed between the first active region AR1 and the second active region AR2. At this time, at least one dummy pin extending along the first direction and parallel to the first and second active pins may be disposed in the dummy area DR.

The plurality of conductive lines CL may extend along the second direction and may be disposed parallel to each other in the first direction. In this embodiment, the conductive lines CL may include first through fourth conductive lines CL1 through CL4 arranged in parallel with each other. At this time, the conductive lines CL may be made of any material having electrical conductivity, and may include, for example, polysilicon, metal, metal fitting, and the like. In one embodiment, the conductive lines CL may correspond to the gate electrodes. However, the present invention is not limited thereto, and the conductive lines CL may be a trace having any conductivity or the like.

In order to electrically isolate the second and third conductive lines CL2 and CL3 on the first active area AR1 from the second and third conductive lines CL2 and CL3 on the second active area AR2, A cutting layer (CT) can be placed in the dummy region. The cut layer CT may be a marking layer for cutting a part of the second conductive line CL2 and a part of the third conductive line CL3.

In the semiconductor device manufactured according to the layout including the cutting layer CT, the second conductive line CL2 is electrically connected to the second upper conductive line CL2a and the second active area AR2 on the first active area AR1, The second upper conductive line CL2a and the second lower conductive line CL2b can be electrically insulated from each other. The third conductive line CL3 can also be separated into a third upper conductive line CL3a on the first active area AR1 and a third lower conductive line CL3b on the second active area AR2, Accordingly, the third upper conductive line CL3a and the third lower conductive line CL3b can be electrically insulated.

A plurality of source / drain contacts CA may be disposed on the first and second active regions AR1 and AR2 so as to extend along the second direction. Each of the plurality of source / drain contacts CA may be disposed between two adjacent conductive lines CL. At this time, the plurality of source / drain contacts CA may be referred to as source / drain contact patterns or source / drain contact plugs.

A via V0 corresponding to the output node Y is formed on the source / drain contact CA disposed between the second upper conductive line CL2a and the third upper conductive line CL3a in the first active region AR1 . A via V0 corresponding to the output node Y is formed on the source / drain contact CA disposed between the second lower conductive line CL2b and the third upper conductive line CL3b in the second active region AR2 . Although not shown, the output node Y on the first active area AR1 and the output node Y on the second active area AR2 can be electrically connected through the metal line disposed on the top.

The plurality of gate contacts CB may be disposed on some regions of the first to fourth conductive lines CL1 to CL4 corresponding to the dummy region DR. At this time, the plurality of gate contacts CB may be referred to as gate contact patterns or gate contact plugs. Specifically, a first gate contact CB1 is disposed on the first conductive line CL1, a second upper gate contact CB2a is disposed on the second upper conductive line CL2a, and a second lower conductive line CL2b The third lower conductive contact CL3a is provided with the third lower conductive contact CL3a and the third lower conductive contact CL3b is provided with the third lower conductive contact CL3a, And a fourth gate contact CB4 may be disposed on the fourth conductive line CL4.

In one embodiment, the second and third top gate contacts CB2a, CB3a may be spaced apart by substantially the same distance in the lower boundary line LBL. In other words, the second and third top gate contacts CB2a, CB3a may be disposed at corresponding positions along the first direction. In one embodiment, the second and third bottom gate contacts CB2b, CB3b may be spaced apart by substantially the same distance in the lower boundary line LBL. In other words, the second and third bottom gate contacts CB2b and CB3b may be disposed at corresponding positions along the first direction.

The first input signal I0 may be applied through the first gate contact CB1 and the first input signal I0 may be transmitted to the first conductive line CL1. The second input signal I1 may be applied through the fourth gate contact CB4 and the second input signal I2 may be transmitted to the fourth conductive line CL4. The first control signal A may be applied through the second upper gate contact CB2a and the third lower gate contact CB3b and the first control signal A may be applied to the second upper conductive line CL2a and 3 lower conductive line CL3b, respectively. The second control signal B may be applied through the second lower gate contact CB2b and the third upper gate contact CB3a and the second control signal B may be applied through the second lower conductive line CL2b and 3 upper conductive line CL3a, respectively.

At this time, a via V0 for electrically connecting each gate contact and the upper metal line may be formed on each gate contact. At this time, the via V0 may be formed in a dimension substantially similar to each gate contact. In some embodiments, vias V0 may not be formed on top of one of the second bottom gate contact CB2b and the third top gate contact CB3a.

According to the present embodiment, the cross-coupled circuit XCC may further include a diagonal contact CAd connecting the second lower gate contact CB2b and the third upper gate contact CB3a. At this time, the oblique line contact CAd may be formed to extend in the diagonal direction so that the distance between the second bottom gate contact CB2b and the third top gate contact CB3a, which are different from the distance from the lower boundary line LBL, ) Can be electrically connected. In one embodiment, the diagonal contact (CAd) may be formed in the same process step as the plurality of source / drain contacts (CA).

In one embodiment, the height from the substrate to the top surface of the oblique contact (CAd) may be substantially the same as the second bottom gate contact (CB2b) and the third top gate contact (CB3a). In other words, the height from the substrate to the top surface of the oblique contact CAd is the height from the substrate to the top surface of the second bottom gate contact CB2b and from the substrate to the top surface of the third top gate contact CB3a . ≪ / RTI >

In one embodiment, a via V0 is formed on the second bottom gate contact CB2b and a second control signal B is applied through the via V0 to connect the third top Gate contact CB3a. In one embodiment, a via V0 is formed on the third top gate contact CB3a and a second control signal B is applied through the via V0 to connect the second bottom Gate contact CB2b.

Conventional cross-coupled portions did not include a cut-off layer and an oblique contact, and thus could be implemented in regions corresponding to three conductive lines. In other words, the conventional cross-coupled portion can be designed in a region corresponding to three grids. Here, the grid may correspond to an area corresponding to the number of conductive lines, and may be referred to as a contact poly pitch (CPP).

In the present embodiment, the cross-coupling portion XC includes the cut layer CT, the second and third top gate contacts CB2a and CB3a, the second and third bottom gate contacts CB2b and CB3b, Can be implemented in the region corresponding to the two conductive lines, i.e., the second and third conductive lines CL2 and CL3, using the contact CAd. In other words, the cross-coupling portion XC according to the present embodiment can be designed into two grids or two CPPs. Therefore, the area occupied by the cross-coupled portion XC according to the present embodiment is reduced in comparison with the prior art, so space efficiency can be improved.

5 is a circuit diagram showing a scan flip-flop 10A according to one embodiment of the present disclosure.

5, the scan flip-flop 10A may include a multiplexer 100a, a master latch 200a, and a slave latch 300a, and may further include peripheral circuits 410 to 440. Referring to FIG. The scan flip flop 10A according to the present embodiment may be an embodiment of the scan flip flop 10 of FIG. 2, and the above description with reference to FIG. 2 may also be applied to this embodiment.

The multiplexer 100a may be implemented as the cross-coupled circuit XCC illustrated in FIG. Specifically, the multiplexer 100a may include first and second three-phase inverters 110 and 120 sharing the first output node ND1, and the signal output from the first output node ND1 may be a signal Lt; RTI ID = 0.0 > IS. ≪ / RTI > The first three-phase inverter 110 may invert the data input signal D based on the scan enable signal SE and the reverse scan enable signal NSE and the second three-phase inverter 120 may enable the scan enable The scan input signal SI can be inverted based on the signal SE and the inverted scan enable signal NSE. The inverter 420 can output the inverted scan enable signal NSE by inverting the scan enable signal SE.

The first three-phase inverter 110 includes a first pull-up transistor 111 connected to the first power terminal P1, a first PMOS transistor 112 connected between the first pull-up transistor 111 and the first output node ND1, A first NMOS transistor 113 connected to the first output node ND1 and a first pull-down transistor 114 connected between the first NMOS transistor 113 and the first ground terminal G1.

Specifically, the first pull-up transistor 111 may include a source coupled to the first power terminal P1 and a gate to which the data input signal D is applied, and the first PMOS transistor 112 may include a first pull- A source coupled to the drain of the transistor 111, a gate to which the sense enable signal SE is applied, and a drain coupled to the first output node ND1. The first NMOS transistor 113 may include a drain coupled to the first output node ND1 and a gate to which the inverted sense enable signal NSE is applied and the first pull- A drain connected to the source of the first transistor 113, a gate to which the data input signal D is applied, and a source connected to the first ground terminal G1.

The second three-phase inverter 120 includes a second pull-up transistor 121 connected to the second power supply terminal P2, a second PMOS transistor 122 connected between the second pull-up transistor 121 and the first output node ND1, A second NMOS transistor 123 connected to the first output node ND1 and a second pull-down transistor 124 connected between the second NMOS transistor 123 and the second ground terminal G2.

Specifically, the second pull-up transistor 121 may include a source coupled to the second power supply terminal P2 and a gate to which the scan input signal SI is applied, and the second PMOS transistor 122 may include a second pull- A source connected to the drain of the transistor 121, a gate to which the inverted sense enable signal NSE is applied, and a drain connected to the first output node ND1. The second NMOS transistor 123 may include a drain coupled to the first output node ND1 and a gate to which the sense enable signal SE is applied and the second pull down transistor 124 may include a second NMOS transistor 123, a gate to which the scan input signal SI is applied, and a source connected to the second ground terminal G2.

In this embodiment, the sense enable signal SE is applied to the gates of the first PMOS transistor 112 and the second NMOS transistor 123, and the first NMOS transistor 113 and the second PMOS transistor 122, The inversion sense enable signal NSE may be applied to the gates of the transistors Q1 and Q2. Accordingly, the first and second PMOS transistors 112 and 122 and the first and second NMOS transistors 113 and 123 may constitute the first cross-coupled portion XC1. The first cross-coupling portion XC1 can be implemented in the layout illustrated in FIG. 4, so that the first cross-coupling portion XC1 can be designed into two grids or two CPPs.

The master latch 200a may be implemented as the cross-coupled circuit XCC illustrated in FIG. Specifically, the master latch 200a may include third and fourth three-phase inverters 210 and 220 that share a second output node ND2, and may further include a first inverter 230 . The third three-phase inverter 210 can invert the output of the multiplexer 110a, that is, the signal of the first output node ND1 based on the buffered clock signal BCLK and the inverted clock signal NCLK, The four-phase inverter 220 can reverse the output of the first inverter 230, that is, the signal of the third output node ND3, based on the buffered clock signal BCLK and the inverted clock signal NCLK. At this time, the inverter 430 inverts the clock signal CLK to output the inverted clock signal NCLK, and the inverter 440 inverts the inverted clock signal NCLK to output the buffered clock signal BCLK can do.

The third three-phase inverter 210 includes a third pull-up transistor 211 connected to the second power supply terminal P2, a third PMOS transistor 212 connected between the third pull-up transistor 211 and the second output node ND2, A third NMOS transistor 213 connected to the second output node ND2 and a third pull-down transistor 214 connected between the third NMOS transistor 213 and the second ground terminal G2.

Specifically, the third pull-up transistor 211 may include a source coupled to the second power terminal P2 and a gate coupled to the first output node ND1, and the third PMOS transistor 212 may include a third pull- A source coupled to the drain of the first output node 211, a gate to which the buffered clock signal BCLK is applied, and a drain coupled to the second output node ND2. The third NMOS transistor 213 may include a drain connected to the second output node ND2 and a gate to which the inverted clock signal NCLK is applied and the third pull down transistor 214 may include a third NMOS transistor 213 , A gate coupled to the first output node ND1, and a source coupled to the second ground terminal G2.

The fourth four-phase inverter 220 includes a fourth pull-up transistor 221 connected to the third power supply terminal P3, a fourth PMOS transistor 222 connected between the fourth pull-up transistor 221 and the second output node ND2, A fourth NMOS transistor 223 connected to the second output node ND2 and a fourth pull-down transistor 224 connected between the fourth NMOS transistor 223 and the third ground terminal G3.

Specifically, the fourth pull-up transistor 221 may include a source coupled to the third power terminal P3 and a gate coupled to the third output node ND3, and the fourth PMOS transistor 222 may include a fourth pull- A source connected to the drain of the first output node 221, a gate to which the inverted clock signal NCLK is applied, and a drain connected to the second output node ND2. The fourth NMOS transistor 223 may include a drain connected to the second output node ND2 and a gate to which the buffered clock signal BCLK is applied and the fourth pull down transistor 224 may include a fourth NMOS transistor 223, a gate connected to the third output node ND3, and a source connected to the third ground terminal G3.

The third NMOS transistor 213 and the fourth PMOS transistor 222 are applied with the clock signal BCLK buffered in the gates of the third PMOS transistor 212 and the fourth NMOS transistor 223, The inverted clock signal NCLK may be applied to the gates of the flip-flops. Accordingly, the third and fourth PMOS transistors 212 and 222 and the third and fourth NMOS transistors 213 and 223 may constitute a second cross coupling portion XC2. The second cross coupling portion XC2 can be implemented in the layout illustrated in Fig. 4, whereby the second cross coupling portion XC2 can be designed into two grids or two CPPs.

The master latch included in the conventional scan flip-flop includes the output of the multiplexer, that is, the transfer gate for receiving the internal signal, and provides the internal signal to the output node without inverting. At this time, since the transfer gate can be implemented by two transistors, the number of transistors is smaller than that of the third three-phase inverter 210 according to the present embodiment. However, according to the related art, since the merge of the power terminal / ground terminal is not performed between the multiplexer and the master latch, the cell area can not be further reduced, and the space efficiency is lowered.

According to the present embodiment, the master latch 200a includes a third three-phase inverter 210 receiving the output of the multiplexer 100a to invert the signal of the first output node ND1 to form a second output node ND2 ). At this time, since the third three-phase inverter 210 can be implemented with four transistors 211 to 214, the number of transistors is larger than that of the prior art. However, according to the present embodiment, a merge of the power terminal / ground terminal may occur between the second three-phase inverter 120 included in the multiplexer 100a and the third three-phase inverter 210 included in the master latch 200a Thus, additionally, the cell area can be reduced.

Specifically, the second three-phase inverter 120 included in the multiplexer 100a and the third three-phase inverter 210 included in the master latch 200a may be disposed adjacent to each other in the first direction. Accordingly, the second three-phase inverter 120 and the third three-phase inverter 210 can share the second power supply terminal P2 and the second ground terminal G2. In other words, the power supply terminal of the third three-phase inverter 210 can be merged to the second power supply terminal P2 of the second three-phase inverter 120, and the ground terminal of the third three- May be merged to the second ground terminal (G2) of the second transistor (120). Thus, the size of the area required to implement the multiplexer 110a and the master latch 200a may be further reduced by, for example, one to two grids.

The slave latch 300a may include a transfer gate 310 and a fifth three-phase inverter 320, and may further include a second inverter 330. [ The transfer gate 310 transfers the output of the master latch 200a, that is, the signal of the third output node ND3 to the fourth output node ND4, based on the buffered clock signal BCLK and the inverted clock signal NCLK. . The second inverter 330 inverts the signal of the fourth output node ND4 and the fifth three-phase inverter 320 inverts the signal of the fourth output node ND4 based on the buffered clock signal BCLK and the inverted clock signal NCLK, The signal of the node ND5 can be inverted.

The fifth three-phase inverter 320 includes a fifth pull-up transistor 321 connected to the fourth power supply terminal P4, a fifth PMOS transistor 322 connected between the fifth pull-up transistor 321 and the fourth output node ND4, A fifth NMOS transistor 323 connected to the fourth output node ND4 and a fifth pull-down transistor 324 connected between the fifth NMOS transistor 323 and the fourth ground terminal G4.

Specifically, the fifth pull-up transistor 321 may include a source connected to the fourth power supply terminal P4 and a gate connected to the fifth output node ND5, and the fifth PMOS transistor 322 may include a fifth pull- A source coupled to the drain of the first output node 321, a gate to which the buffered clock signal BCLK is applied, and a drain coupled to the fourth output node ND4. The fifth NMOS transistor 323 may include a drain coupled to the fourth output node ND4 and a gate to which the inverted clock signal NCLK is applied and the fifth pull-down transistor 324 may include a fifth NMOS transistor 323 A gate connected to the fifth output node ND5, and a source connected to the fourth ground terminal G4.

The transfer gate 310 may include a sixth PMOS transistor 311 and a sixth NMOS transistor 312. The sixth PMOS transistor 311 may be connected between the third output node ND3 and the fourth output node ND4 and may include a gate to which the inverted clock signal NCLK is applied. The sixth NMOS transistor 312 may be connected between the third output node ND3 and the fourth output node ND4 and may include a gate to which the buffered clock signal BCLK is applied.

The second inverter 330 may include a sixth pull-up transistor 331 and a sixth pull-down transistor 332. The sixth pull-up transistor 331 may include a source coupled to the fourth power supply terminal P4, a gate coupled to the fourth output node ND4, and a drain coupled to the fifth output node ND5. The sixth pull-down transistor 332 may include a drain coupled to the fifth output node ND5, a gate coupled to the fourth output node ND4, and a source coupled to the fourth ground terminal G4.

In this embodiment, the buffered clock signal BCLK is applied to the gates of the fifth PMOS transistor 322 and the sixth NMOS transistor 312 and the fifth NMOS transistor 323 and the sixth PMOS transistor 311, The inverted clock signal NCLK may be applied to the gates of the flip-flops. Accordingly, the fifth and sixth PMOS transistors 322 and 311 and the fifth and sixth NMOS transistors 323 and 312 may constitute a third cross coupling portion XC3. The third cross coupling portion XC3 can be implemented in the layout illustrated in Fig. 4, and thus the third cross coupling portion XC3 can be designed into two grids or two CPPs.

Therefore, according to the present embodiment, the multiplexer 100a includes the first cross coupler XC1, the master latch 200a includes the second cross coupler XC2, and the slave latch 300a includes the first cross- 3 cross coupling portion XC3, the cell size of the scan flip-flop 10A can be reduced by three grids compared with the conventional one. Furthermore, according to the present embodiment, since the master latch 200a includes the third three-phase inverter 210 instead of the general inverter, the cell size of the scan flip-flop 10A can be further reduced by one to two grids .

FIG. 6 schematically shows a standard cell 10B in which the scan flip-flop of FIG. 5 is implemented.

6, the standard cell 10B is defined by a cell boundary CB and may include a multiplexer 100b, a master latch 200b, and a slave latch 300b, for example, Other functional units such as peripheral circuits 420, 430, and 440 of FIG. The multiplexer 100b may include the multiplexer 100a of FIG. 5, and may further include other components. The master latch 200b may include the master latch 200a of FIG. 5, and may further include other components. The slave latch 300b may include the slave latch 300a of Fig. 5, and may further include other components. Therefore, the above-described contents with reference to Fig. 5 can also be applied to this embodiment.

The multiplexer 100b may include a first cross coupling portion XC1 and the first three-phase inverter 110 may be connected between the first power terminal P1 and the first ground terminal G1, The inverter 120 may be connected between the second power supply terminal P2 and the second ground terminal G2. The first cross-coupling portion XC1 can be implemented as shown in FIG. 4, and can obtain one grid gain with respect to the size of the multiplexer 100b. The master latch 200b may include the second cross coupling portion XC2 and the third three-phase inverter 210 may be connected between the second power supply terminal P2 and the second ground terminal G2, The three-phase inverter 220 may be connected between the third power supply terminal P3 and the third ground terminal G3. The second cross coupling unit XC2 can be implemented as shown in FIG. 4, and can obtain one grid gain for the size of the master latch 200b.

The slave latch 300b may include a third cross coupling portion XC3 and the fifth three-phase inverter 320 may be connected between the fourth power terminal P4 and the fourth ground terminal G4. The third cross coupling unit XC3 can be implemented as shown in FIG. 4, and can obtain one grid gain with respect to the size of the slave latch 300b. The multiplexer 100b and the master latch 200b may share the second power terminal P2 and the second ground terminal G2 so that the size of the multiplexer 100b and the master latch 200b may be 1 2 You can acquire more grid gain. Therefore, for the entire size of the standard cell 10B in which the scan flip-flop is implemented, 4 to 5 grid gains can be obtained compared to the conventional case.

7 is a circuit diagram showing a scan flip-flop 20A according to one embodiment of the present disclosure.

7, the scan flip flop 20A according to the present embodiment may be a scan flip flop having a reset function and includes a multiplexer 100a, a master latch 200c, and a slave latch 300c can do. The scan flip-flop 20A is a modified embodiment of the scan flip-flop 10A shown in Fig. 5. Hereinafter, the difference between the scan flip-flop 10A of Fig. 5 and the scan flip- I will explain it mainly. In this instance, the same reference numerals refer to the same elements, and a duplicate description will be omitted.

The master latch 200c may include a third three-phase inverter 210a, a fourth three-phase inverter 220, a first inverter 230, and a first reset switch 510. The first reset switch 510 may include an NMOS transistor 511 including a drain connected to the second output node ND2, a gate to which the reset control signal R is applied, and a source connected to the ground terminal. The reset control signal R is a signal for controlling the reset operation. When the reset control signal R is activated, that is, when the reset control signal R is in a logical high state, the first reset switch 510 is turned on , The voltage of the second output node ND2 may be at the ground level, and accordingly, the output of the master latch 200c may be reset.

The third three-phase inverter 210a includes a second reset switch 520, a third pull-up transistor 211a, a third PMOS transistor 212, a third NMOS transistor 213 and a third pull-down transistor 214 . The second reset switch 520 may include a PMOS transistor 521 including a source connected to the second power supply terminal P2 and a gate to which the reset control signal R is applied. The source of the third pull-up transistor 211a may be connected to the drain of the PMOS transistor 521. [ When the reset control signal R is activated, the second reset switch 520 is turned off and the power supply voltage can not be supplied to the second output node ND2.

The slave latch 300c may include a transfer gate 310, a fifth three-phase inverter 320, a second inverter 330a, and a third reset switch 530. The third reset switch 530 may include an NMOS transistor 531 including a drain connected to the fifth output node ND5, a gate to which the reset control signal R is applied, and a source connected to the ground terminal. When the reset control signal R is activated, the third reset switch 530 is turned on and the voltage of the fifth output node ND5 can be ground level.

The second inverter 330a may include a fourth reset switch 540, a sixth pull-up transistor 331a, and a sixth pull-down transistor 332. [ The fourth reset switch 540 may include a PMOS transistor 541 including a source connected to the fourth power terminal P4 and a gate to which the reset control signal R is applied. The source of the sixth pull-up transistor 331a may be connected to the drain of the PMOS transistor 541. [ When the reset control signal R is activated, the fourth reset switch 540 is turned off, so that no power supply voltage is provided to the fifth output node ND5.

According to the present embodiment, the multiplexer 100a, the master latch 200c and the slave latch 300c included in the scan flip-flop 20A having the reset function are respectively connected to the scan flip- And a cross-coupling portion. For example, the multiplexer 100a, the master latch 200c, and the slave latch 300c may include first through third cross coupling portions XC1, XC2, and XC3, respectively, and the first through third cross- Since the units XC1, XC2, and XC3 can be implemented as shown in FIG. 4, three grid gains can be obtained. Further, since the multiplexer 100a and the master latch 200c can share the second power terminal P2 and the second ground terminal G2, the size of the multiplexer 100a and the master latch 200c can be set to 1 2 You can acquire more grid gain.

According to the present embodiment, the scan flip-flop 20A can perform the reset operation based on the reset control signal R for instructing the reset operation. For example, the scan flip-flop 20A may perform a normal operation or a scan test operation in response to a reset control signal R having a logic low level, and may perform a reset operation in response to a reset control signal R having a logic high level Operation can be performed.

8 is a circuit diagram showing a modification 20B of the scan flip-flop of Fig.

8, the scan flip flop 20B according to the present embodiment may be a scan flip flop having a reset function and may include a multiplexer 100a, a master latch 200d and a slave latch 300c . The scan flip-flop 20B is a modification of the scan flip-flop 20A of Fig. 7, and will be described below with reference to the difference between the scan flip-flop 20A of Fig. 7 and the scan flip- I will explain. In this instance, the same reference numerals refer to the same elements, and a duplicate description will be omitted.

The fourth three-phase inverter 220a included in the master latch 200d includes a fifth reset switch 550, a fourth pull-up transistor 221a, a fourth PMOS transistor 222, a fourth NMOS transistor 223, Pull-down transistor 224. The fifth reset switch 550 may include a PMOS transistor 551 including a source connected to the third power terminal P3 and a gate to which the reset control signal R is applied. The source of the fourth pull-up transistor 221a may be connected to the drain of the PMOS transistor 551. [

According to the present embodiment, when the reset control signal R is activated, the fifth reset switch 550 is turned off, and the power supply voltage can not be supplied to the second output node ND2. Thus, even when the driving force of the fourth pull-up transistor 221a is high, the second output node ND2 can stably output the ground voltage.

9 is a circuit diagram showing a scan flip-flop 30A according to an embodiment of the present disclosure.

9, the scan flip flop 30A according to the present embodiment may be a scan flip flop having a set function, and may include a multiplexer 100a, a master latch 200e, and a slave latch 300d . The scan flip-flop 30A is a modified embodiment of the scan flip-flop 10A shown in Fig. 5. Hereinafter, the difference between the scan flip-flop 10A of Fig. 5 and the scan flip- I will explain it mainly. In this instance, the same reference numerals refer to the same elements, and a duplicate description will be omitted.

The master latch 200e may include a third three-phase inverter 210b, a fourth three-phase inverter 220, a first inverter 230, and a first set switch 610. The first set switch 610 may include a PMOS transistor 611 including a source coupled to a power terminal, a gate to which an inverted set control signal SN is applied, and a drain coupled to a second output node ND2 . At this time, the inverted set control signal SN may be a signal whose set control signal S controlling the set operation is inverted. When the set control signal S is activated, that is, when the inversion set control signal SN is in a logic low state, the first set switch 610 is turned on and the voltage of the second output node ND2 is set to the power supply voltage level , So that the output of the master latch 200e can be set.

The third three-phase inverter 210b includes a third pull-up transistor 211, a third PMOS transistor 212, a third NMOS transistor 213, a third pull-down transistor 214a and a second set switch 620 . The second set switch 620 may be an NMOS transistor 621 including a gate to which the inverted set control signal SN is applied and a source coupled to the second ground terminal G2. The source of the third pull-down transistor 214a may be connected to the drain of the NMOS transistor 621. [ When the set control signal S is activated, the second set switch 520 is turned off and the ground voltage can not be provided to the second output node ND2.

The slave latch 300d may include a transfer gate 310, a fifth three-phase inverter 320, a second inverter 330b, and a third set switch 630. The third set switch 630 may include a PMOS transistor 631 including a source coupled to a power supply terminal, a gate to which an inverted set control signal SN is applied, and a drain coupled to a fifth output node ND5 . When the set control signal S is activated, the third set switch 630 is turned on and the voltage of the fifth output node ND5 may be the power supply voltage level.

The second inverter 330b may include a sixth pull-up transistor 331, a sixth pull-down transistor 332a, and a fourth set switch 640. The fourth set switch 640 may include an NMOS transistor 641 including a source coupled to a fourth ground terminal G4 and a gate to which an inverted set control signal SN is applied. The source of the sixth pull-down transistor 332a may be connected to the drain of the NMOS transistor 641. [ When the set control signal S is activated, the fourth set switch 640 is turned off, so that no ground voltage is provided to the fifth output node ND5.

The scan flip flop 30A having the set function according to the present embodiment is configured such that the multiplexer 100a, the master latch 200e and the slave latch 300d operate as a scan flip flop 10A illustrated in FIG. 5, . For example, the multiplexer 100a, the master latch 200e, and the slave latch 300d may include first through third cross coupling portions XC1, XC2, and XC3, respectively, and the first through third cross- Since the units XC1, XC2, and XC3 can be implemented as shown in FIG. 4, three grid gains can be obtained. Further, since the multiplexer 100a and the master latch 200e can share the second power terminal P2 and the second ground terminal G2, the size of the multiplexer 100a and the master latch 200e is 1 to 2 You can acquire more grid gain.

According to the present embodiment, the scan flip-flop 30A can perform the set operation based on the set control signal S indicating the set operation. For example, the scan flip-flop 30A may perform a normal operation or a scan test operation in response to a set control signal S having a logic low level, Operation can be performed.

10 is a circuit diagram showing a modification 30B of the scan flip-flop of Fig.

10, the scan flip flop 30B according to the present embodiment may be a scan flip flop having a set function, and may include a multiplexer 100a, a master latch 200f, and a slave latch 300d . The scan flip-flop 30B is a modified embodiment of the scan flip-flop 30A shown in Fig. 9 and will be described below with reference to the difference between the scan flip-flop 30A of Fig. 9 and the scan flip- I will explain. In this instance, the same reference numerals refer to the same elements, and a duplicate description will be omitted.

The fourth three-phase inverter 220b included in the master latch 200f includes a fourth pull-up transistor 221, a fourth PMOS transistor 222, a fourth NMOS transistor 223, a fourth pulldown transistor 224a, And may include a set switch 650. The fifth set switch 650 may include an NMOS transistor 651 including a source connected to the third ground terminal G3 and a gate to which the inverted set control signal SN is applied. The source of the fourth pull-down transistor 224a may be connected to the drain of the NMOS transistor 651. [

According to this embodiment, when the set control signal SN is activated, the fifth set switch 650 is turned off, and the ground voltage can not be provided to the second output node ND2. Thus, even when the driving force of the fourth pull-down transistor 224a is high, the second output node ND2 can stably output the power supply voltage.

11 is a circuit diagram showing a scan flip-flop 40A according to an embodiment of the present disclosure.

11, the scan flip-flop 40A according to the present embodiment may be a scan flip flop having a set / reset function and includes a multiplexer 100a, a master latch 200g and a slave latch 300e . The scan flip-flop 40A is a modification of the scan flip-flop 10A shown in Fig. 5, and the difference between the scan flip-flop 10A of Fig. 5 and the scan flip- I will explain it mainly. In this instance, the same reference numerals refer to the same elements, and a duplicate description will be omitted.

The master latch 200g may include a third three-phase inverter 210c, a fourth three-phase inverter 220, a first inverter 230, and a first set / reset switch 710. The first set / reset switch 710 includes a PMOS transistor 711 connected between the power supply terminal and the second output node ND2, NMOS transistors 712, 712 connected in series between the second output node ND2 and the ground terminal, 713). The PMOS transistor 711 and the NMOS transistor 712 can be turned on and off by the inverted set control signal SN and the NMOS transistor 713 can be turned on and off by the reset control signal R.

When the reset control signal R is activated and the set control signal S is deactivated, the PMOS transistor 711 and the NMOS transistor 712 are turned off and the NMOS transistor 713 is turned on, The voltage can be at the ground voltage level, so that the output of the master latch 200g can be reset. On the other hand, when the reset control signal R is inactivated and the set control signal S is activated, the PMOS transistor 711 and the NMOS transistor 712 are turned on and the NMOS transistor 713 is turned off, May be the power supply voltage level, and accordingly, the output of the master latch 200g may be set.

The third three-phase inverter 210c includes a first reset switch 720, a third pull-up transistor 211b, a third PMOS transistor 212, a third NMOS transistor 213, a third pull-down transistor 214b, And may include a set switch 730. The first reset switch 720 may be a PMOS transistor 721 including a source connected to the second power supply terminal P2 and a gate to which the reset control signal R is applied. When the reset control signal R is activated, the first reset switch 720 is turned off, so that the power supply voltage can not be supplied to the second output node ND2. The first set switch 730 may be an NMOS transistor 731 including a source connected to the second ground terminal G2 and a gate to which the inverted set control signal SN is applied. When the set control signal S is activated, the first set switch 730 is turned off, so that the ground voltage can not be supplied to the second output node ND2.

The slave latch 300e may include a transfer gate 310, a fifth three-phase inverter 320, a second inverter 330c, and a second set / reset switch 740. The second set / reset switch 740 includes a PMOS transistor 741 including a source connected to the power supply terminal, a gate to which the inverted set control signal SN is applied, and a drain connected to the fifth output node ND5, A drain coupled to the fifth output node ND5, and a gate to which a reset control signal R is applied. When the reset control signal R is activated, the NMOS transistor 742 is turned on and the voltage of the fifth output node ND5 can be grounded. On the other hand, when the set control signal S is activated, the PMOS transistor 741 is turned on and the voltage of the fifth output node ND5 becomes the power supply voltage level.

The second inverter 330c may include a second reset switch 750, a sixth pull-up transistor 331b, a sixth pull-down transistor 332b, and a second set switch 760. The second reset switch 750 may include a PMOS transistor 751 including a source connected to the fourth power terminal P4 and a gate to which the reset control signal R is applied. The source of the sixth pull-up transistor 331b is connected to the drain of the second reset switch 750. [ When the reset control signal R is activated, the second reset switch 750 is turned off, so that no power supply voltage is provided to the fifth output node ND5.

The second set switch 760 may include an NMOS transistor 761 including a source coupled to a fourth ground terminal G4 and a gate to which an inverted set control signal SN is applied. The source of the sixth pull-down transistor 332b may be connected to the drain of the NMOS transistor 761 and the source of the NMOS transistor 742. [ When the set control signal S is activated, the second set switch 760 is turned off, so that no ground voltage is provided to the fifth output node ND5.

The scan flip flop 40A having the set / reset function according to the present embodiment has a configuration in which the multiplexer 100a, the master latch 200g and the slave latch 300e are connected to each other as a scan flip flop 10A, And a coupling portion. For example, the multiplexer 100a, the master latch 200g, and the slave latch 300e may include first through third cross coupling portions XC1, XC2, and XC3, respectively, and the first through third cross- Since the units XC1, XC2, and XC3 can be implemented as shown in FIG. 4, three grid gains can be obtained. Further, since the multiplexer 100a and the master latch 200g can share the second power terminal P2 and the second ground terminal G2, the size of the multiplexer 100a and the master latch 200g is 1 to 2 You can acquire more grid gain.

According to the present embodiment, the scan flip-flop 40A can perform the reset operation based on the reset control signal R for instructing the reset operation, and can set the set control signal S based on the set control signal S Operation can be performed. For example, the scan flip-flop 40A may perform a normal operation or a scan test operation in response to a reset control signal R having a logic low level, and may perform a reset operation in response to a reset control signal R having a logic high level Operation can be performed. In addition, the scan flip-flop 40A can perform a normal operation or a scan test operation in response to the set control signal S having a logic low level, Operation can be performed.

12 is a circuit diagram showing a modification 40B of the scan flip-flop of Fig.

12, the scan flip flop 40B according to the present embodiment may be a scan flip flop having a set / reset function and includes a multiplexer 100a, a master latch 200h and a slave latch 300e . The scan flip-flop 40B is a modified embodiment of the scan flip-flop 40A of Fig. 11 and will be described below with reference to the difference between the scan flip-flop 40A of Fig. 11 and the scan flip- I will explain. In this instance, the same reference numerals refer to the same elements, and a duplicate description will be omitted.

The fourth three-phase inverter 220c included in the master latch 200h includes a third reset switch 770 connected to the third power supply terminal P3, a fourth pull-up transistor 221b, a fourth PMOS transistor 222, 4 NMOS transistor 223, a fourth pull-down transistor 224b, and a third set 780. The third reset switch 770 may include a PMOS transistor 771 including a source coupled to the third power terminal P3 and a gate to which the reset control signal R is applied. The source of the fourth pull-up transistor 221b may be connected to the drain of the PMOS transistor 771. [ The third set switch 780 may include an NMOS transistor 772 including a source coupled to the third ground terminal G3 and a gate to which an inverted set control signal SN is applied. The source of the fourth pull-down transistor 224b may be connected to the drain of the NMOS transistor 772. [

According to this embodiment, when the reset control signal R is activated, the third reset switch 770 is turned off, and the power supply voltage can not be supplied to the second output node ND2. Thus, even when the driving force of the fourth pull-up transistor 221b is high, the second output node ND2 can stably output the ground voltage. Further, when the set control signal S is activated, the third set switch 780 is turned off, and the ground voltage can not be provided to the second output node ND2. Thus, even when the driving force of the fourth pull-down transistor 224b is strong, the second output node ND2 can stably output the power supply voltage.

13 is a block diagram illustrating a scan chain 50 that includes a scan flip flop in accordance with one embodiment of the present disclosure.

13, the scan chain 50 may include a plurality of scan flip-flops 10a to 10c, and each scan flip-flop 10a to 10c may include a scan flip- As shown in FIG. Each scan flip-flop 10a-10c may be fabricated using standard cells stored in a standard cell library. For example, a standard cell may be designed as shown in FIG.

Each scan flip-flop 10a-10c may include a first terminal D for receiving a data input signal and a second terminal SI for receiving a scan input signal, have. Specifically, the first scan flip flop 10a includes a first terminal D for receiving the input data DIN and a second terminal SI for receiving the scan data SIN. The second scan flip flop 10b includes first and second terminals D and SI for receiving output data Q of the first scan flip flop 10a.

However, the present invention is not limited to this. In some embodiments, the first and second terminals D and SI of the first scan flip-flop 10a receive the output data Q and the inverted output data, can do. Also, in some embodiments, the first and second terminals D, SI of the first scan flip-flop 10a may receive inverted output data. Although not shown, in some embodiments, The output data Q of the first scan flip flop 10a may be input to at least one of the first terminal D and the second terminal SI of the second scan flip flop 10b after being processed by the logic circuit have. Here, the logic network may be a combinational logic circuit.

14 is a block diagram illustrating a data processing apparatus 1000 including a scan flip flop in accordance with one embodiment of the present disclosure.

14, the data processing apparatus 1000 may include a scan flip flop group 1100 and a logic circuit 1200. The data processing apparatus 1000 may include an integrated circuit (IC), a system-on-a-chip ), A central processing unit (CPU), or a processor.

The scan flip flop group 1100 may include a plurality of scan flip flops 10, and each scan flip flop may be implemented as one of the scan flip flops illustrated in FIGS. Each scan flip-flop 10 may perform data communication with the logic circuit 1200 in accordance with the clock signal CLK. The logic circuit 1200 may be implemented as a synchronous circuit or an asynchronous circuit. The logic circuit 1200 can process the input data DIN or the scan data SIN and output the output data DOUT corresponding to the processing result.

15 is a block diagram illustrating a scan test circuit 2000 that includes a scan flip-flop in accordance with one embodiment of the present disclosure.

Referring to FIG. 15, the scan test circuit 2000 may include a sequential circuit portion 2100, a combinational circuit portion 2200, and inverters 2310 to 2340. The sequential circuit portion 2100 includes first and second scan flip-flops 2110 and 2120 and the combinational circuit portion 2200 includes first to third combinational logic circuits 2210, 2220 and 2230.

The first combinational logic circuit 2210 may operate the plurality of input data DIN to provide the data input signal D to the first scan flip flop 2210. [ The first scan flip flop 2210 synchronizes the clock signal CLK to output the data input signal D as the output data Q in a normal operation mode (for example, when the scan enable signal SE is logic low level) And provides the scan input signal SI as output data Q in a scan test mode (e.g., the scan enable signal SE is at a logic high level).

The second combinational logic circuit 2220 may operate on the output data Q of the first scan flip flop 2110 and provide it as the data input signal D of the second scan flip flop 2120. The second scan flip flop 2120 may receive the output data Q of the first scan flip flop 2110 as the scan input signal SI. Also, the second scan flip flop 2220 can operate according to the normal operation mode or the scan test operation mode based on the scan enable signal SE and the clock signal CLK.

The third combinational logic circuit 830 can calculate the output data Q of the second scan flip flop 2120 and provide it as a plurality of output data DOUT. In the scan test mode, the output data (Q) of the second scan flip flop 2120 can be provided as a scan output (SO) through the inverters 2330 and 2340.

16 is a block diagram illustrating a computing system 3000 including a scan flip flop in accordance with one embodiment of the present disclosure.

16, a computing system 3000 may include a processor 3100, a memory device 3200, a storage device 3300, a power supply 3400, and an input / output device 3500. 16, the computing system 3000 may further include ports capable of communicating with, or communicating with, video cards, sound cards, memory cards, USB devices, and the like .

As such, the processor 3100, the memory device 3200, the storage device 3300, the power supply 3400, or the input / output device 3500 included in the computing system 3000 can be implemented in the embodiment according to the technical idea of the present invention Lt; RTI ID = 0.0 > flip < / RTI > In one embodiment, at least one of the plurality of semiconductor elements included in the processor 3100, the memory device 3200, the storage device 3300, the power supply 3400, or the input / output device 3500, And a first and a second three-phase inverters sharing a first output node and facing each other, wherein the first and second three-phase inverters are connected to each other, And a scan flip flop including a flip flop that latches an internal signal in response to a signal.

Processor 3100 may perform certain calculations or tasks. According to an embodiment, the processor 3100 may be a micro-processor, a central processing unit (CPU). The processor 3100 is coupled to the memory device 3200, the storage device 3300, and the input / output device 3500 via a bus 3600, such as an address bus, a control bus, and a data bus, Lt; / RTI > In accordance with an embodiment, the processor 3100 may also be coupled to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

The memory device 3200 may store data necessary for the operation of the computing system 3000. For example, the memory device 3200 may be implemented as a DRAM, a mobile DRAM, an SRAM, a PRAM, an FRAM, an RRAM, and / or an MRAM. have. The storage device 2300 may include a solid state drive, a hard disk drive, a CD-ROM, and the like. The input / output device 3500 may include input means such as a keyboard, a keypad, a mouse, etc., and output means such as a printer, a display, and the like. The power supply 3400 may supply the operating voltage required for operation of the computing system 3000.

The integrated circuit including the scan flip flop and the scan flip flop according to the embodiments of the present invention described above can be implemented in various types of packages. For example, at least some configurations of an integrated circuit may be implemented using a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC), plastic dual in- , Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-Level Fabricated Package Package (WSP) or the like.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

10A, 10B, 20A, 20B, 30A, 30B, 40A, and 40B: scan flip-
50: scan chain
1000: Data processing device
2000: Scan test device

Claims (10)

An input unit for selecting one of a data input signal and a scan input signal according to an operation mode and providing the selected data as an internal signal; And
And a flip-flop having a cross-coupled structure including first and second tri-state inverters sharing a first output node and facing each other, the flip-flop latching the internal signal according to a clock signal. The method according to claim 1,
The flip-
A master latch including the first and second three-phase inverters; And
And a slave latch connected to the master latch. 3. The method of claim 2,
The first three-phase inverter includes a first pull-up section, a first pull-down section, a first PMOS transistor connected between the first pull-up section and the first output node, and a second PMOS transistor connected between the first output node and the first pull- And a first NMOS transistor coupled thereto,
The second three-phase inverter includes a second pull-up section, a second pull-down section, a second PMOS transistor connected between the second pull-up section and the first output node, and a second PMOS transistor connected between the first output node and the second pull- And a second NMOS transistor coupled to the scan line. The method of claim 3,
Wherein the gates of the first PMOS transistor and the second NMOS transistor are electrically connected to each other and the gates of the first NMOS transistor and the second PMOS transistor are electrically connected to each other, 1 and the second NMOS transistors form a first cross-coupled portion. The method of claim 3,
An inverted clock signal in which the clock signal is inverted is applied to the gates of the second NMOS transistor and the first PMOS transistor,
And a buffered clock signal in which the inverted clock signal is inverted is applied to the gates of the first PMOS transistor and the second NMOS transistor. 3. The method of claim 2,
Wherein the input comprises a multiplexer including third and fourth three-phase inverters sharing a second output node and facing each other,
The third three-phase inverter includes a third pull-up section and a third pull-down section controlled according to the data input signal, a third PMOS transistor connected between the third pull-up section and the second output node, And a third NMOS transistor coupled between the third pull-
The fourth four-phase inverter includes a fourth pull-up section and a fourth pull-down section controlled in accordance with the scan input signal, a fourth PMOS transistor connected between the fourth pull-up section and the second output node, And a fourth NMOS transistor connected between the fourth pull-down unit and the fourth pull-down unit. The method according to claim 6,
The gates of the third PMOS transistor and the fourth NMOS transistor are electrically connected and the gates of the fourth NMOS transistor and the third PMOS transistor are electrically connected to each other, 3 and the fourth NMOS transistors constitute a second cross-coupled portion. The method according to claim 6,
Wherein the first and fourth three-phase inverters share a power terminal and a ground terminal. 3. The method of claim 2,
The master latch
A reset switch connected between the first output node and a ground terminal, the reset switch being controlled in accordance with a reset control signal; And
Further comprising at least one of a set switch connected between a power supply terminal and the first output node and controlled according to a set control signal. Wherein at least one of the first and second scan flip-flops includes a first and a second scan flip-flops, wherein the first and second scan flip-flops share a first output node and have first and second three-phase inverters facing each other, A progressive circuit portion including a flip flop; And
Wherein the first combinational logic circuit provides a first data input signal generated by a logical operation of a plurality of data to the first scan flip flop, Wherein the second scan flip-flop provides a second data input signal generated by a logical operation of an output signal of the first scan flip-flop to the second scan flip-flop.

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