KR20150107547A - Unit pixel of image sensor, image sensor including the same and method of manufacturing image sensor - Google Patents

Abstract

A unit pixel of an image sensor includes a photoelectric conversion region, a first floating expansion region, a transfer gate, a second floating expansion region, and a dual conversion gain gate. The photoelectric conversion region is formed within a semiconductor substrate and collects photo-charges based on incidence rays. The first floating expansion region is formed within the semiconductor substrate while being separated from the photoelectric conversion region. The transfer gate is formed on the semiconductor substrate and transfers the photo-charges to the first floating expansion region based on a transfer control signal. The second floating expansion region is formed within the semiconductor substrate while being separated from the first floating expansion region. The dual conversion gain gate is formed in the vertical direction from a first side of the semiconductor substrate to be adjacent to the first and second floating expansion regions, and selectively transfers the photo-charges to the second floating expansion region based on a dual conversion gain control signal.

Description

TECHNICAL FIELD [0001] The present invention relates to a unit pixel of an image sensor, an image sensor including the unit pixel, and a manufacturing method of the image sensor. [0002]

The present invention relates to an image sensor, and more particularly, to an image sensor including a unit pixel of an image sensor, at least one unit pixel, and a method of manufacturing the image sensor.

The image sensor is a semiconductor device that converts incident light incident from the outside into an electric signal, and provides image information corresponding to the incident light. Generally, a unit pixel of an image sensor includes a photoelectric conversion region for converting the incident light into the electric signal. Among various parameters indicating the performance of the image sensor, the conversion gain represents the efficiency of converting the charges collected in the photoelectric conversion region to the output voltage. The conversion gain of the image sensor may be determined by the capacitance associated with the floating diffusion region included in the unit pixel of the image sensor.

An object of the present invention is to provide a unit pixel of an image sensor capable of effectively controlling a conversion gain.

Another object of the present invention is to provide an image sensor including the unit pixel.

Still another object of the present invention is to provide a method of manufacturing the image sensor.

To achieve the above object, a unit pixel of an image sensor according to embodiments of the present invention includes a photoelectric conversion region, a first floating diffusion region, a transfer gate, a second floating diffusion region, and a double conversion gain gate. The photoelectric conversion region is formed in the semiconductor substrate, and collects the photo charges based on the incident light. And the first floating diffusion region is formed in the semiconductor substrate away from the photoelectric conversion region. The transfer gate is formed on the semiconductor substrate between the photoelectric conversion region and the first floating diffusion region and transfers the photo charges to the first floating diffusion region based on a transfer control signal. And the second floating diffusion region is formed in the semiconductor substrate away from the photoelectric conversion region and the first floating diffusion region. Wherein the double conversion gain gate is formed vertically from a first side of the semiconductor substrate to be adjacent to the first and second floating diffusion regions, As shown in FIG.

The dual conversion gain gate may include at least one lower region and an upper region. The at least one lower region is formed inside the semiconductor substrate, and at least a part of the at least one lower region is included in the semiconductor substrate and surrounded by the semiconductor substrate. The upper region may be formed on a first side of the semiconductor substrate and connected to the at least one lower region.

The depth of the at least one lower region of the double conversion gain gate may be shallower than the depth of the first and second floating diffusion regions.

In one embodiment, the conversion gain of the unit pixel may decrease as the depth of the at least one lower region of the double conversion gain gate is deeper.

In one embodiment, the conversion gain of the unit pixel may decrease and decrease as the number of the at least one lower region of the double conversion gain gate increases.

In one embodiment, the lower surface of the at least one lower region of the double conversion gain gate is planar, and the lower edge of the at least one lower region of the double conversion gain gate may be round.

The radius of curvature of the lower edge of the at least one lower region of the dual conversion gain gate may have a value between 10 nm and 100 nm.

The unit pixel may further include a reset gate. The reset gate is formed on the semiconductor substrate and can reset the first and second floating diffusion regions based on a reset signal.

In one embodiment, the first floating diffusion region is formed in the semiconductor substrate between the transfer gate and the double conversion gain gate, and the second floating diffusion region is formed between the double conversion gain gate and the reset gate, Can be formed in the substrate.

In one embodiment, the first floating diffusion region may be formed in the semiconductor substrate between the transfer gate and the double conversion gain gate and between the transfer gate and the reset gate.

In one embodiment, the double conversion gain control signal may be selectively activated according to the illuminance of the incident light.

In one embodiment, the dual conversion gain control signal may be selectively activated based on an externally applied user setting signal.

The unit pixel may further include an output unit. The output may be coupled to the first floating diffusion region and generate a pixel signal corresponding to the incident light based on the photo charges.

The output section may include a drive transistor and a selection transistor. The drive transistor may include a first terminal coupled to a power supply voltage, a control terminal coupled to the first floating diffusion region, and a second terminal. The selection transistor may include a first terminal connected to a second terminal of the driving transistor, a control terminal applied with a selection signal, and a second terminal outputting the pixel signal.

According to another aspect of the present invention, there is provided an image sensor including a pixel array and a signal processing unit. The pixel array includes a plurality of unit pixels, and generates a plurality of pixel signals based on the incident light. The signal processing unit generates image data based on the plurality of pixel signals. Each of the plurality of unit pixels includes a photoelectric conversion region, a first floating diffusion region, a transfer gate, a second floating diffusion region, and a double conversion gain gate. The photoelectric conversion region is formed in the semiconductor substrate, and collects the photo charges based on the incident light. And the first floating diffusion region is formed in the semiconductor substrate away from the photoelectric conversion region. The transfer gate is formed on the semiconductor substrate between the photoelectric conversion region and the first floating diffusion region and transfers the photo charges to the first floating diffusion region based on a transfer control signal. And the second floating diffusion region is formed in the semiconductor substrate away from the photoelectric conversion region and the first floating diffusion region. Wherein the double conversion gain gate is formed vertically from a first side of the semiconductor substrate to be adjacent to the first and second floating diffusion regions, As shown in FIG.

In one embodiment, the signal processing unit may include an operation mode detection unit that automatically determines the operation mode of the image sensor based on the illuminance and the reference illuminance of the incident light. Wherein the signal processing unit activates the double conversion gain control signal when the illuminance of the incident light is higher than the reference illuminance and when the illuminance of the incident light is lower than or equal to the reference illuminance, Can be deactivated.

In one embodiment, the signal processing unit may receive a user setting signal for setting an operation mode of the image sensor. Wherein the signal processing unit activates the double conversion gain control signal when the user setting signal corresponds to the high contrast operation mode, and when the user setting signal corresponds to the low light operation mode, the signal processing unit performs the double conversion gain control The signal can be deactivated.

According to another aspect of the present invention, there is provided a method of manufacturing an image sensor, including: forming a photoelectric conversion region in a semiconductor substrate, a first floating diffusion region spaced apart from the photoelectric conversion region, And a second floating diffusion region spaced apart from the first floating diffusion region. A portion of the semiconductor substrate between the first floating diffusion region and the second floating diffusion region is removed to form a recess. A transfer gate is formed on the semiconductor substrate between the photoelectric conversion region and the first floating diffusion region. A dual conversion gain gate is formed vertically from the first side of the semiconductor substrate to fill the recess and adjacent the first and second floating diffusion regions.

In one embodiment, the bottom surface of the recess is flat, and the bottom edge of the recess is round.

The radius of curvature of the bottom edge of the recess may have a value between 10 nm and 100 nm.

In one embodiment, a first insulating layer may be further formed on the first surface of the semiconductor substrate.

In one embodiment, a unit pixel region may be defined by further forming an element isolation region perpendicularly from the first surface of the semiconductor substrate. The photoelectric conversion region, the first and second floating diffusion regions, the transfer gate, and the double conversion gain gate may be formed in the unit pixel region.

The element isolation region may be formed from a first surface of the semiconductor substrate to a second surface opposite to the first surface of the semiconductor substrate.

In one embodiment, a color filter may be further formed on the second surface opposite to the first surface of the semiconductor substrate. A microlens may further be formed on the color filter.

In one embodiment, a first insulating layer may be further formed between the second surface of the semiconductor substrate and the color filter.

In one embodiment, a color filter may be further formed on the first side of the semiconductor substrate. A microlens may further be formed on the color filter.

The unit pixel of the image sensor according to the above-described embodiments of the present invention may include a plurality of pixels (for example, a vertical structure) formed vertically from the first surface of the semiconductor substrate so as to be adjacent to the first and second floating diffusion regions And a double conversion gain control signal applied to the double conversion gain gate is selectively activated in accordance with an operation mode or a usage environment so that the unit pixel and the image sensor including the unit pixel The conversion gain can be effectively controlled.

1 is a cross-sectional view showing a unit pixel of an image sensor according to embodiments of the present invention.
2 and 3 are cross-sectional views showing unit pixels of an image sensor according to embodiments of the present invention.
4 is a circuit diagram showing an example of the unit pixel of FIG.
5 is a cross-sectional view showing the structure of the unit pixel of FIG.
6A and 6B are views for explaining the operation of the unit pixel of FIG.
7 is a circuit diagram showing another example of the unit pixel of FIG.
8 and 9 are sectional views showing the structure of the unit pixel of FIG.
10A and 10B are views for explaining the operation of a unit pixel according to the embodiments of the present invention.
11 is a cross-sectional view showing a unit pixel of an image sensor according to embodiments of the present invention.
12A, 12B, 12C, 12D, 12E and 12F are cross-sectional views for explaining an example of a method of manufacturing the unit pixel and the image sensor including the unit pixel of FIG.
13 is a cross-sectional view illustrating unit pixels of an image sensor according to embodiments of the present invention.
Fig. 14 is an enlarged cross-sectional view of part A of Fig.
15A, 15B, 15C, and 15D are cross-sectional views for explaining an example of a method of manufacturing a unit pixel and an image sensor including the unit pixel of FIG.
16, 17, 18, 19, 20 and 21 are sectional views showing unit pixels of an image sensor according to embodiments of the present invention.
22 is a block diagram illustrating an image sensor including unit pixels according to embodiments of the present invention.
23 is a flowchart for explaining the operation of the image sensor of FIG.
24 is a block diagram illustrating an image sensor including unit pixels according to embodiments of the present invention.
25 is a flowchart for explaining the operation of the image sensor of FIG.
26 is a block diagram illustrating a computing system including an image sensor in accordance with embodiments of the present invention.
27 is a block diagram illustrating an example of an interface used in the computing system of Fig.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

On the other hand, if an embodiment is otherwise feasible, the functions or operations specified in a particular block may occur differently from the order specified in the flowchart. For example, two consecutive blocks may actually be performed at substantially the same time, and depending on the associated function or operation, the blocks may be performed backwards.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

An image sensor is a semiconductor device that converts light incident from the outside (hereinafter, incident light) into an electric signal, and can be classified into a charge coupled device (CCD) image sensor, a complementary metal oxide semiconductor (CMOS) image sensor, and the like. Embodiments of the present invention will be described below with reference to a CMOS image sensor, but the embodiments of the present invention can be equally applied to any image sensor such as a CCD image sensor.

1 is a cross-sectional view showing a unit pixel of an image sensor according to embodiments of the present invention.

1, a unit pixel 100 of an image sensor includes a photoelectric conversion region PD formed in a semiconductor substrate 101, a first floating diffusion region FD1, a transfer gate TG, (FD2) and a dual conversion gain gate (DG). The unit pixel 100 may further include an output unit 170.

The semiconductor substrate 101 may include a first surface 101a and a second surface 101b opposite to the first surface 101a. For example, the semiconductor substrate 101 may comprise a semiconductor layer formed through an epitaxial process.

The photoelectric conversion region PD is formed in the semiconductor substrate 101 and collects the photo charges generated based on the incident light. For example, electron-hole pairs corresponding to the incident light are generated, and the photoelectric conversion region PD can collect such electrons or holes.

1, the photoelectric conversion region PD is shown as a photo diode, but the photoelectric conversion region PD may be a photodiode, a photo transistor, a photo gate, A pinned photo diode (PPD), or a combination thereof.

The first floating diffusion region FD1 is formed in the semiconductor substrate 101 away from the photoelectric conversion region PD. A transfer gate TG is formed on the semiconductor substrate 101 between the photoelectric conversion region PD and the first floating diffusion region FD1.

The photo charges collected in the photoelectric conversion region PD are transferred to the first floating diffusion region FD1 based on the transfer control signal TX applied to the transfer gate TG. In other words, the transfer gate TG has a structure for transferring the photo-charges from the photoelectric conversion region PD to the first floating diffusion region FD1. Specifically, the photoelectric conversion region PD and the first floating diffusion region FD1 can be electrically connected in response to the transmission control signal TX. Such an electrical connection may be a channel formed in the semiconductor substrate 101 between the two regions PD and FD1. According to an embodiment, the channel may be a surface channel or a buried channel.

The second floating diffusion region FD2 is formed in the semiconductor substrate 101 away from the photoelectric conversion region PD and the first floating diffusion region FD1. The dual conversion gain gate DG is formed vertically from the first surface 101a of the semiconductor substrate 101 so as to be adjacent to the first and second floating diffusion regions FD1 and FD2. In other words, the double conversion gain gate DG may have a vertical gate structure formed between the first floating diffusion region FD1 and the second floating diffusion region FD2.

The photo-charges are selectively transferred to the second floating diffusion region FD2 based on the double conversion gain control signal DX applied to the double conversion gain gate DG. In other words, the double conversion gain gate DG has a structure for transferring the photo-charges from the photoelectric conversion region PD to the second floating diffusion region FD2 via the first floating diffusion region FD1. Specifically, as described above, the photoelectric conversion region PD and the first floating diffusion region FD1 are electrically connected in response to the transmission control signal TX, and in response to the double conversion gain control signal DX, The floating diffusion region FD1 and the second floating diffusion region FD2 may be electrically connected. Such an electrical connection may be a channel formed in the semiconductor substrate 101 between the two regions FD1 and FD2.

The output unit 170 is connected to the first floating diffusion region FD1 and can generate a pixel signal VPIX corresponding to the incident light based on the photo charges. As described above, the first floating diffusion region FD1 receives the photo charges through the transfer gate TG and the second floating diffusion region FD2 receives the transfer gate TG and the double conversion gain gate DG Lt; / RTI > The output section 170 corresponds to the image data based on the amount of charges of the photo charges transferred to the first floating diffusion region FD1 or the amount of charges of the photo charges transferred to the first and second floating diffusion regions FD1 and FD2 The pixel signal VPIX can be generated.

Although not shown, the unit pixel 100 includes an insulating capping layer (not shown) covering an upper surface of the gate structures TG and DG and / or an insulating spacer (not shown) covering the sidewalls of the gate structures TG and DG ).

Depending on the embodiment, the double conversion gain control signal DX may be selectively activated based on the illuminance of the incident light or based on a user-set signal applied externally. When the unit pixel is operated in the read mode, only the first floating diffusion region FD1 is used as the storage region of the photo charges when the double conversion gain control signal DX is inactivated, The first and second floating diffusion regions FD1 and FD2 may all be used as the storage regions of the light charges. The capacitance for the storage region (for example, the floating diffusion region) of the photo charges in the read mode is adjusted according to whether or not the double conversion gain control signal DX is activated, so that the photo- The conversion gain indicating the efficiency of conversion into the signal VPIX can be effectively adjusted. The operation of the unit pixel according to whether the dual conversion gain control signal DX is activated will be described later in more detail with reference to FIGS. 6A, 6B, 10A, and 10B.

In one embodiment, the dual conversion gain gate DG can be divided into at least one bottom portion (BP) and a top portion (TP) as shown by the dashed line in FIG. At least one lower region (BP) may be a portion formed inside the semiconductor substrate 101 and surrounded by the semiconductor substrate 101. In other words, at least a part of at least one lower region BP may be included in the semiconductor substrate 101. [ The upper region TP may be a portion formed on the first surface 101a of the semiconductor substrate 101 and connected to at least one lower region BP. At least one lower region BP and upper region TP may be formed substantially simultaneously using the same process (e.g., a deposition and / or patterning process). The structure of the at least one lower region BP can be variously changed according to the embodiment, which will be described later in detail with reference to FIGS. 2 and 3. FIG.

In one embodiment, the depth of at least one lower region BP of the dual conversion gain gate DG may be shallower than the depth of the first and second floating diffusion regions FD1, FD2. Specifically, a depth D1, which indicates the distance from the first surface 101a of the semiconductor substrate 101 to the end surface of at least one lower region BP, is greater than the depth D1 of the first surface 101a of the semiconductor substrate 101 (D2) indicating the distance from the first floating diffusion regions (101a) to the longitudinal sides of the first and second floating diffusion regions (FD1, FD2). In this case, in the region between the lower end of at least one lower region BP and the first and second floating diffusion regions FD1 and FD2 in the semiconductor substrate 101 in response to the double conversion gain control signal DX, A channel can be formed.

The unit pixel 100 of the image sensor according to the embodiments of the present invention is formed so as to extend vertically from the first surface 101a of the semiconductor substrate 101 so as to be adjacent to the first and second floating diffusion regions FD1 and FD2 And a dual conversion gain gate (DG) formed. The double conversion gain gate (DG) has a vertical gate structure, thereby increasing the surface area at which the double conversion gain gate (DG) and the semiconductor substrate (101) are in contact. Therefore, when the double conversion gain control signal DX is activated when compared with the case where the double conversion gain gate has a planar gate structure, the storage region of the photo charges in the reading mode (for example, The floating diffusion region of the pixel 100) can be increased more. As a result, the conversion gain of the unit pixel 100 can be effectively adjusted based on the double conversion gain control signal DX without loss of area of the photoelectric conversion region PD (i.e., without decreasing the fill factor) have.

2 and 3 are cross-sectional views showing unit pixels of an image sensor according to embodiments of the present invention.

2, the unit pixel 100a of the image sensor includes a photoelectric conversion region PD formed in the semiconductor substrate 101, a first floating diffusion region FD1, a transfer gate TG, (FD2) and a dual conversion gain gate (DG '), and may further include an output section (170).

The photoelectric conversion region PD, first and second floating diffusion regions FD1 and FD2, transfer gate TG and output portion 170 of FIG. 2 correspond to the photoelectric conversion regions PD, The second floating diffusion regions FD1 and FD2, the transfer gate TG, and the output portion 170, respectively.

The dual conversion gain gate DG 'is formed vertically from the first surface 101a of the semiconductor substrate 101 so as to be adjacent to the first and second floating diffusion regions FD1 and FD2. The dual conversion gain gate DG 'is divided into at least one lower region BP' and an upper region TP, and at least one lower region BP 'may be formed relatively deeply. In other words, the depth of at least one lower region BP 'of the double conversion gain gate DG' of FIG. 2 is greater than the depth of at least one lower region BP of the double conversion gain gate DG of FIG. .

In one embodiment, as the depth of at least one lower region of the double conversion gain gate is deeper, the conversion gain of a unit pixel according to embodiments of the present invention may be reduced. For example, the depth D1 ', which represents the distance from the first surface 101a of the semiconductor substrate 101 to the longitudinal side of at least one lower region BP' of FIG. 2, May be deeper than the depth D1 that represents the distance from the surface 101a to the longitudinal section of at least one lower region BP of Fig. In this case, the surface area at which the double conversion gain gate DG 'in FIG. 2 contacts the semiconductor substrate 101 is wider than the surface area at which the double conversion gain gate DG in FIG. 1 contacts the semiconductor substrate 101, When the double conversion gain control signal DX is activated, the capacitance for the floating diffusion region of the unit pixel 100a of FIG. 2 may increase more than the capacitance for the floating diffusion region of the unit pixel 100 of FIG. have. 6A and 6B, since the conversion gain of the unit pixel is inversely proportional to the capacitance of the unit pixel with respect to the floating diffusion region, when the double conversion gain control signal DX is activated, The conversion gain of the unit pixel 100a may be smaller than the conversion gain of the unit pixel 100 of FIG.

As described above with reference to FIGS. 1 and 2, the depth of the vertical dual conversion gain gate DG 'included in the unit pixel according to the embodiments of the present invention is smaller than the depth of the first and second floating diffusion regions FD1 and FD2 In the range of depth that is less than the depth of the trench. In one embodiment, the depth of at least one lower region BP 'of the double conversion gain gate DG' may be less than half the depth of the first and second floating diffusion regions FD1, FD2 have. In other words, the depth D1 'may be greater than zero and less than half of the depth D2, i.e., D2 / 2. In another embodiment, the depth of at least one lower region BP 'of the double conversion gain gate DG' is greater than or equal to half the depth of the first and second floating diffusion regions FD1 and FD2 May be shallower than the depth of the first and second floating diffusion regions FD1 and FD2. In other words, the depth D1 'may be greater than or equal to half of the depth D2, i.e., D2 / 2, and less than the depth D2. Depending on the embodiment, the depth of the first floating diffusion region FD1 and the depth of the second floating diffusion region FD2 may be different, in which case at least one lower region of the double conversion gain gate DG ' BP 'may be shallower than the shallow depth of the first and second floating diffusion regions FD1 and FD2.

Although not shown, the depth of at least one lower region of the double conversion gain gate may be implemented to be deeper than or equal to the depth of the first and second floating diffusion regions FD1, FD2.

3, the unit pixel 100b of the image sensor includes a photoelectric conversion region PD formed in the semiconductor substrate 101, a first floating diffusion region FD1, a transfer gate TG, (FD2) and a dual conversion gain gate (DG "), and may further include an output section (170).

The photoelectric conversion region PD, the first and second floating diffusion regions FD1 and FD2, the transfer gate TG and the output portion 170 of FIG. 3 correspond to the photoelectric conversion regions PD, The second floating diffusion regions FD1 and FD2, the transfer gate TG, and the output portion 170, respectively.

The double conversion gain gate DG is formed vertically from the first surface 101a of the semiconductor substrate 101 so as to be adjacent to the first and second floating diffusion regions FD1 and FD2. "May be divided into a plurality of lower regions BP1, BP2 and an upper region TP.

In one embodiment, the conversion gain of a unit pixel according to embodiments of the present invention may decrease as the number of lower regions of the double conversion gain gate increases. For example, the double conversion gain gate DG "of FIG. 3 includes two lower regions BP1 and BP2, and the dual conversion gain gate DG of FIG. 1 includes one lower region BP The surface area at which the dual conversion gain gate DG "in FIG. 3 contacts the semiconductor substrate 101 is larger than the surface area at which the double conversion gain gate DG in FIG. 1 contacts the semiconductor substrate 101. [ When the double conversion gain control signal DX is activated, the capacitance of the unit pixel 100b of FIG. 3 with respect to the floating diffusion region is larger than the capacitance of the unit pixel 100 of the unit pixel 100 with respect to the floating diffusion region It can increase a lot. 6A and 6B, since the conversion gain of the unit pixel is inversely proportional to the capacitance of the unit pixel with respect to the floating diffusion region, when the double conversion gain control signal DX is activated, The conversion gain of the unit pixel 100b may be smaller than the conversion gain of the unit pixel 100 of FIG.

As described above with reference to Figs. 1 and 3, the number of the lower regions of the vertical double conversion gain gate DG "included in the unit pixel according to the embodiments of the present invention can be variously changed. Thus, the double conversion gain gate DG "may be implemented to include three or more sub regions. According to the embodiment, the depth of the lower region BP1 and the depth of the lower region BP2 may be different. Also, the depths of the lower regions BP1 and BP2 may be shallower than the depths of the first and second floating diffusion regions FD1 and FD2. Although not shown, the depths of the lower regions BP1 and BP2 may be deeper than or equal to the depths of the first and second floating diffusion regions FD1 and FD2.

In the unit pixel 100 of the image sensor according to the embodiments of the present invention, impurities contained in the semiconductor substrate 101 are transferred to the photoelectric conversion region PD and the first and second floating diffusion regions FD1 and FD2 It can have a different conductivity type from the contained impurity. For example, the semiconductor substrate 101 may be a semiconductor substrate doped with p-type impurities. A photoelectric conversion region PD and first and second floating diffusion regions FD1 and FD2 doped with n-type impurities may be provided through an ion implantation process. In this case, the photoelectric conversion region PD can collect electrons from the electron-hole pairs.

Although not shown, the unit pixel 100 of the image sensor according to embodiments of the present invention may further include an insulating layer (not shown) formed between the semiconductor substrate 101 and the gate structures TG and DG have. In this case, the transfer gate TG and the double conversion gain gate DG may be formed by laminating a gate conductive film on the insulating layer, and then patterning the stacked gate conductive film. The gate conductive film may be formed using polysilicon, a metal, and / or a metal compound. Depending on the embodiment, the transfer gate TG and the dual conversion gain gate DG may be formed simultaneously (i. E., Using the same process) and sequentially (i. Depending on the embodiment, the dual conversion gain gate (DG) may have a pillar shape or a cup shape. Depending on the embodiment, the transfer gate TG may also have a vertical gate structure.

The unit pixel 100 of the image sensor according to embodiments of the present invention may be included in a frontside illuminated image sensor (FIS) or a backside illuminated image sensor (BIS) . Specifically, the first surface 101a of the semiconductor substrate 101 on which the gate structures TG and DG are formed is the front surface of the semiconductor substrate 101 and the second surface 101b opposite to the first surface 101a May be the rear surface of the semiconductor substrate 101. [ For example, when the pixel signal VPIX is generated based on the incident light incident through the front surface of the semiconductor substrate 101 as shown in FIG. 1, the unit pixel may be included in the FIS. In another example, the unit pixel may be included in the BIS when generating the pixel signal VPIX based on the incident light incident through the rear surface of the semiconductor substrate 101, though not shown.

Although not shown, the unit pixel 100 of the image sensor according to the embodiments of the present invention further includes a color filter (not shown) and a microlens (not shown) for providing incident light to the photoelectric conversion region PD . When the unit pixel is included in the FIS, the color filter and the microlens are formed on the front surface of the semiconductor substrate 101, and when the unit pixel is included in the BIS, May be formed on the rear surface of the semiconductor substrate 101. The unit pixel 100 of the image sensor according to the embodiments of the present invention includes an element isolation region (not shown) formed vertically from the first surface 101a of the semiconductor substrate 101 so as to surround the unit pixel 100 (For example, a shallow trench isolation (STI) region or a deep trench isolation (DTI) region).

Meanwhile, the unit pixel 100 of the image sensor according to embodiments of the present invention may have a 5-transistor structure including a reset transistor, a transfer transistor, a floating diffusion node, and a dual conversion gain transistor, Adjacent unit pixels may have a structure in which some transistors are shared. The circuit structure of the unit pixel and the specific embodiment therefor will be described later in detail with reference to FIGS. 4 and 7. FIG.

4 is a circuit diagram showing an example of the unit pixel of FIG.

Referring to FIG. 4, the unit pixel 200 of the image sensor may include a photoelectric conversion unit 210 and a signal generation circuit 212.

The photoelectric conversion unit 210 can perform photoelectric conversion based on the incident light. The signal generating circuit 212 can generate the pixel signal VPIX based on the photo charges generated by the photoelectric conversion. The signal generating circuit 212 includes a transfer transistor 220, a first floating diffusion node 230, a dual conversion gain transistor 240, a second floating diffusion node 250, a reset transistor 260, . ≪ / RTI >

The transfer transistor 220 may include a first terminal coupled to the photoelectric conversion unit 210, a second terminal coupled to the first floating diffusion node 230, and a gate to which the transfer control signal TX is applied. The dual conversion gain transistor 240 includes a first terminal coupled to the first floating diffusion node 230, a second terminal coupled to the second floating diffusion node 250 and a gate to which the dual conversion gain control signal DX is applied can do. The reset transistor 260 may include a first terminal to which the power supply voltage VDD is applied, a second terminal coupled to the second floating diffusion node 250, and a gate to which the reset signal RST is applied. The output 270 is coupled to the first floating diffusion node 230 and generates a pixel signal VPIX based on the photo charges and includes a drive transistor 280 (e.g., a source follower) Transistors) and a selection transistor 290. The drive transistor 280 may include a first terminal to which a power supply voltage VDD is applied, a gate connected to the first floating diffusion node 230, and a second terminal. The selection transistor 290 may include a first terminal connected to the second terminal of the drive transistor 280, a gate to which the selection signal SEL is applied, and a second terminal for outputting the pixel signal VPIX.

5 is a cross-sectional view showing the structure of the unit pixel of FIG.

4 and 5, the unit pixel 200 of the image sensor includes a photoelectric conversion region PD formed in the semiconductor substrate 201, a first floating diffusion region FD1, a transfer gate TG, A reset diffusion region FD2, a double conversion gain gate DG, a reset drain region RD, a reset gate RG and an output portion 270. [

The second photoelectric conversion region PD, the transfer gate TG, the first floating diffusion region FD1, the double conversion gain gate DG, the second floating diffusion region FD2, the reset gate RG, The first floating diffusion node 230, the second conversion gain transistor 240, the second floating diffusion node 250, the reset transistor (not shown) 260 and the output unit 270 of FIG. The photoelectric conversion region PD, the first and second floating diffusion regions FD1 and FD2, the transfer gate TG, the double conversion gain gate DG and the output portion 270 of FIG. 5 correspond to the photoelectric conversion The first and second floating diffusion regions FD1 and FD2, the transfer gate TG, the double conversion gain gate DG, and the output unit 170, respectively.

The reset drain region RD may be formed in the semiconductor substrate 201 away from the photoelectric conversion region PD and the first and second floating diffusion regions FD1 and FD2. The power supply voltage VDD can be applied to the reset drain region RD.

A reset gate RG is formed on the semiconductor substrate 201 between the second floating diffusion region FD2 and the reset drain region RD. The first and second floating diffusion regions FD1 and FD2 can be reset based on the reset signal RST applied to the reset gate RG. For example, by discharging the charges accumulated in the first and second floating diffusion regions FD1, FD2 in response to the reset signal RST, the first and second floating diffusion regions FD1, It can be initialized to the level of the voltage VDD.

4 and 5, a first floating diffusion node 230, a dual conversion gain transistor 240 and a second floating diffusion node 250 are formed between the transfer transistor 220 and the reset transistor 260 . In other words, in the unit pixel 200, the first floating diffusion region FD1 is formed in the semiconductor substrate 201 between the transfer gate TG and the double conversion gain gate DG, and the second floating diffusion region FD2 May be formed in the semiconductor substrate 201 between the double conversion gain gate DG and the reset gate RG.

6A and 6B are views for explaining the operation of the unit pixel of FIG. 6A is a cross-sectional view for explaining a conversion gain of the unit pixel 200 of FIG. 5 when the double conversion gain control signal DX is inactivated. FIG. 6A is a diagram illustrating a case where the double conversion gain control signal DX is activated 5 is a cross-sectional view for explaining the conversion gain of the unit pixel 200 of FIG. For convenience of description, the illustration of the selection transistor (290 in Fig. 5) included in the output portion (270 in Fig. 5) in Figs. 6A and 6B is omitted.

In the unit pixel of the image sensor according to the embodiments of the present invention, the double conversion gain control signal DX can be selectively activated based on the illuminance of the incident light or based on the externally applied user setting signal. A configuration in which the activation of the dual conversion gain control signal DX is automatically determined according to the illuminance of the incident light and a configuration in which the activation of the double conversion gain control signal DX is manually determined based on the user setting signal Will be described later in more detail with reference to FIGS. 22, 23, 24, and 25.

6A, for example, when the illuminance of the incident light is lower than or equal to the reference illuminance, or when the image sensor is set to operate in the low-illuminance operation mode based on the user setting signal, the double conversion gain control signal DX) may be deactivated. In this case, only the first floating diffusion region FD1 can be used as the storage region of the photo charges when the unit pixel 200 operates in the read mode after the light integration mode. In the example of FIG. 6A, the capacitance CFD for the first floating diffusion region FD1, which is the storage region of the photo charges in the read mode, is obtained as shown in Equation 1 below, The first conversion gain CG1 of the output signal of the second comparator 22 can be obtained as shown in the following equation (2).

[Equation 1]

&Quot; (2) "

Cj denotes a capacitance existing between the first floating diffusion region FD1 and the semiconductor substrate 201 and CT denotes a capacitance between the transfer gate TG and the first floating diffusion region FD1. CDG1 represents a capacitance existing between the upper region TP of the double conversion gain gate DG and the first floating diffusion region FD1 and CDG2 represents the capacitance existing between the lower portion of the double conversion gain gate DG CD represents the capacitance existing between the first terminal of the drive transistor 280 and the gate and CS represents the capacitance existing between the first transistor and the first floating diffusion region FD1. And the capacitance existing between the gate and the second terminal. Gsf represents the gain of the drive transistor 280 and is a ratio of the output signal to the input signal of the drive transistor 280 (that is, the voltage of the first floating diffusion region FD1) (that is, the pixel signal VPIX) Can be corresponding. In Equation (2) above, Q may correspond to the amount of charge of the photo charges collected in the photoelectric conversion region PD in the photo integration mode and transferred to the first floating diffusion region FD1 in the readout mode.

6B, for example, when the illuminance of the incident light is higher than the reference illuminance or when the image sensor is set to operate in the high contrast operation mode based on the user setting signal, the double conversion gain control signal DX) can be activated. In this case, when the unit pixel 200 operates in the read mode after the light integration mode, the first and second floating diffusion regions FD1 and FD2 can be used as the storage regions of the light charges. In the example of FIG. 6B, the capacitance CFD 'for the first and second floating diffusion regions FD1 and FD2, which are the storage regions of the photo charges in the read mode, is obtained as Equation (3) , And the second conversion gain CG2 of the unit pixel 200 can be obtained as shown in Equation (4) below.

&Quot; (3) "

&Quot; (4) "

CDG3 represents the capacitance existing between the upper region TP of the double conversion gain gate DG and the second floating diffusion region FD2 and CDG4 represents the capacitance existing between the double conversion gain gate DG and the second floating diffusion region FD2, And CR represents the capacitance existing between the second floating diffusion region FD2 and the reset gate RG. In the figure, the capacitance between the lower floating diffusion region FD2 and the second floating diffusion region FD2 is shown. In the above formula (2), Q 'is the charge amount of the photo charges collected in the photoelectric conversion region PD in the light integration mode and transferred to the first and second floating diffusion regions FD1 and FD2 in the readout mode Can be corresponding.

The unit pixel of the image sensor according to embodiments of the present invention further includes a double conversion gain gate DG and selectively activates the double conversion gain control signal DX applied to the double conversion gain gate DG, The conversion gain of the unit pixel can be effectively controlled according to the operation mode or the use environment of the image sensor. In addition, when the double conversion gain control signal DX is activated by forming the double conversion gain gate DG into a vertical gate structure so that the surface area in which the double conversion gain gate DG and the semiconductor substrate 201 contact each other increases, The capacitance for the floating diffusion region of the unit pixel can be increased relatively (e.g., by CDG2 and CDG4 in Fig. 6B), and thus the conversion gain of the unit pixel can be effectively adjusted.

7 is a circuit diagram showing another example of the unit pixel of FIG.

Referring to FIG. 7, the unit pixel 300 of the image sensor may include a photoelectric conversion unit 310 and a signal generation circuit 312.

The photoelectric conversion unit 310 can perform photoelectric conversion based on the incident light. The signal generating circuit 312 can generate the pixel signal VPIX based on the photo charges generated by the photoelectric conversion. The signal generating circuit 312 includes a transfer transistor 320, a first floating diffusion node 330, a dual conversion gain transistor 340, a second floating diffusion node 350, a reset transistor 360 and an output 370, . ≪ / RTI >

The transfer transistor 320 may include a first terminal coupled to the photoelectric conversion unit 310, a second terminal coupled to the first floating diffusion node 330, and a gate to which the transfer control signal TX is applied. The dual conversion gain transistor 340 includes a first terminal coupled to the first floating diffusion node 330, a second terminal coupled to the second floating diffusion node 350 and a gate to which the dual conversion gain control signal DX is applied can do. The reset transistor 360 may include a first terminal to which the power supply voltage VDD is applied, a second terminal coupled to the first floating diffusion node 330, and a gate to which the reset signal RST is applied. The output 370 is coupled to the first floating diffusion node 330 and generates a pixel signal VPIX based on the photo charges and may include a drive transistor 380 and a selection transistor 390 . The drive transistor 380 may include a first terminal to which a power supply voltage VDD is applied, a gate connected to the first floating diffusion node 330, and a second terminal. The selection transistor 390 may include a first terminal connected to the second terminal of the drive transistor 380, a gate to which the selection signal SEL is applied, and a second terminal for outputting the pixel signal VPIX.

8 and 9 are sectional views showing the structure of the unit pixel of FIG.

7, 8 and 9, the unit pixel 300 of the image sensor includes a photoelectric conversion region PD formed in the semiconductor substrate 301, a first floating diffusion region FD1, a transfer gate TG, 2 floating diffusion region FD2, a double conversion gain gate DG, a reset drain region RD, a reset gate RG and an output portion 370. [

The transfer gate TG, the first floating diffusion region FD1, the double conversion gain gate DG, the second floating diffusion region FD2, the reset gate RG, and the second floating diffusion region FD shown in Figs. 8 and 9, The output unit 370 includes the photoelectric conversion unit 310, the transfer transistor 320, the first floating diffusion node 330, the double conversion gain transistor 340, the second floating diffusion node 350, The transistor 360 and the output portion 370 of FIG. The photoelectric conversion region PD, the first and second floating diffusion regions FD1 and FD2, the transfer gate TG, the double conversion gain gate DG and the output portion 370 of FIGS. The first and second floating diffusion regions FD1 and FD2, the transfer gate TG, the double conversion gain gate DG, and the output portion 170, respectively.

The reset drain region RD may be formed in the semiconductor substrate 301 away from the photoelectric conversion region PD and the first and second floating diffusion regions FD1 and FD2. The power supply voltage VDD can be applied to the reset drain region RD. A reset gate RG is formed on the semiconductor substrate 301 between the first floating diffusion region FD1 and the reset drain region RD. The first and second floating diffusion regions FD1 and FD2 can be reset based on the reset signal RST applied to the reset gate RG.

The first floating diffusion node 330 is formed between the transfer transistor 320 and the reset transistor 360 and also between the transfer transistor 320 and the dual conversion gain transistor 340. In the embodiment of Figures 7, As shown in FIG. In other words, in the unit pixel 300, the first floating diffusion region FD1 is formed in the semiconductor substrate 301 between the transfer gate TG and the double conversion gain gate DG, and also the transfer gate TG And may be formed in the semiconductor substrate 301 between the reset gates RG.

The unit pixel 300 of Figures 7, 8, and 9 may operate substantially the same as the unit pixel 200 of Figures 4 and 5. Thus, as described above with reference to Figs. 6A and 6B, the conversion gain of the unit pixel can be effectively adjusted by selectively activating the double conversion gain control signal DX applied to the double conversion gain gate DG. In addition, the conversion gain of the unit pixel can be effectively controlled by forming the double conversion gain gate (DG) into the vertical gate structure so that the surface area in which the double conversion gain gate (DG) and the semiconductor substrate 301 contact each other increases.

10A and 10B are views for explaining the operation of a unit pixel according to the embodiments of the present invention. 10A is a timing chart showing the operation of the unit pixel when the illuminance of the incident light is lower than or equal to the reference illuminance or when the illuminance is set to be driven in the low-illuminance operation mode based on the user setting signal. 10B is a timing chart showing the operation of the unit pixel when the illuminance of the incident light is higher than the reference illuminance or when the illuminance is set to be driven in the high contrast operation mode based on the user setting signal.

Referring to FIG. 10A, the light integration mode (TINT) starts at time t1. The reset signal RST is activated at time t1 and the transfer control signal TX is activated in the interval of time t1 to t2 to reset the photoelectric conversion region PD and the first floating diffusion region FD1. The reset signal RST remains active in the light integration mode (TINT).

Photoelectric conversion is performed based on the incident light in the light integration mode (TINT) after time t2. When the image sensor including the unit pixel is a CMOS image sensor, the shutter of the CMOS image sensor is opened during the light integration mode (TINT) so that the charge carrier such as electron-hole pairs is generated and collected by the incident light, Is collected.

At time t3, the light integration mode (TINT) is ended and the read mode (TRD) is started. At time t3, the selection signal SEL is activated to select a unit pixel for outputting the pixel signal. The reset signal RST that has been kept in the activated state is inactivated at time t4. In the interval TA after the time t4, the reset signal of the pixel signal VPIX corresponding to the voltage of the first floating diffusion region FD1 whose sampling signal SMPL is activated and reset is sampled.

In the interval TB after the interval TA, the transmission control signal TX is activated to transfer the photo charges from the photoelectric conversion region PD to the first floating diffusion region FD1. In the interval TC after the section TB, the sampling signal SMPL is activated and the image component of the pixel signal VPIX corresponding to the voltage of the first floating diffusion area FD1 is sampled. The effective image component of the pixel signal VPIX can be generated based on the reset component of the pixel signal VPIX and the image component of the pixel signal VPIX.

In the section TD after the section TC, the reset signal RST is activated and the first floating diffusion region FD1 is reset. At time t5 after the period TD, the selection signal SEL is inactivated and the read mode TRD is ended.

In the embodiment of FIG. 10A, the dual conversion gain control signal DX remains inactive during the light integration mode (TINT) and the read mode (TRD). In other words, during the read mode TRD, only the first floating diffusion region FD1 is used as the storage region of the photo charges and the second floating diffusion region FD2 is not used. Thus, a unit pixel can have a relatively large conversion gain. However, when the second floating diffusion region FD2 and the double conversion gain gate DG are disposed between the reset gate RG and the first floating diffusion region FD1 as shown in FIGS. 4 and 5, The double conversion gain control signal DX may be activated during the same period (for example, from time t1 to t4 and period TD) as the period during which the reset signal RST is activated to reset the floating diffusion region FD1.

Referring to FIG. 10B, the light integration mode (TINT) starts at time t6. The reset signal RST and the double conversion gain control signal DX are activated at the time t6 and the transmission control signal TX is activated in the interval of the time t6 to t7 to make the photoelectric conversion region PD and the first and second floating diffusion The regions FD1 and FD2 are reset. The reset signal RST and the double conversion gain control signal DX remain active in the light integration mode TINT. Photoelectric conversion is performed based on the incident light in the light integration mode (TINT) after time t7.

At time t8, the light integration mode (TINT) is ended and the read mode (TRD) is started. At time t8, the selection signal SEL is activated to select a unit pixel to output the pixel signal. The reset signal RST that has been kept in the activated state is inactivated at time t9. The dual conversion gain control signal DX remains active even in the read mode TRD. In the interval TE after time t9, the reset component of the pixel signal VPIX corresponding to the voltage of the first and second floating diffusion regions FD1 and FD2 whose sampling signal SMPL is activated and reset is sampled.

In the interval TF after the interval TE, the transmission control signal TX is activated to transfer the photo charges to the first and second floating diffusion regions FD1 and FD2 in the photoelectric conversion region PD. In the section TH after the section TF, the sampling signal SMPL is activated and the image component of the pixel signal VPIX corresponding to the voltages of the first and second floating diffusion regions FD1 and FD2 is sampled.

In the section TI after the section TH, the reset signal RST is activated to reset the first and second floating diffusion regions FD1 and FD2. At time t10 after the interval TI, the selection signal SEL and the double conversion gain control signal DX are inactivated and the read mode TRD is ended.

In the embodiment of FIG. 10B, the dual conversion gain control signal DX remains active during the light integration mode (TINT) and the read mode (TRD). In other words, during the read mode TRD, both the first and second floating diffusion regions FD1 and FD2 are used as the storage regions of the light charges. Thus, a unit pixel can have a relatively small conversion gain.

10A and 10B, the reset signal RST is activated when the light integration mode (TINT) is started and maintained in the light integration mode (TINT), but the reset signal RST (For example, a period from time t1 to t2 in FIG. 10A or a period from time t6 to t7 in FIG. 10B) and an initial operation period (for example, from time t6 to t7 in FIG. 10B) of the light integration mode For example, a period from time t3 to t4 in Fig. 10A or a period from time t8 to t9 in Fig. 10B).

Hereinafter, various embodiments of unit pixels and a method of manufacturing unit pixels and an image sensor including the unit pixels will be described in detail with reference to FIGS. 11 to 21. FIG.

11 is a cross-sectional view showing a unit pixel of an image sensor according to embodiments of the present invention.

11, the unit pixel 400 of the image sensor includes a photoelectric conversion region PD formed in the semiconductor substrate 401, a first floating diffusion region FD1, a transfer gate TG, (FD2) and a dual conversion gain gate (DG). The unit pixel 400 may further include an isolation region 410, a first insulation layer 420, a second insulation layer 430, a color filter CF, and a microlens ML. For example, the unit pixel 400 of FIG. 11 may be included in the BIS.

The semiconductor substrate 401 may include a first surface 401a and a second surface 401b opposite to the first surface 401a. For example, the first surface 401a of the semiconductor substrate 401 may be the front surface of the semiconductor substrate 401, and the second surface 401b of the semiconductor substrate 401 may be the rear surface of the semiconductor substrate 401.

The photoelectric conversion region PD, the first and second floating diffusion regions FD1 and FD2, the transfer gate TG and the double conversion gain gate DG in Fig. 11 correspond to the photoelectric conversion region PD in Fig. 1, 1 and the second floating diffusion regions FD1 and FD2, the transfer gate TG, and the double conversion gain gate DG, respectively.

The element isolation region 410 may be formed vertically from the first surface 401a of the semiconductor substrate 401. [ The unit pixel region can be defined based on the element isolation region 410, as described below with reference to FIG. 12A. The photoelectric conversion region PD, the first and second floating diffusion regions FD1 and FD2, the transmission gate TG and the double conversion gain gate DG may be formed in the unit pixel region. The element isolation region 410 may include an insulating material.

The unit pixel 400 may further include a polysilicon region (not shown) formed in the element isolation region 410 or may include a surface doping film (not shown) formed on the surface of the element isolation region 410 Time). The polysilicon region is surrounded by an element isolation region 410 and may include polysilicon, a metal, and / or a metal compound. A dark current is reduced by forming an impurity region (for example, a p-type region) so as to surround the surface of the element isolation region 410 by using an ion implantation process such as plasma doping (PLAD) doping The surface doping film may be provided. For example, the surface doping layer may be formed by doping impurities of the same type as the impurities contained in the semiconductor substrate 401 at a higher concentration than that of the semiconductor substrate 401, or impurities contained in the photoelectric conversion region PD, Can be doped with a higher concentration than the photoelectric conversion region PD.

The first insulating layer 420 may be formed on the first surface 401 a of the semiconductor substrate 401. For example, the first insulating layer 420 may electrically isolate the gate structures TG and DG from the semiconductor substrate 401, and may be referred to as a gate insulating layer.

The second insulating layer 430 may be formed on the first surface 401a of the semiconductor substrate 401, for example, on the transfer gate TG and the double conversion gain gate DG. The second insulating layer 430 may include a plurality of metal wirings WL. The plurality of metal wirings WL may be electrically connected to the gate structures TG and DG through contacts or plugs, or may be electrically connected to each other. For example, the plurality of metal wirings WL may be formed by a method of stacking and patterning a conductive material including a metal such as copper, tungsten, titanium, aluminum, or the like. Although not shown, the second insulating layer 430 may have a multi-layer structure in which a plurality of insulating layers are stacked.

Depending on the embodiment, the second insulating layer 430 may further include additional gate structures (not shown), and depending on the connection and arrangement of the additional gate structures and the plurality of metal wirings WL, The signal generating circuit 212 of FIG. 7 and the signal generating circuit 312 of FIG. 7 can be implemented.

The color filter CF may be formed on the second surface 401b of the semiconductor substrate 401. [ The color filters CF may be included in a color filter array arranged in a matrix form. In one embodiment, the color filter array may have a Bayer pattern including a red filter, a green filter, and a blue filter. In another embodiment, the color filter array may include a yellow filter, a magenta filter, and a cyan filter. The color filter array may further include a white filter.

The microlens ML may be formed on the color filter CF. The microlens ML can adjust the path of the incident light so that the incident light incident on the microlens ML can be converged on the photoelectric conversion region PD. In addition, the microlenses ML may be included in a microlens array arranged in a matrix form.

According to the embodiment, an anti-reflection layer (not shown) may be further formed between the second surface 401b of the semiconductor substrate 401 and the color filter CF. The anti-reflection layer may prevent the incident light from being reflected. According to an embodiment, the anti-reflection layer may be formed by alternately stacking materials having different refractive indexes. In this case, the transmittance of the anti-reflection layer may be improved as the materials having different refractive indexes are alternately stacked.

12A, 12B, 12C, 12D, 12E and 12F are cross-sectional views for explaining an example of a method of manufacturing the unit pixel and the image sensor including the unit pixel of FIG.

12A, an element isolation region 410 is vertically formed from a first surface 401a of a semiconductor substrate 401 to define a unit pixel region UPA in the entire region UPT. For example, the semiconductor substrate 401 may be a p-type epitaxial layer. the p-type epitaxial layer is formed on a p-type bulk silicon substrate (not shown), and the p-type bulk silicon substrate is ground by a mechanical method and / or a chemical method to form a semiconductor substrate 401 . In addition, the element isolation region 410 can be provided by etching the semiconductor substrate 401 to form a trench and filling the trench with an insulating material.

Although not shown, the insulating material may have a different energy and may be implanted a plurality of times to form the element isolation region 410. As the implantation is performed a plurality of times as described above, the element isolation region 410 has a surface It can have an oval convex structure.

Referring to FIG. 12B, a photoelectric conversion region PD, a first floating diffusion region FD1, and a second floating diffusion region FD2 are formed in a semiconductor substrate 401. FIG. For example, the photoelectric conversion region PD, the first and second floating diffusion regions FD1 and FD2 are formed by doping n-type impurities into the semiconductor substrate 401 using an ion implantation process can do.

Although not shown, the photoelectric conversion region PD may be formed by stacking a plurality of doped regions.

According to the embodiment, the photoelectric conversion region PD, the first and second floating diffusion regions FD1 and FD2 may be formed sequentially or substantially simultaneously. 12A and 12B illustrate that the regions PD, FD1 and FD2 are formed after the element isolation region 410 is formed. However, after the regions PD, FD1 and FD2 are formed according to the embodiment An element isolation region 410 may be formed.

12C, a part of the semiconductor substrate 401 between the first floating diffusion region FD1 and the second floating diffusion region FD2 is removed so as to be electrically connected to the first surface 401a of the semiconductor substrate 401, A recess 405 is formed. For example, a dry and / or wet etch process may be used to etch a portion of the semiconductor substrate 401 on which the double conversion gain gate (DG of FIG. 12D) is to be formed by a certain depth to form the recess 405 have. The shape and depth of the recess 405 can be varied variously.

Although not shown, a channel impurity region (not shown) may be provided by doping p-type impurities on the side wall and the bottom surface of the recess 405.

12D, a first insulating layer 420 is formed on a first surface 401a of a semiconductor substrate 401 and a transfer gate TG and a double conversion gain gate (DG). For example, the first insulating layer 420 may be formed of a material selected from the group consisting of silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride (SiNx), germanium oxynitride (GeOxNy), germanium silicon oxide (GeSixOy) Or may be formed with a multi-layer structure composed of two or more selected materials among the above-mentioned materials. In addition, the gate structures TG and DG can be provided by laminating a gate conductive film on the first insulating layer 420 and then patterning the stacked gate conductive film. A transfer gate TG is formed on the semiconductor substrate 401 between the photoelectric conversion region PD and the first floating diffusion region FD1 to fill the recess 405 in Figure 12C to form first and second floating diffusion A double conversion gain gate DG may be formed vertically from the first surface 401a of the semiconductor substrate 401 so as to be adjacent to the regions FD1 and FD2. For example, a vertical dual conversion gain gate (DG) may be provided by forming a conductive layer to fill the interior of the recess (405 in FIG. 12C), which may be doped polysilicon, metal, And at least one material selected from metal silicides.

Depending on the embodiment, the transfer gate TG and the double conversion gain gate DG may be formed sequentially or substantially simultaneously.

Referring to FIG. 12E, a second insulating layer 430 including a plurality of metal wirings WL is formed on the transfer gate TG and the double conversion gain gate DG. 12F, a color filter CF is formed on the second surface 401b of the semiconductor substrate 401, and a microlens ML is formed on the color filter CF.

For example, the color filter CF may be formed using a dyeing process, a pigment dispersion process, a printing process, or the like. The color filter CF may be formed by applying a photosensitive material such as a dyed photoresist, and performing an exposure and development process. In addition, it is possible to form patterns using a light-transmissive photoresist, reflow the pattern, and form a microlens ML having a certain curvature and having a convex shape toward a direction in which the incident light is provided. In one embodiment, in the case where the microlens ML includes a photoresist, a baking process may be performed so that the microlens ML maintains its shape.

Although not shown, a planarization layer (not shown) such as an over-coating layer (OCL) may be formed between the color filter CF and the microlens ML.

13 is a cross-sectional view illustrating unit pixels of an image sensor according to embodiments of the present invention. Fig. 14 is an enlarged cross-sectional view of part A of Fig.

13 and 14, the unit pixel 400a of the image sensor includes a photoelectric conversion region PD formed in the semiconductor substrate 401, a first floating diffusion region FD1, a transfer gate TG, A diffusion region FD2 and a double conversion gain gate (DGR). The unit pixel 400a may further include an isolation region 410, a first insulation layer 420, a second insulation layer 430, a color filter CF, and a microlens ML.

The first photoelectric conversion region PD, the first and second floating diffusion regions FD1 and FD2, the transfer gate TG, the element isolation region 410, the first insulation layer 420, The first and second floating diffusion regions FD1 and FD2, the transfer gate TG, the element isolating region 430, the color filter CF, and the microlens ML, The first insulating layer 420, the second insulating layer 430, the color filter CF, and the microlens ML, respectively.

The dual conversion gain gate DGR is vertically formed from the first surface 401a of the semiconductor substrate 401 so as to be adjacent to the first and second floating diffusion regions FD1 and FD2 and has at least one lower region BPR And an upper region TP.

14, the lower surface S1 of the at least one lower region BPR is flat and the lower surface S1R of the at least one lower region BPR is in contact with the lower edge S2) may be round. In this case, when the double conversion gain control signal (DX in Fig. 1) applied to the double conversion gain gate (DGR) is activated, the first point P1 in the semiconductor substrate 401 adjacent to the lower surface S1 and The electric field distribution can be uniformly formed at both the lower edge S2 and the second point P2 in the semiconductor substrate 401 adjacent thereto. Therefore, the channel between the first and second floating diffusion regions FD1 and FD2 is easily formed, and the charge transfer between the first and second floating diffusion regions FD1 and FD2 can be smoothly performed. The first width W1 of the upper end of the at least one lower region BPR may be greater than the second width W2 of the lower surface S1. For example, the second width W2 may be greater than the first width W2, Half of the width W1.

The radius of curvature R of the bottom edge S2 of the at least one bottom region BPR may be greater than the radius of curvature R of at least one of the bottom regions BPR in order to evenly form the electric field distribution at the second point P2 in the semiconductor substrate 401. [ ) May have a certain range. For example, the radius of curvature R of the bottom edge S2 may have a value between about 10 nm and 100 nm, and preferably between about 60 nm and 100 nm. Here, the radius of curvature R of the bottom edge S2 may indicate the radius of a circle that shares the bottom edge S2 (e.g., the dotted line in FIG. 14). When the curvature radius R of the lower edge S2 is less than 10 nm, the charge transfer characteristic may be deteriorated by the electric field barrier. When the curvature radius R of the lower edge S2 is greater than 100 nm Which can cause problems in the manufacturing process.

15A, 15B, 15C, and 15D are cross-sectional views for explaining an example of a method of manufacturing a unit pixel and an image sensor including the unit pixel of FIG.

In the fabrication of the unit pixels and the image sensor including the same in Fig. 13, the step of forming the element isolation region and the step of forming the photoelectric conversion region and the floating diffusion regions are substantially the same as those described with reference to Figs. 12A and 12B, respectively Do. The embodiment of manufacturing the unit pixel of FIG. 13 and the image sensor including the unit pixel of FIG. 13 includes the embodiment of manufacturing the unit pixel of FIG. 11 and the image sensor including the same, except that the structure of the double conversion gain gate (DGR) So that redundant description will be omitted.

Referring to FIG. 15A, a portion of the semiconductor substrate 401 between the first floating diffusion region FD 1 and the second floating diffusion region FD 2 is removed to form a recess 406. For example, a recess 406 can be formed by etching a portion of the semiconductor substrate 401 on which a double conversion gain gate (DGR in FIG. 15B) is to be formed, by a predetermined depth. The bottom surface C1 of the recess 406 may be flat and the bottom edge C2 may be rounded.

According to the embodiment, the isotropic etching process is performed after forming the recess having the angled edge by the anisotropic etching process, or the recess having the angled edge is formed by the anisotropic etching process, and then the thermal oxidation process is performed, A recess 406 having a flat bottom surface C1 and a rounded corner C2 can be formed by removing the thermal oxide film.

In one embodiment, the radius of curvature of the bottom edge C2 of the recess 406 may have a constant range. For example, the radius of curvature of the lower edge C2 may have a value between about 10 nm and 100 nm, and preferably between about 60 nm and 100 nm.

15B, a first insulating layer 420 is formed on a first surface 401a of a semiconductor substrate 401 and a transfer gate TG and a double conversion gain gate (DGR). Referring to FIG. 15C, a second insulating layer 430 including a plurality of metal wirings WL is formed on the transfer gate TG and the double conversion gain gate DGR. 15D, a color filter CF is formed on the second surface 401b of the semiconductor substrate 401, and a microlens ML is formed on the color filter CF.

16, 17, 18, 19, 20 and 21 are sectional views showing unit pixels of an image sensor according to embodiments of the present invention.

16, the unit pixel 400b of the image sensor includes a photoelectric conversion region PD formed in the semiconductor substrate 401, a first floating diffusion region FD1, a transfer gate TG, (FD2) and a dual conversion gain gate (DG). The unit pixel 400b may further include an isolation region 410a, a first insulation layer 420, a second insulation layer 430, a color filter CF, and a microlens ML.

The first photoelectric conversion region PD, the first and second floating diffusion regions FD1 and FD2, the transfer gate TG, the double conversion gain gate DG, the first insulation layer 420, The layer 430, the color filter CF and the microlenses ML are formed in the same manner as the photoelectric conversion region PD of FIG. 11, the first and second floating diffusion regions FD1 and FD2, the transfer gate TG, The first insulating layer 420, the second insulating layer 430, the color filter CF, and the microlens ML, as shown in FIG.

The element isolation region 410a of FIG. 16 may be formed so as to be deeper than the photoelectric conversion region PD from the first surface 401a of the semiconductor substrate 401. For example, the element isolation region 410a may be a DTI region formed from the first surface 401a to the second surface 401b of the semiconductor substrate 401, and a longitudinal section of the element isolation region 410a may be a DTI region, And the second surface 401b of the base 401.

In one embodiment, the element isolation region 410a may be formed of an insulating material having a refractive index smaller than that of the semiconductor substrate 401 with respect to incident light. In this case, the leakage component L1 of the incident light generated by the microlens ML is totally reflected on the surface of the element isolation region 410a, and the leakage component L1 reaches the adjacent unit pixels (not shown) And the reflection component L2 whose leakage component L1 is reflected by the element isolation region 410a can reach the photoelectric conversion region PD. Also, since the element isolation region 410a is formed of the insulating material, the charge carriers generated by the incident light can be prevented from reaching the adjacent unit pixels by diffusion. Therefore, the crosstalk between adjacent unit pixels is reduced and the SNR (Signal-to-Noise Ratio) characteristic of the image sensor including the unit pixel 400b can be improved.

Referring to FIG. 17, the unit pixel 400c of the image sensor includes a photoelectric conversion region PD 'formed in the semiconductor substrate 401, a first floating diffusion region FD1, a transfer gate TG, Region FD2 and a dual conversion gain gate DG. The unit pixel 400c may further include an isolation region 410a, a first insulation layer 420, a second insulation layer 430, a color filter CF, and a microlens ML.

The first and second floating diffusion regions FD1 and FD2, the transmission gate TG, the double conversion gain gate DG, the first insulation layer 420, the second insulation layer 430, The first and second floating diffusion regions FD1 and FD2, the transmission gate TG, the double conversion gain gate DG, the first insulation layer 420, The second insulating layer 430, the color filter CF, and the microlens ML, respectively. The element isolation region 410a of FIG. 17 may be substantially the same as the element isolation region 410a of FIG.

The photoelectric conversion region PD 'of FIG. 17 is formed in the semiconductor substrate 401 and may be formed to contact the second surface 401b of the semiconductor substrate 401, for example. In other words, the photoelectric conversion region PD of FIG. 16 contacts only the first surface 401a of the semiconductor substrate 401, but the photoelectric conversion region PD 'of FIG. 17 corresponds to the first surface 401a of the semiconductor substrate 401 401a and the second surface 401b. Although not shown, the photoelectric conversion region may be formed so as to contact only the second surface 401b of the semiconductor substrate 401. [

On the other hand, according to the embodiment, the double conversion gain gate DG of Figs. 16 and 17 may be formed such that the lower surface of at least one lower region is flat and the lower edge is rounded as described above with reference to Figs. 13 and 14 have.

Referring to FIG. 18, the unit pixel 400d of the image sensor includes a photoelectric conversion region PD formed in the semiconductor substrate 401, a first floating diffusion region FD1, a transfer gate TG, (FD2) and a dual conversion gain gate (DG). The unit pixel 400d may further include an element isolation region 410, a first insulating layer 420, a second insulating layer 430, a third insulating layer 440, a color filter CF, and a microlens ML .

The first photoelectric conversion region PD, the first and second floating diffusion regions FD1 and FD2, the transfer gate TG, the double conversion gain gate DG, the element isolation region 410, The first insulating layer 420, the second insulating layer 430, the color filter CF and the microlens ML are formed in the same manner as the photoelectric conversion region PD of FIG. 11, the first and second floating diffusion regions FD1 and FD2, The first insulating layer 420, the second insulating layer 430, the color filter CF, and the microlenses ML, and the gate electrode TG, the double conversion gain gate DG, the element isolation region 410, . ≪ / RTI >

The third insulating layer 440 of FIG. 18 may be formed between the second surface 401b of the semiconductor substrate 401 and the color filter CF. In one embodiment, the third insulating layer 440 may have a negative fixed charge. For example, the third insulating layer 440 may be formed by oxidizing metal elements such as hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y) And may have at least a partially crystallized region in the film.

Hole accumulation may occur in the lower region of the semiconductor substrate 401 when the third insulating layer 440 has a negative fixed charge. Noises may be generated by surface defects present on the rear surface 401b of the semiconductor substrate 401 in the manufacturing process of the image sensor of the rear light receiving type. As described above, by the third insulating layer 440 The accumulated holes can be used to passivate such surface defects. For example, electrons generated in a dark state (i.e., dark current) are combined with the accumulated holes, so that occurrence of dark current can be reduced.

The third insulating layer 440 may include an optical shielding layer (not shown) for preventing light from entering the optical black area (not shown) which is a region where photoelectric conversion does not occur in the semiconductor substrate 401, , Not shown).

On the other hand, according to the embodiment, the double conversion gain gate DG of Fig. 18 may be formed such that the lower surface of at least one lower region is flat and the lower edge is rounded as described with reference to Figs. 13 and 14, 18 may be formed from the first surface 401a to the second surface 401b of the semiconductor substrate 401 as described above with reference to FIG. 16, and the photoelectric conversion regions PD May be formed to contact the second surface 401b of the semiconductor substrate 401 as described above with reference to Fig.

19, the unit pixel 400e of the image sensor includes a photoelectric conversion region PD formed in the semiconductor substrate 401, a first floating diffusion region FD1, a transfer gate TG ', a second floating diffusion Region FD2 and a dual conversion gain gate DG. The unit pixel 400e may further include an element isolation region 410, a first insulating layer 420, a second insulating layer 430, a color filter CF, and a microlens ML.

The first and second floating diffusion regions FD1 and FD2, the double conversion gain gate DG, the element isolation region 410, the first insulation layer 420, the second photoelectric conversion region PD, The insulating layer 430, the color filter CF and the microlens ML are formed by the photoelectric conversion region PD of FIG. 11, the first and second floating diffusion regions FD1 and FD2, the double conversion gain gate DG, The device isolation region 410, the first insulating layer 420, the second insulating layer 430, the color filter CF, and the microlens ML, respectively.

The transfer gate TG 'in FIG. 19 may be formed vertically from the first surface 401a of the semiconductor substrate 401 so as to be adjacent to the photoelectric conversion region PD and the first floating diffusion region FD1. In other words, both the transfer gate TG 'and the dual conversion gain gate DG can have a vertical gate structure. For example, the transfer gate TG 'is formed on the first surface 401a of the semiconductor substrate 401 and the lower region formed inside the semiconductor substrate 401 and surrounded by the semiconductor substrate 401, And an upper region connected to the lower region.

On the other hand, according to the embodiment, the double conversion gain gate (DG) and / or the transmission gate TG 'of FIG. 19 are formed such that the lower surface of at least one lower region is flat, The element isolation region 410 of FIG. 19 may be formed from the first surface 401a to the second surface 401b of the semiconductor substrate 401 as described above with reference to FIG. 16 , The photoelectric conversion region PD of FIG. 19 may be formed to contact the second surface 401b of the semiconductor substrate 401 as described above with reference to FIG. The unit pixel 400e of FIG. 19 may further include a third insulating layer 440 as described above with reference to FIG.

Referring to FIG. 20, the unit pixel 400f of the image sensor includes a photoelectric conversion region PD ", a first floating diffusion region FD1, a transfer gate TG" A diffusion region FD2 and a dual conversion gain gate DG. The unit pixel 400f may further include an element isolation region 410a, a first insulation layer 420, a second insulation layer 430, a color filter CF, and a microlens ML.

The first and second floating diffusion regions FD1 and FD2, the double conversion gain gate DG, the first insulating layer 420, the second insulating layer 430, the color filter CF, The first insulating layer 420 and the second insulating layer 430 are formed on the first and second floating diffusion regions FD1 and FD2, the double conversion gain gate DG, the first insulating layer 420, the color filter CF And the microlenses ML, respectively. The element isolation region 410a of FIG. 20 may be substantially the same as the element isolation region 410a of FIG.

The photoelectric conversion region PD "in Fig. 20 can be formed in a region (i.e., relatively deep) farther from the first surface 401a of the semiconductor substrate 401 than the photoelectric conversion region PD in Fig. 11, The transfer gate TG "in FIG. 20 is formed in the unit pixel region as a whole and has a relatively large area. The transfer gate TG " in FIG. 20 includes the photoelectric conversion region PD & The first insulating layer 420 may be formed vertically from the first surface 401a of the semiconductor substrate 401 so as to be adjacent to the region FD1 of the transfer gate TG. The portion of the first insulating layer 420 under the transfer gate TG "and the photoelectric conversion region PD" may be spaced apart from each other, according to the embodiment.

On the other hand, according to the embodiment, the double conversion gain gate (DG) and / or the transmission gate TG "in Fig. 20 are formed such that the lower surface of at least one lower region is flat, The unit pixel 400f of FIG. 20 may further include a third insulating layer 440 as described above with reference to FIG.

21, a unit pixel 400g of the image sensor includes a photoelectric conversion region PD formed in a semiconductor substrate 401, a first floating diffusion region FD1, a transfer gate TG, a second floating diffusion region (FD2) and a dual conversion gain gate (DG). The unit pixel 400g may further include an element isolation region 410, a first insulation layer 420, a second insulation layer 430, a color filter CF ', and a microlens ML'. For example, the unit pixel 400g may be included in the FIS.

The first photoelectric conversion region PD, the first and second floating diffusion regions FD1 and FD2, the transfer gate TG, the double conversion gain gate DG, the element isolation region 410, The first and second floating diffusion regions FD1 and FD2 and the transfer gate TG and the double conversion gain gate DG of FIG. The device isolation region 410, the first insulating layer 420, and the second insulating layer 430, respectively.

The color filter CF 'of FIG. 21 may be formed on the first surface 401b of the semiconductor substrate 401. FIG. For example, a color filter CF 'may be formed on the transfer gate TG and the dual conversion gain gate DG, or on the second insulating layer 430. The microlens ML 'may be formed on the color filter CF'.

On the other hand, according to the embodiment, the double conversion gain gate DG of FIG. 21 may be formed such that the lower surface of at least one lower region is flat and the lower edge is rounded, as described above with reference to FIGS. 13 and 14, 21 may be formed from the first surface 401a to the second surface 401b of the semiconductor substrate 401 as described above with reference to FIG. 16, or may be formed in the photoelectric conversion region PD May be formed to contact the second surface 401b of the semiconductor substrate 401 as described above with reference to FIG. 17, and the transfer gate TG of FIG. 21 may be formed to contact the second surface 401b of the semiconductor substrate 401, Type gate structure. In addition, the unit pixel 400G of FIG. 21 may further include a third insulating layer 440 as described above with reference to FIG.

22 is a block diagram illustrating an image sensor including unit pixels according to embodiments of the present invention.

Referring to FIG. 22, the image sensor 500 includes a pixel array 510 and a signal processing unit 520.

The pixel array 510 generates a plurality of pixel signals (e.g., analog pixel signals) based on the incident light. The pixel array 510 may include a plurality of unit pixels arranged in a matrix of a plurality of rows and a plurality of columns. 2, 3, 4, 5, 7, 8, 9, 11, 13, 16, 17, 18, 19, 20 and 21 may be used as the unit pixel 100 of FIG. The above structure can be obtained. That is, each of the plurality of unit pixels includes a double conversion gain gate having a vertical gate structure such that the surface area in contact with the semiconductor substrate is increased, and the double conversion gain control signal applied to the double conversion gain gate is selectively activated The conversion gain of the plurality of unit pixels and the image sensor 500 including the plurality of unit pixels can be effectively adjusted without reducing the fill factor.

The signal processing unit 520 generates image data (for example, digital effective image data) based on the plurality of pixel signals. The signal processing unit 520 includes a row driving unit 530, an analog-to-digital conversion (ADC) unit 540, a digital signal processing (DSP) unit 550, . ≪ / RTI >

The row driver 530 is connected to each row of the pixel array 510 and may generate a driving signal for driving the respective row. For example, the row driver 530 may drive the plurality of unit pixels included in the pixel array 510 in a row unit.

The ADC unit 540 is connected to each column of the pixel array 510 and can convert an analog signal output from the pixel array 510 into a digital signal. In one embodiment, the ADC portion 540 may include a plurality of analog-to-digital converters and may perform column ADCs that convert the analog signals output for each column line in parallel (i.e., concurrently) to digital signals . In another embodiment, the ADC portion 540 includes a single analog-to-digital converter and can perform a single ADC that sequentially converts the analog signals into digital signals.

According to an embodiment, the ADC unit 540 may include at least one correlated double sampling (CDS) unit (not shown) for extracting a valid signal component. In one embodiment, the CDS unit may perform analog double sampling to extract the effective image component based on a difference between an analog reset signal representative of a reset component and an analog image signal representative of an image component. In another embodiment, the CDS unit performs digital double sampling, which converts the analog reset signal and the analog image signal into digital signals and then extracts the difference between the two digital signals as the effective image component can do. In yet another embodiment, the CDS unit may perform dual correlated double sampling that performs both the analog double sampling and the digital double sampling.

The DSP unit 550 may receive the digital signal output from the ADC unit 540 and may perform image data processing on the digital signal. For example, the DSP unit 550 may perform image interpolation, color correction, white balance, gamma correction, color conversion, and the like .

The control unit 560 may control the row driver 530, the ADC unit 540, and the DSP unit 550. The controller 560 may supply control signals such as a clock signal, a timing control signal, and the like required for the operations of the row driver 530, the ADC 540, and the DSP 550. In one embodiment, the control unit 560 may include a logic control circuit, a phase locked loop (PLL) circuit, a timing control circuit, and a communication interface circuit.

In one embodiment, the control unit 560 may receive a user setting signal USS to set the operating mode of the image sensor 500. [ The user setting signal USS indicates a signal input from the user and the double conversion gain control signal (DX in FIG. 1) applied to the unit pixel of the pixel array 510 based on the user setting signal USS is selectively Can be activated. For example, when the user setting signal USS has a first value corresponding to the high contrast operation mode, the control unit 560 can activate the double conversion gain control signal, and the unit pixel and the image sensor 500 may operate as the example shown in FIG. 10B based on the activated dual conversion gain control signal. If the user setting signal USS has a second value corresponding to the low light intensity operation mode, the controller 560 may deactivate the double conversion gain control signal, and the unit pixel and the image sensor 500 may be deactivated Lt; RTI ID = 0.0 > 10A, < / RTI > In the image sensor 500, whether to activate the double conversion gain control signal may be manually determined based on a user setting signal USS input from the user.

23 is a flowchart for explaining the operation of the image sensor of FIG.

Referring to FIGS. 22 and 23, the controller 560 included in the signal processor 520 determines whether the user setting signal USS has the first value or the second value (step S110).

If the user setting signal USS has the first value (S110: YES), the controller 560 included in the signal processor 520 determines that the image sensor 500 is set to the high-illuminance operation mode And activates the double conversion gain control signal (step S130). The image sensor 500 operates in the light integration mode (TINT) and the read mode (TRD) as shown in FIG. 10B based on the activated double conversion gain control signal (step S170).

The control unit 560 included in the signal processing unit 520 determines that the image sensor 500 is set to the low-illuminance operation mode, if the user setting signal USS has the second value (S110: NO) The dual conversion gain control signal is deactivated (step S150). The image sensor 500 operates in the light integration mode (TINT) and the read mode (TRD) as shown in FIG. 10A based on the deactivated dual conversion gain control signal (step S170).

24 is a block diagram illustrating an image sensor including unit pixels according to embodiments of the present invention.

Referring to FIG. 24, the image sensor 600 includes a pixel array 610 and a signal processing unit 620.

The pixel array 610 includes a plurality of unit pixels, and generates a plurality of pixel signals based on the incident light. A signal processing unit 620 generates image data based on the plurality of pixel signals. The signal processing unit 620 may include a row driving unit 630, an ADC unit 640, a DSP unit 650, a control unit 660, and an operation mode detecting unit 670. The pixel array 610, the row driver 630, the ADC unit 640 and the DSP unit 650 of FIG. 24 correspond to the pixel array 510, the row driver 530, the ADC unit 540, (550), respectively.

The operation mode detection unit 670 can automatically determine the operation mode of the image sensor based on the illuminance of the incident light and the reference illuminance. For example, when the illuminance of the incident light is higher than the reference illuminance, the operation mode detector 670 may generate a mode signal MS having a first value corresponding to the high contrast operation mode. When the illuminance of the incident light is lower than or equal to the reference illuminance, the operation mode detector 670 may generate a mode signal MS having a second value corresponding to the low-illuminance operation mode.

The control unit 660 may control the row driving unit 630, the ADC unit 640, and the DSP unit 650. In one embodiment, the control unit 660 receives the mode signal MS and generates a double conversion gain control signal (DX in FIG. 1) applied to a unit pixel of the pixel array 610 based on the mode signal MS. Can be selectively activated. For example, when the user setting signal USS has the first value, the controller 660 may activate the double conversion gain control signal, and the unit pixel and the image sensor 600 may be activated And can operate as the example shown in Fig. 10B based on the double conversion gain control signal. When the user setting signal USS has the second value, the controller 660 may deactivate the double conversion gain control signal, and the unit pixel and the image sensor 600 may control the deactivated dual conversion gain control Based on the signal shown in Fig. 10A. In the image sensor 600, whether to activate the double conversion gain control signal may be automatically determined based on the illuminance of the incident light.

25 is a flowchart for explaining the operation of the image sensor of FIG.

Referring to FIGS. 24 and 25, the operation mode detector 670 included in the signal processor 620 determines whether the illuminance of the incident light is higher or lower than or equal to the reference illuminance (step S210).

If the illuminance of the incident light is higher than the reference illuminance (S210: YES), the operation mode detector 670 included in the signal processor 620 outputs the mode signal having the first value corresponding to the high- MS), and the control unit 660 included in the signal processing unit 620 activates the double conversion gain control signal based on the mode signal MS (step S230). The image sensor 600 operates in the light integration mode (TINT) and the read mode (TRD) as shown in FIG. 10B based on the activated double conversion gain control signal (step S270).

If the illuminance of the incident light is lower than or equal to the reference illuminance (S210: NO), the operation mode detector 670 included in the signal processor 620 detects the mode signal having the second value corresponding to the low- And the control unit 660 included in the signal processing unit 620 deactivates the double conversion gain control signal based on the mode signal MS (step S250). The image sensor 600 operates in the light integration mode (TINT) and the read mode (TRD) as shown in FIG. 10A based on the deactivated dual conversion gain control signal (step S270).

26 is a block diagram illustrating a computing system including an image sensor in accordance with embodiments of the present invention.

Referring to Figure 26, a computing system 900 may include a processor 910, a memory device 920, a storage device 930, an image sensor 940, an input / output device 950, and a power supply 960 have. 26, the computing system 900 may further include ports capable of communicating with, or communicating with, video cards, sound cards, memory cards, USB devices, and the like .

Processor 910 may perform certain calculations or tasks. In accordance with an embodiment, the processor 910 may be a micro-processor or a central processing unit (CPU). The processor 910 is connected to the memory device 920, the storage device 930, and the input / output device 950 via an address bus, a control bus, and a data bus, Can be performed. In accordance with an embodiment, the processor 910 may also be coupled to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

The memory device 920 may store data necessary for operation of the computing system 900. For example, the memory device 920 may be a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like, and an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a ferroelectric random access memory A non-volatile memory device such as a FRAM, a Resistive Random Access Memory (RRAM), a Ferromagnetic Random Access Memory (MRAM), and the like.

The storage device 930 may include a solid state drive, a hard disk drive, and a CD-ROM. The input / output device 950 may include input means such as a keyboard, a keypad, a mouse, etc., and output means such as a printer, a display, and the like. The power supply 960 may supply the operating voltage required for operation of the computing system 900.

The image sensor 940 may be in communication with the processor 910 through the buses or other communication links. The image sensor 940 may be one of the image sensors 500 and 600 of Figures 22 and 24 and may be any of the image sensors 910 and 920 of Figures 1, 2, 3, 4, 5, 7, 8, 9, 11, 13, 16, 18, 19, 20, and 21 described above. That is, the unit pixel includes a double conversion gain gate having a vertical gate structure to increase the surface area in contact with the semiconductor substrate, and the double conversion gain control signal applied to the double conversion gain gate is selectively activated, The conversion gain of the unit pixel and the image sensor 940 including the unit pixel can be effectively controlled.

The image sensor 940 may be implemented in various types of packages. For example, at least some of the configurations of the image sensor 940 may include Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Level Processed Stack Package (WSP) and the like.

Depending on the embodiment, the image sensor 940 may be integrated on one chip with the processor 910, or may be integrated on different chips, respectively. On the other hand, the computing system 900 may be interpreted as any computing system that utilizes an image sensor. For example, the computing system 900 may include a digital camera, a mobile phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, and the like.

27 is a block diagram illustrating an example of an interface used in the computing system of Fig.

27, the computing system 1000 may be implemented as a data processing device (e.g., a mobile phone, PDA, PMP, smart phone, etc.) capable of using or supporting a MIPI interface, A stacked image sensor 1140, a display 1150, and the like.

The CSI host 1112 of the application processor 1110 can perform serial communication with the CSI device 1141 of the stacked image sensor 1140 through a camera serial interface (CSI). In one embodiment, the CSI host 1112 may include an optical deserializer (DES), and the CSI device 1141 may include an optical serializer (SER). The DSI host 1111 of the application processor 1110 can perform serial communication with the DSI device 1151 of the display 1150 through a display serial interface (DSI). In one embodiment, the DSI host 1111 may include an optical serializer (SER), and the DSI device 1151 may include an optical deserializer (DES).

In addition, the computing system 1000 may further include a Radio Frequency (RF) chip 1160 capable of communicating with the application processor 1110. The PHY 1113 of the computing system 1000 and the PHY 1161 of the RF chip 1160 can perform data transmission and reception according to a Mobile Industry Processor Interface (MIPI) DigRF. The application processor 1110 may further include a DigRF MASTER 1114 for controlling data transmission and reception according to the MIPI DigRF of the PHY 1161. The RF chip 1160 may include a DigRF MASTER 1114, SLAVE < / RTI >

Meanwhile, the computing system 1000 includes a Global Positioning System (GPS) 1120, a storage 1170, a microphone 1180, a Dynamic Random Access Memory (DRAM) 1185 and a speaker 1190 . In addition, the computing system 1000 may utilize an Ultra Wide Band (UWB) 1210, a Wireless Local Area Network (WLAN) 1220, and a Worldwide Interoperability for Microwave Access (WIMAX) So that communication can be performed. However, the structure and the interface of the computing system 1000 are not limited thereto.

The present invention can be applied to an image sensor and any device and electronic device including the same. In particular, the present invention can be applied to a computer, a digital camera, a three-dimensional camera, a mobile phone, a PDA, a scanner, a navigation system for a vehicle, a video phone, a surveillance system, an autofocus system,

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined in the appended claims. It will be understood.

Claims (20)

A photoelectric conversion region formed in the semiconductor substrate and collecting photo charges based on the incident light;
A first floating diffusion region formed in the semiconductor substrate apart from the photoelectric conversion region;
A transfer gate formed on the semiconductor substrate between the photoelectric conversion region and the first floating diffusion region, the transfer gate transferring the photo charges to the first floating diffusion region based on a transfer control signal;
A second floating diffusion region formed in the semiconductor substrate so as to be spaced apart from the photoelectric conversion region and the first floating diffusion region; And
A second floating diffusion region formed vertically from a first side of the semiconductor substrate to be adjacent to the first and second floating diffusion regions and selectively transferring the light charges to the second floating diffusion region based on a double conversion gain control signal; A unit pixel of an image sensor comprising a conversion gain gate. 2. The dual conversion gain gate of claim 1,
At least one lower region formed within the semiconductor substrate, at least a portion of which is included in the semiconductor substrate and is surrounded by the semiconductor substrate; And
And an upper region formed on the first surface of the semiconductor substrate and connected to the at least one lower region. 3. The method of claim 2,
Wherein a depth of the at least one lower region of the dual conversion gain gate is shallower than a depth of the first and second floating diffusion regions. 3. The method of claim 2,
And the conversion gain of the unit pixel decreases as the depth of the at least one lower region of the double conversion gain gate becomes deeper. 3. The method of claim 2,
And the conversion gain of the unit pixel decreases as the number of the at least one lower region of the double conversion gain gate increases. 3. The method of claim 2,
Wherein the lower surface of the at least one lower region of the double conversion gain gate is planar and the lower edge of the at least one lower region of the double conversion gain gate is rounded. The method according to claim 6,
Wherein the curvature radius of the lower edge of the at least one lower region of the double conversion gain gate has a value between 10 nm and 100 nm. The method according to claim 1,
Further comprising a reset gate formed on the semiconductor substrate and resetting the first and second floating diffusion regions based on a reset signal. 9. The method of claim 8,
Wherein the first floating diffusion region is formed in the semiconductor substrate between the transfer gate and the double conversion gain gate and the second floating diffusion region is formed in the semiconductor substrate between the double conversion gain gate and the reset gate A unit pixel of an image sensor characterized by: 9. The method of claim 8,
Wherein the first floating diffusion region is formed in the semiconductor substrate between the transfer gate and the double conversion gain gate and between the transfer gate and the reset gate. The method according to claim 1,
Wherein the dual conversion gain control signal is selectively activated according to the illuminance of the incident light. The method according to claim 1,
Wherein the double conversion gain control signal is selectively activated based on an externally applied user setting signal. The method according to claim 1,
And an output unit connected to the first floating diffusion region and generating an image signal corresponding to the incident light based on the photo charges. A pixel array including a plurality of unit pixels and generating a plurality of pixel signals based on incident light; And
And a signal processing unit for generating image data based on the plurality of pixel signals,
Wherein each of the plurality of unit pixels comprises:
A photoelectric conversion region formed in the semiconductor substrate and collecting photo charges based on the incident light;
A first floating diffusion region formed in the semiconductor substrate apart from the photoelectric conversion region;
A transfer gate formed on the semiconductor substrate between the photoelectric conversion region and the first floating diffusion region, the transfer gate transferring the photo charges to the first floating diffusion region based on a transfer control signal;
A second floating diffusion region formed in the semiconductor substrate so as to be spaced apart from the photoelectric conversion region and the first floating diffusion region; And
A second floating diffusion region formed vertically from a first side of the semiconductor substrate to be adjacent to the first and second floating diffusion regions and selectively transferring the light charges to the second floating diffusion region based on a double conversion gain control signal; An image sensor comprising a conversion gain gate. 15. The method of claim 14,
Wherein the signal processing unit includes an operation mode detection unit that automatically determines an operation mode of the image sensor based on the illuminance of the incident light and the reference illuminance,
Wherein the signal processing unit activates the double conversion gain control signal when the illuminance of the incident light is higher than the reference illuminance and when the illuminance of the incident light is lower than or equal to the reference illuminance, Inactivates the image sensor. 15. The method of claim 14,
Wherein the signal processing unit receives a user setting signal for setting an operation mode of the image sensor,
Wherein the signal processing unit activates the double conversion gain control signal when the user setting signal corresponds to the high contrast operation mode, and when the user setting signal corresponds to the low light operation mode, the signal processing unit performs the double conversion gain control Wherein the signal is deactivated. Forming a photoelectric conversion region in the semiconductor substrate, a first floating diffusion region spaced apart from the photoelectric conversion region, and a second floating diffusion region spaced apart from the photoelectric conversion region and the first floating diffusion region;
Removing a portion of the semiconductor substrate between the first floating diffusion region and the second floating diffusion region to form a recess;
Forming a transfer gate on the semiconductor substrate between the photoelectric conversion region and the first floating diffusion region; And
And forming a double conversion gain gate vertically from the first side of the semiconductor substrate to fill the recess and adjacent the first and second floating diffusion regions. 18. The method of claim 17,
Wherein the lower surface of the recess is flat and the lower edge of the recess is rounded. 19. The method of claim 18,
Wherein the curvature radius of the bottom edge of the recess has a value between 10 nm and 100 nm. 18. The method of claim 17,
Further comprising the step of forming a device isolation region vertically from the first surface of the semiconductor substrate to define a unit pixel region,
Wherein the photoelectric conversion region, the first and second floating diffusion regions, the transfer gate, and the double conversion gain gate are formed in the unit pixel region.

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