KR20150071288A - Liquid Crystal Display - Google Patents

Abstract

The present invention relates to a liquid crystal display device. The liquid crystal display device has: a liquid crystal panel; a memory in which a writing protection function is selectively activated; and a timing controller activating the writing protection function of the memory during a signal period which receives an image signal for screen display on the liquid crystal panel, and deactivating the writing protection function of the memory during a non-signal period which does not receive the image signal.

Description

[0001] Liquid crystal display [0002]

The present invention relates to a liquid crystal display capable of easily changing data in a memory.

2. Description of the Related Art Liquid crystal display devices are one of the most widely used flat panel display devices, and include two substrates on which pixel electrodes and common electrodes are formed, and a liquid crystal layer between two substrates. Such a liquid crystal display determines orientation of liquid crystal molecules in a liquid crystal layer according to an electric field generated by a voltage applied to an electrode, and controls the polarization of incident light to display an image. The liquid crystal display device is advantageous for moving picture display and has a high contrast ratio. Therefore, the liquid crystal display device can be replaced with a cathode ray tube (CRT) instead of a display device .

The liquid crystal display device includes an EEPROM capable of reading model information such as resolution and timing at the time of booting the system, and transmitting the read model information to the liquid crystal driving circuit. The EEPROM is a memory capable of reading and writing. However, in the manufacturing process of the liquid crystal display device, the WP (Write Protection) function of the EEPROM is activated in the state of a liquid crystal module (LCM) in which a liquid crystal panel, a drive circuit, The write function is inhibited.

If the data of the EEPROM is changed while the liquid crystal module is manufactured, it is troublesome to remove the cover shield and float the resistor connected to the WP terminal.

* Related Prior Art

Korean Patent Laid-Open No. 10-2012-0108438, entitled: RESET CIRCUIT AND LIQUID CRYSTAL DISPLAY

The present invention is intended to provide a liquid crystal display capable of easily changing data in a memory.

The liquid crystal display device according to the present invention activates a write protection function of a memory during a signal period in which a liquid crystal panel, a memory in which a write protection function is selectively activated, and a liquid crystal panel are supplied with a video signal for display, And disable the write protection function of the memory during the non-signal period.

Since the liquid crystal display device according to the present invention selectively activates the write protection function of the memory in accordance with the presence or absence of the video signal, the data in the memory can be easily changed without troublesome operation.

1 is a view showing a liquid crystal display device according to the present invention.
Figure 2 shows a memory and timing controller of the present invention.
3 is a flowchart showing a method of writing memory data according to the present invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 is a view showing a liquid crystal display device of the present invention.

Referring to FIG. 1, a liquid crystal display according to the present invention includes a liquid crystal panel 11, a gate driver 11a, a data driver 11b, a timing controller 23, and a memory 25.

The liquid crystal panel 11 has a matrix of pixel regions in which a plurality of gate lines G and data lines D are arranged in a direction perpendicular to each other and thin film transistors And a liquid crystal capacitor Clc connected to the TFT. The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT, and a common electrode arranged between the pixel electrode and the liquid crystal. The TFT supplies a data voltage from each data line D to the pixel electrode in response to a scan pulse from each gate line G. [ The liquid crystal capacitor Clc charges the difference voltage between the data voltage supplied to the pixel electrode and the reference common voltage supplied to the common electrode and varies the arrangement of the liquid crystal molecules according to the difference voltage to adjust the light transmittance to express the luminance . The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied.

The timing controller 23 reads the data stored in the memory 25 and outputs an operation signal for operating the DC-DC converter 24 and various control signals for driving the liquid crystal display panel. At this time, the timing controller 23 inputs the input / output control clock CLK to the memory 25 to receive driving information and image data modulation information of the liquid crystal panel 11, and outputs drive information and image data modulation information The gate driver 11a and the data driver 11b.

The timing controller 23 receives a power supply voltage Vin for generating a voltage such as a backlight driving voltage and an operating voltage. The timing controller 23 receives the video signal required for driving from the interface board 5 in a manner such as a transition minimized differential signaling (TMDS) or a low voltage differential signaling (LVDS) signal.

The timing controller 23 activates or deactivates the write protection function of the memory 25 depending on the presence or absence of a video signal. And includes an input signal determination unit 23-1 and a voltage output unit 23-2 for this purpose. A detailed description of a method for controlling the write protection function of the memory 25 using the timing controller 23 will be described later.

The DC-DC converter 24 receives the voltage from the system through the connector 22 and outputs the driving voltages Vcc and Vdd and outputs the gate low voltage signal VGL and the gate high voltage signal VGL in accordance with the operation signal of the timing controller 23. [ (VGH).

The gate driver 11a receives the gate high voltage signal VGH and the gate low voltage signal VGL from the DC-DC converter 24 according to the operation signal of the timing controller 23 to generate a scan pulse, Are sequentially supplied to the respective gate lines (G) of the panel (11).

The data driver 11b receives the corrected video signal Do, which is a digital signal, from the timing controller 23, converts the corrected video signal Do into a corrected data signal which is an analog signal, and supplies the corrected data signal to the respective data of the liquid crystal display panel 11 To the line (D).

The memory 25 stores the size of the liquid crystal panel 11, resolution conversion information, image data conversion information, driving frequency of the timing controller 23, and driving timing information. When the input / output control clock is input, the memory 25 supplies the stored driving information, image data modulation information, and the like to the timing controller 23. The memory 25 may be an EEPROM (Electrically Erasable Programmable Read Only Memory) or the like. The EEPROM is a memory element in which data is stored even when the power is turned off, and transmits and receives data to and from the timing controller 23 through the serial communication means of the I 2 C bus. I2C is a 2-wire serial communication interface, a method of data communication between an integrated circuit consisting of a serial data line (SDL) and a serial clock line (SCL).

In this liquid crystal display device, the timing controller 23 selectively activates the write protection function of the memory 25 in accordance with a signal supplied from the outside. The connection relationship between the timing controller 23 and the memory 25 will now be described with reference to FIG.

The memory 25 includes a plurality of terminals. The A0 terminal (1) and the A2 terminal (2) are for EEPROM Address setting for I2C communication and are connected to the low potential voltage together with the GND terminal (4). The A1 terminal 1 is connected to the driving potential VCC. The SDA terminal 5 and the SCL terminal 6 are respectively connected to the SCL pin 32 of the SDA pin 31 of the timing controller 23 so that the clock signal CLK for I2C communication and the data signal DATA . WP terminal (7) is write protection. When write voltage of high voltage is applied, write protection function is activated and only read function is performed. When low voltage is applied, read and write function It is possible. The WP terminal 7 is connected to the WP pin 33 of the timing controller 23 and is supplied with the write protection voltage or the low potential voltage of the high potential voltage from the timing controller 23. The VCC terminal 8 is supplied with an input voltage as a power source.

A first pull-up resistor R1 for maintaining a high level of the serial clock line SCL of the EEPROM 13 is connected between the driving power supply VCC and the serial clock line SCL, A second pull-up resistor R2 for maintaining a high level of the serial data line SDA is formed between the data lines SDA.

In order to stabilize the circuit, a third resistor is formed between the WP line and the low potential line GND and a capacitor C is formed between the driving power supply VCC and the low potential line GND.

3 is a flow chart showing how the timing controller controls the write protection function of the memory. Table 1 is a table showing the relationship in which the timing controller 23 provides the output voltage to the memory 25 in accordance with the input signal provided by the timing controller 23. Referring to FIG. 3 and [Table 1], a method for controlling the write protection function of the memory according to the present invention will be described as follows.

Input signal Output voltage Video signal + Power supply voltage (VIN) Write protection voltage Power supply voltage (VIN) Low potential voltage

<Power supply voltage reception: S301, S303>

The input signal determination unit 23-1 of the timing controller 23 detects whether the power supply voltage VIN is supplied from the outside through the connector 22. [

<Judgment of presence or absence of video signal: S305>

If the input signal determining unit 23-1 detects that the power source voltage VIN is provided in step S301, the input signal determining unit 23-1 determines whether the video signal is supplied along with the power source voltage VIN .

<Enable write protection function via write protection voltage output: S307>

If the input signal determination unit 23-1 determines that the video signal is supplied from the outside together with the power supply voltage VIN in step S303, the voltage output unit 23-2 of the timing controller 23 controls the WP pin 31, And outputs the write protection voltage to the memory 25 via the write protection voltage. The WP pin 31 of the timing controller 23 may use a pulse width modulation (PWM) pin formed in the timing controller 23. That is, the timing controller 23 provides a high-potential voltage to the memory 25 that can activate the write protection function of the memory 25 using pulse width modulation. At this time, the timing controller 23 can output the high-level write protection voltage by using the driving power source VCC. As described above, the write protection function is activated by receiving the write protection voltage from the voltage output portion 23-2 of the timing controller 23.

<Disable write protection via low voltage output: S309>

If the input signal determination unit 23-1 determines in step S303 that the video signal is not supplied when the power supply voltage VIN is applied from the outside, the voltage output unit 23-2 outputs the low potential voltage to the memory 25 . The low potential voltage is provided to the write protection terminal 7 of the memory 25, so that the write protection function of the memory 25 is not activated.

As described above, the memory control method according to the present invention activates the write protection function of the memory 25 only in a signal period in which a video signal is provided from the outside. In addition, the present invention does not activate the write protection function in a non-signal period in which a video signal is not supplied from the outside but only a power source voltage is supplied. Therefore, in the present invention, the read operation is possible in the memory 25 when the video signal is not provided. That is, before the product is shipped, the write protection function of the memory 25 can be canceled by supplying only the power supply voltage except the external video signal, so that the data in the memory 25 can be changed or updated easily.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

11: liquid crystal panel 11a: gate driver
11b: Data driver 22: Connector
23: Timing controller 24: DC-DC converter
25: Memory

Claims (5)

A memory for selectively activating write protection; And
And a timing controller for activating a write protection function of the memory during a signal period in which a video signal to be displayed on the liquid crystal panel is input and for deactivating a write protection function of the memory during a no signal period during which the video signal is not inputted, Display device.
The method according to claim 1,
Wherein the memory is an EEPROM including a write protection terminal for activating the write protection function in response to a high potential voltage.
3. The method of claim 2,
The timing controller
And provides the high potential voltage through a pulse width modulation scheme to a write protection terminal of the memory during the signal period.
3. The method of claim 2,
The timing controller
And provides a low potential voltage to the write-protect terminal of the memory during the no signal period.
The method of claim 3,
Wherein the timing controller generates the write protection voltage by using a driving voltage provided through the VCC terminal.

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