KR20150030541A - Liquid crystal display device incuding gate driver - Google Patents

Abstract

A liquid crystal display device is disclosed. More specifically, the present invention relates to a liquid crystal display device including a gate driver, which is capable of discharging the residual charge when a low-temperature polysilicon (LTPS) liquid crystal display device is abnormally powered off while maintaining a narrow bezel by minimizing the number of elements. According to an embodiment of the present invention, a liquid crystal display device drops a common voltage among signals applied to a liquid crystal panel to AVEE voltage potential to discharge the residual charge through a common voltage terminal, when the liquid crystal display device is abnormally powered off, to remove an APO circuit provided in a conventional gate driver to reduce the number of elements of the gate driver, thereby easily implementing a narrow bezel structure.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display (LCD)

The present invention relates to a liquid crystal display (LCD), and more particularly, to a liquid crystal display device which minimizes the number of elements and maintains a narrow bezel while maintaining a residual charge when an abnormal power off of a low temperature polysilicon (LTPS) And a gate driver for discharging the liquid crystal display panel.

2. Description of the Related Art [0002] With the development of information devices such as potable devices such as mobile phones and notebook computers and high-resolution and high-quality images such as HDTVs, flat panel displays Display Device) is increasing. As such flat panel display devices, a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting diode (OLED) have been actively studied. However, And realization of a large area screen, a liquid crystal display (LCD) is in the spotlight at present.

In particular, an active matrix type liquid crystal display device in which a thin film transistor (TFT) is used as a switching element is suitable for displaying dynamic images. In order to control such a switching device, a liquid crystal display device is provided with a gate driver, and in recent years, the gate driver is provided not in a driving IC separate from the liquid crystal panel but in the form of a thin film transistor on a liquid crystal panel.

FIG. 1 is a diagram showing a schematic equivalent circuit of one stage of a gate driver provided in a conventional liquid crystal display device.

Referring to FIG. 1, a conventional gate driving unit 1 includes two OR gates A1 and A2 connected to a first input S and a second input R, and pull-up and pull-down transistors TPU and TPD The first and second auxiliary transistors TCU and TCD may be represented by an RS flip flop 5 connected to the first output terminal Q and the second output terminal Q.

Further, in the conventional gate driver 1, when an abnormal power off occurs in driving the liquid crystal display device, there is an abnormal power off circuit 7 for discharging the electric charge remaining in the liquid crystal panel Respectively.

The abnormal power off indicates a situation in which the power suddenly turns off due to an unexpected occurrence of a battery being disconnected from the device while the mobile device is mounted on the liquid crystal display device. When the abnormal power is turned off, The discharged electric charge is not normally discharged, which causes a deterioration in image quality such as a residual image on the screen or a flicker. In order to solve this problem, an output terminal of the gate driving signal Gout (n) of the gate driving unit 1, and a first output terminal Q and a second output terminal QB are connected to all the gates The first to third APO transistors TA1 to TA3 for transiting the drive signal Gout (n) to a high potential and for shifting the first output terminal Q and the second output terminal QB to the low potential side are connected.

FIG. 2 is a view showing signal waveforms inputted / outputted to / from a liquid crystal display device when the abnormal power is off, and FIG. 3 is a view showing a mode in which one pixel of the liquid crystal panel is discharged according to the signal of FIG.

Referring to FIGS. 2 and 3, when the abnormal power supply is turned off, the conventional liquid crystal display detects that the abnormal power supply is off as the potential of the VDD voltage VDD falls to the GND voltage (GND) The voltages S1 to S2400 of the data lines are connected to the GND voltage at the time of detecting the Abnormal Power-Off and the potential of the MUXs formed in the liquid crystal panel 10 is raised to the gate high voltage VGH, The data lines in the pixels are connected to the data lines already made to have the GND voltage, thereby discharging the charges charged in the panel. The gate start signal Vst and the clock signals CLKs and the like transition to the same potential as the gate low voltage VGL falls and the gate low voltage VGL transits to the GND voltage GND, Vcom) also changes to the GND voltage (GND).

The gate high voltage VGH is applied to all the gate lines GL of the liquid crystal panel 10 so that the switching element T and the mux transistor TMUX of each pixel PX are turned on, The electric charge Vchg charged in the liquid crystal capacitor lc is discharged to the GND voltage GND through the data line DL.

However, as described above, one stage of the conventional gate driver includes the pull-up and pull-down transistors TPU and TPD and the first and second auxiliary transistors TCU and TCD as shown in FIG. 1, The gates A1 and A2 and the flip-flop 5 are composed of ten thin film transistors, and therefore, they include fourteen thin film transistors. Further, since three thin film transistors are further included in the APO circuit 7, each stage of the gate driver is composed of 17 thin film transistors in total.

Accordingly, since the gate driver includes a plurality of thin film transistors, it is difficult to realize a narrow bezel that minimizes the non-display area of the liquid crystal panel according to the current trend of the liquid crystal display device. In addition, it is difficult to secure reliability in the operation of the thin film transistors included in the APO circuit, and it is also difficult to set an accurate operation timing.

The gate high voltage (VGH) for driving the APO circuit consumes a large amount of power as it is supplied to all the stages of the gate driving unit. In the state where the power is disconnected from the outside, the temporary high- The capacity of the means (e.g., capacitor) is limited and the time for maintaining the gate high voltage (VGH) from the abnormal power-off detection point is short, so that the discharge operation may not be performed properly.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a liquid crystal display device capable of efficiently performing discharge driving of a liquid crystal panel while omitting an APO circuit provided in a gate driver for discharging a charge remaining on a liquid crystal panel And to provide a liquid crystal display device including a gate driver.

In order to achieve the above object, a liquid crystal display device according to a preferred embodiment of the present invention includes: a liquid crystal panel in which a plurality of gate wirings and data wirings are crossed and pixels are defined at intersections; A gate driver for applying a gate driving signal to the gate line; A data driver for applying a data signal to the data line; A power supply unit including a common voltage supply unit for generating a plurality of driving voltages corresponding to an external voltage and supplying a common voltage to the liquid crystal panel; And an abnormal power-off detection unit for applying a control signal to the gate driver and the data driver and controlling the common power supply unit to lower the common voltage to a predetermined value or less when an abnormal power- And a timing control section including a circuit.

According to another aspect of the present invention, there is provided a liquid crystal display device, wherein the gate driver further includes an initialization transistor, wherein the initialization signal is applied to the gate of the initialization transistor, And the gate low voltage is applied to the source.

According to the embodiment of the present invention, when the abnormal power is turned off, the potential of the muxes MUXs formed on the liquid crystal panel 10 is raised to the gate high voltage VGH to turn the entire muxes into a turn-on state, GL to apply the GND voltage to the switching elements of each pixel PX and to lower the common voltage among the signals applied to the liquid crystal panel to the AVEE voltage potential so that the switching elements of each pixel PX turn- Thereby discharging the remaining charge through the data line. Thus, other transistors except for one of the APO circuits provided in the conventional gate driver can be omitted. Accordingly, the number of elements of the gate driver can be reduced, and a norrow bezel structure can be easily implemented.

Further, by using less electric power in the discharge driving than in the prior art, there is an effect that the discharge time of the residual electric charge is further extended.

FIG. 1 is a diagram showing a schematic equivalent circuit of one stage of a gate driver provided in a conventional liquid crystal display device.
FIG. 2 is a diagram showing signal waveforms input / output to / from a liquid crystal display device when the abnormal power is off. FIG.
FIG. 3 is a view illustrating a state in which one pixel of the liquid crystal panel is discharged according to the signal of FIG. 2. FIG.
4 is a diagram showing the entire structure of a liquid crystal display device including a gate driver according to an embodiment of the present invention.
5 is an equivalent circuit diagram of one stage of the gate driver according to the embodiment of the present invention.
FIG. 6 is a diagram showing waveforms of a part of signals applied to the liquid crystal display device when the abnormal power is off according to the embodiment of the present invention.
7 is a diagram illustrating a driving mode for one pixel of the liquid crystal panel according to the operation of the gate driver.
8 is an equivalent circuit diagram of one stage of a gate driver of a liquid crystal display according to another embodiment of the present invention.
FIG. 9 is a diagram showing waveforms of some of the signals applied to the liquid crystal display including the gate driver of FIG. 8 when the abnormal power is off.

Hereinafter, a liquid crystal display device including a gate driver according to a preferred embodiment of the present invention will be described with reference to the drawings.

4 is a diagram showing the entire structure of a liquid crystal display device including a gate driver according to an embodiment of the present invention.

4, the liquid crystal display device of the present invention includes a liquid crystal panel 100 in which a plurality of pixels PX are formed to define a display area for displaying an image and a non-display area, And a function of controlling the potentials of the specific voltages supplied to the liquid crystal panel 100 to discharge the remaining charges when the abnormal power-off occurs, in addition to the timing at which the respective drivers and the mux drivers 120, 130, and 140 are controlled, A data driver 130 for supplying a data signal to the pixel PX, and a data driver 130 for supplying a data signal to the pixel PX. The data driver 130 includes a control unit 110, a gate driving unit 120 mounted in the liquid crystal panel 100 and supplying a gate driving signal to the pixel PX, And a mux driver 140 connected to an output terminal of the driver 130 to reduce the number of channels.

In the liquid crystal panel 100, two transparent substrates made of glass or plastic are adhered to each other with a predetermined distance therebetween, and a liquid crystal layer is interposed therebetween. A gate line GL and a plurality of data lines DL are arranged in a matrix in a direction perpendicular to the gate line GL on one substrate of the two substrates and a pixel PX is defined do. A plurality of pixels PX constitute a display region, and at least one thin film transistor T serving as a switching element is formed in each pixel PX. The gate of the thin film transistor T is connected to the gate line GL and is turned on / off by a gate driving signal. The drain is connected to the data line DL and the source is connected to the pixel electrode. In addition, the pixel electrode forms a common electrode and a liquid crystal capacitor (lc) facing each other, and the electric charge corresponding to the data signal applied through the data line DL is charged in the liquid crystal capacitor lc, And displays an image. Although not shown, the liquid crystal capacitor lc may further be connected to a storage capacitor (not shown) to stably maintain the charged voltage level until the next frame of the charged data signal.

A non-display region is defined at the outside of the display region of the liquid crystal panel 100 in which an image is not displayed and the gate driver 120, the mux driver 140, and various wirings (not shown) are extended.

The timing controller 110 receives an externally applied video signal and a predetermined timing signal and outputs an aligned video signal RGB and a gate control signal GCS, a data control signal DCS, and a mux control signal MCS And supplies them to the driving units 120 and 130, respectively.

The timing controller 110 supplies not only the gate control signal GCS for controlling the gate driver 120 but also one or more clock signals CLK for driving the gate driver 120.

Although not shown, the timing controller 110 is designed to receive image-related signals and timing signals output from the external system via a predetermined interface, without noise, at a high speed. Such interfaces include a low voltage differential signal (LVDS) method or a transistor-transistor logic (TTL) interface method.

A gate driver 120 including a plurality of thin film transistors is formed on a non-display region of at least one side of the liquid crystal panel 100. An output end of the gate driver 120 is connected to a plurality of gate lines GL formed in the display region A / And are electrically connected.

The gate driver 120 applies a gate driving signal to the gate line GL arranged on the liquid crystal panel 100 in response to the gate control signal GCS applied from the timing controller 110, The data signal of the analog waveform supplied from the data driver 130 is supplied to the liquid crystal capacitor LC connected to each thin film transistor T .

The gate control signal GCS includes a gate start pulse, a gate shift clock, and a gate output enable signal.

The gate driver 120 receives the gate high voltage VGH and the gate low voltage VGL that define the high potential and the low potential of the gate driving signal from the power supply unit 150, A voltage corresponding to the gate high voltage VGH sequentially through the gate wiring GL for each one horizontal period 1H and outputs the gate low voltage VGL for the remaining period. The gate high voltage VGH between the gate lines GL is set so as not to overlap with each other. However, according to the trend that the liquid crystal panel 100 realizes a high resolution image and is formed in a large area, The supply time of each gate high voltage VGH may be adjusted so as to prevent malfunction due to a shortage of the gate high voltage VGH.

The data driver 130 converts the aligned image signal RGB input according to the data control signal DCS input from the timing controller 110 into an analog data signal using the reference voltage. The data signals are latched by pixels on one horizontal line, and are simultaneously output to the liquid crystal panel 100 through all the data lines DL corresponding to the gate driving signals. At this time, the data driver 130 divides data signals of two to three data lines (DL) for one channel during one horizontal period (1H), and outputs the data signals by overlapping .

The data control signal DCS includes a source start pulse SSP, a source shift clock SSC and a source output enable SOE, a polarity reversal signal POL ).

The mux driver 140 may alternately apply two or three data lines DL of the display panel 100 to one channel CH of the data driver 130 according to the mux control signal MCS And performs a connection function. For this, the mux driver 140 may be formed of a plurality of thin film transistors (not shown) distributed in one channel CH. The mux driver 140 may be formed in the non-display region of the liquid crystal panel 100, such as the gate driver 120.

Although not shown, the timing controller 110 includes a control circuit (not shown) for selectively turning on / off the thin film transistors included in the mux driver 140, which will be described later. May be implemented as a 1x2 demultiplexer (1x2 demultiplexer) or a 1x3 demultiplexer that outputs data signals between two or three data lines DL so as not to overlap each other.

The power supply unit 150 generates a plurality of voltages for driving the liquid crystal display device using power supply voltages input from an external power supply (not shown). Basically, the power supply unit 150 receives the VDD voltage (VDD), the AVDD voltage (AVDD), and the AVEE voltage (AVEE) and generates a plurality of voltages based on the received voltages. The gate high voltage VGH and the gate low voltage VGL defining the potential of the liquid crystal panel 100 and the common voltage Vcom applied to the common electrode of the liquid crystal panel 100 are generated. The power supply unit 150 generates a gamma voltage Vgamma for converting the digital image signal into an analog form and supplies the gamma voltage Vgamma to the data driver 140. Here, the highest potential and the lowest potential of the gamma voltage Vgamma can be determined as AVDD voltage AVDD and AVEE voltage AVEE, respectively.

Here, the VDD voltage is a reference for generating the common voltage Vcom, and the AVDD voltage AVDD is a reference for determining the highest potential of the gate high voltage VGH and the gamma voltage Vgamma. The AVEE voltage AVEE is a reference for determining the gate low voltage VGL and the lowest potential of the gamma voltage.

The power supply unit 150 may be implemented not in a separate power supply circuit but in a timing controller 110 or a data driver 130. The common power supply unit may include a common power supply unit (not shown) .

In particular, the power supply unit 150 according to the embodiment of the present invention receives the detection signal apo_det for the abnormal power-off from the timing control unit 110 when the abnormal power-off occurs, The switching element T can be turned on even if the gate high voltage VGH is not applied to each switching element T of the liquid crystal panel 100 by lowering the common voltage Vcom to a predetermined potential or lower, So that the source voltage Vgs is secured.

Here, the common voltage Vcom is controlled to be at least equal to or lower than the AVEE voltage AVEE.

That is, in the liquid crystal display according to the embodiment of the present invention, when the abnormal power is off, the ground voltage is applied to the gate of the switching element T, and at least the AVEE voltage By applying the same or lower voltage, the residual charge can be discharged through the data line DL as the gate-source voltage Vgs that maintains the turn-on state of the switching element T is applied.

Therefore, when a plurality of thin film transistors (TA1, TA2, and TA3 in FIG. 1) provided in the gate driver 120 are omitted to turn on all the switching elements T when the abnormal power is turned off, the gate driver 120 ) Is reduced and the narrow bezel can be realized easily.

Hereinafter, a gate driver included in a liquid crystal display according to an embodiment of the present invention will be described with reference to the drawings. In the following description, n indicates a signal corresponding to the current stage, and n-1 and n + 1 indicate signals corresponding to the previous single stage and the next single stage, respectively.

5 is an equivalent circuit diagram of one stage of the gate driver according to the embodiment of the present invention.

5, the gate driver of the present invention includes a plurality of stages, and each stage includes a forward transistor Tf and a reverse transistor Tr that determine the output direction of the gate driving signal Gout (n) Up transistor TPU and the pull-down transistor TPD in accordance with the n-th clock signal CLK (n) and the next stage output signal NEXT (n + 1) Up transistors TPU and TPU for determining the potentials of the capacitors CF, CQ and CQB and the gate driving signal Gout (n), and a plurality of first to seventh transistors T1 to T7 for controlling the capacitors CF, A down transistor TPD, and a first output transistor TO1 and a second output transistor TO2 that determine the output of the previous single stage.

The forward transistor Tf and the reverse transistor Tr are respectively supplied with the previous single stage output signal NEXT (n-1) and the next stage output signal NEXT (n + 1) The Q node Q is charged to a high potential by applying the ST signal ST to the first and second transistors T1 and T2 corresponding to the reverse signal REV.

Accordingly, when the gate driver is set to be driven in the forward direction, that is, in the downward direction of the liquid crystal panel, the forward signal FWD of high potential is applied and the gate driver is driven in the upward direction from the bottom of the liquid crystal panel in the reverse direction The high-level reverse signal REV is applied.

The first transistor T1 is supplied with the ST signal ST at its gate, the gate high voltage VGH at its drain, and its source connected to the drain of the fifth transistor T5. Thus, when the ST signal ST of high potential is applied, the Q node Q is charged to a high potential through the fifth transistor T5.

The second transistor T2 has a gate to which the ST signal ST is applied, a drain connected to the gate of the sixth transistor T6 and a gate low voltage VGL to the source thereof. Thus, when the high-potential ST signal ST is applied, the sixth transistor T6 is turned off.

The third transistor T3 is supplied with the ST signal ST at its gate, the drain connected to the QB node QB and the gate low voltage VGL at its source. Thus, the QB node QB discharges low when the high-potential ST signal ST is applied.

The fourth transistor T4 has a diode connection structure when the same nth clock signal CLK (n) is applied to the gate and the drain thereof. The source thereof is connected to the gate of the sixth transistor T6, (T2). Accordingly, when the high-level n-th clock signal CLK (n) is applied to the corresponding stage, the sixth transistor is turned on until the second transistor T2 is turned on, T6 are maintained in the turn-on state. Here, the potential of the n th clock signal CLK (n) at the high potential can be set equal to the gate high voltage VGH.

The gate of the fifth transistor T5 is supplied with a gate high voltage VGH, the drain thereof is connected to the source of the first transistor T1, and the source of the Q transistor Q is connected to the source thereof. Accordingly, the fifth transistor T5 is always turned on, and charges the Q node Q with a voltage applied through the first transistor T1.

The sixth transistor T6 has a gate connected between the drain of the second transistor T2 and the source of the fourth transistor T4 and an n + 1-th clock signal CLK (n + 1) is applied to the drain thereof And the source is connected to the eighth transistor T8. The sixth transistor T6 is turned on when the second transistor T2 is turned off and the n + 1 th clock signal CLK (n + 1) is applied to the eighth transistor T8. .

The seventh transistor T7 has a gate connected to the QB node QB, a drain connected to the source of the first transistor T1, and a gate low voltage VGL applied to the source. Thus, the seventh transistor T7 functions to discharge the Q node Q when the QB node QB is charged to a high potential.

The eighth transistor T8 is connected to the gate of the sixth transistor T6 and the source of the eighth transistor T8 is connected to the QB node QB. do. Accordingly, when the n + 1th clock signal CLK (n + 1) of high potential is applied, the QB node QB is charged with the voltage applied through the sixth transistor T6. Since the voltage applied from the sixth transistor T6 is a voltage obtained by subtracting the threshold voltage Vth from the (n + 1) th clock signal CLK (n + 1), the eighth transistor T8 is substantially the same as the diode .

The first output transistor TO1 has a gate connected to the Q node Q and an nth clock signal CLK (n) applied to the drain and a source connected to the output signal NEXT (n) . Further, the second output transistor T02 has a gate connected to the QB node QB, a drain connected to the output stage NEXT (n) of the next stage, and a gate low voltage VGL applied to the source . Thus, the first and second output transistors TO1 and TO2 are connected to the Q node Q and the QB node QB, respectively, because the potential of the n th clock signal CLK (n) is equal to the gate high voltage VGH. (NEXT (n)) corresponding to the gate high voltage (VGH) and the gate low voltage (VGL) alternately in accordance with the potential of the gate signal line This output signal NEXT (n) is used as the start signal of the next stage.

The pull-up transistor TPU has a gate connected to the Q node Q, a drain connected to the n th clock signal CLK (n), and a source connected to the gate driving signal Gout (n) . The pull-down output transistor TPD has a gate connected to the QB node QB, a drain connected to the gate driving signal Gout (n), and a gate low voltage VGL applied to the source. Thus, the pull-up transistor TPD and the pull-down transistor TPD are alternately turned on and off according to the potentials of the Q node QB and the QB node QB, And outputs the driving signal Gout (n).

Hereinafter, the method of driving the gate driver of the present invention and the residual charge discharge pattern in the liquid crystal panel accordingly when the abnormal power is off will be described with reference to the drawings.

FIG. 6 is a view showing a waveform of a part of a signal applied to the liquid crystal display device when the abnormal power is off according to the embodiment of the present invention, and FIG. 7 is a diagram illustrating a driving mode for one pixel of the liquid crystal panel according to the operation of the gate driver FIG.

Referring to FIGS. 6 and 7, the VDD voltage VDD of about 0 V to 5.0 V or about -0 V to -5.0 V is applied to the liquid crystal display device during normal driving, and a common voltage of about 0 V to about -0.5 V (VCOM) is constantly applied to the liquid crystal panel.

The data signals S1 to S2400 of positive and negative voltages are output in accordance with the polarities of the corresponding wirings (in the case of 800 channels), and the control signals MUXs of the mux driver are also supplied to the respective data wirings So that the high voltage and the low voltage swing. Also, the start signal (VST) of the gate driver is also output at a high voltage once per frame at the start time of the gate wiring, and the clock signal (CLK) is also output in the form of swinging appropriately for each stage of the gate driver.

When the liquid crystal display device is disconnected from the power supply device arbitrarily during normal driving or when the battery is disconnected, the potential of the VDD voltage (VDD) falls to the ground voltage (GND) potential from that point of time. The power-off control circuit detects that the potential of the VDD voltage (VDD) falls, and detects that the abnormal power is off (Detecting Abnormal Power-off).

When the abnormal power supply is turned off, the potential of the signal applied from the data wiring changes to the ground voltage (GND), and the control signal (MUXs) of the mux driver is outputted to the gate high voltage (VGH) To turn on all the mux transistors (TMUX). Then, it is gradually discharged to the ground voltage (GND). In addition, the start signal VST and the clock signal CLK of the gate driver are lowered to the gate low voltage VGL and are gradually discharged to the ground voltage GND.

At this time, the abnormal power-off control circuit controls the potential of the common voltage VCOM to the potential of the AVEE voltage AVEE at the time of detection and controls the gate low voltage VGL to the ground voltage (GND) potential.

That is, the voltage applied to the gate of the switching element T of each pixel PX of the liquid crystal panel is controlled to 0 V, and the voltage applied to the common electrode is controlled to -5 V to lower the potential of the liquid crystal capacitor lc Turns on the switching element T to discharge the residual charge in the source direction.

Accordingly, the liquid crystal display device of the present invention does not have a separate APO circuit in the gate driver and can discharge the residual charge by lowering the common voltage potential of the liquid crystal panel.

Meanwhile, in the gate driver of the liquid crystal display according to the above-described embodiment, the stage during which the high-potential gate driving signal is currently being output is shifted to the ground voltage (GND) because the Q- Malfunction may occur. Hereinafter, another embodiment of the present invention in which the above problems are solved will be described with reference to the drawings.

8 is a diagram showing an equivalent circuit diagram of one stage of a gate driver of a liquid crystal display according to another embodiment of the present invention, and FIG. 9 is a circuit diagram of a liquid crystal display device including the gate driver of FIG. Fig. 8 is a diagram showing a waveform of a part of an applied signal. Fig. In the following description, the same parts as the above-described embodiments will be schematically described.

8 and 9, the gate driver according to another embodiment of the present invention includes a forward transistor Tf and a reverse transistor Tr for determining the output direction of the gate driving signal Gout (n) Up transistor TPU and the pull-down transistor TPD in accordance with the n-th clock signal CLK (n) and the next stage output signal NEXT (n + 1) An initialization transistor Tinit for discharging the Q node Q in accordance with the initialization signal Init and a gate for resetting the gate of the Q transistor Q according to the initialization signal Init, A pull-up transistor TPU and a pull-down transistor TPD for determining the potential of the driving signal Gout (n), a first output transistor TO1 for determining the output of the previous single stage, (TO2).

Here, the first transistor Tf and the reverse transistor Tr, the first through eighth thin film transistors T1 through T8, the pull-up transistor TPU and the pull-down transistor TPD, The connection structure and function of the transistor TO1 and the second output transistor TO2 are the same as those in the above embodiment. However, there is a difference in that an initialization transistor Tinit is provided between the Q node Q and the gate low voltage VGL to lower the potential of the Q node Q when the abnormal power is off.

In the initialization transistor Tinit, an initialization signal Init is applied to a gate, a drain is connected to a Q node Q, and a gate low voltage VGL is applied to a source. Here, the initializing signal (Init) may be applied only for a certain period of time (one gate line (1 LINE) or several gate lines (2 to 4 Lines)) when the abnormal power-off control circuit detects that the abnormal power- 10 LINE) is output) to the potential of the gate high voltage (VGH). The initialization transistor Tinit is turned on by the initialization signal Init to turn the potential of the Q node Q of the stage outputting the gate drive signal of the current high potential to each stage of the gate driver to the gate low voltage VGL ) To discharge.

Therefore, the gate driver of the liquid crystal display according to another embodiment of the present invention has an advantage that it is driven more stably because the Q-node Q of all the stages is discharged in the abnormal power-off state.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Accordingly, the invention is not to be determined by the embodiments described, but should be determined by equivalents to the claims and the appended claims.

100: liquid crystal panel 110: timing controller
120: Gate driver 130: Data driver
140: MUX driving unit 150: Voltage driving unit
GL: gate wiring DL: data wiring
CH: Channel GCS: Gate control signal
DCS: Data control signal MCS: Mux control signal
RGB: video signal Vgamma: gamma voltage
Vcom: common voltage T: thin film transistor

Claims (13)

A liquid crystal panel in which a plurality of gate wirings and data wirings are cross-formed and pixels are defined at intersections;
A gate driver for applying a gate driving signal to the gate line;
A data driver for applying a data signal to the data line;
A power supply unit including a common voltage supply unit for generating a plurality of driving voltages corresponding to an external voltage and supplying a common voltage to the liquid crystal panel; And
An abnormal power-off detection circuit for applying a control signal to the gate driver and the data driver and controlling the common power supply to lower the common voltage to a predetermined value or less when an abnormal power- And a timing controller
And the liquid crystal display device. The method according to claim 1,
The driving voltage may be,
A VDD voltage as a reference for generating the common voltage;
An AVDD voltage serving as a reference for generating a positive potential of the gamma voltage;
The AVEE voltage which is a reference for generating the negative potential of the gamma voltage
And the liquid crystal display device. 3. The method of claim 2,
Wherein the abnormal power-on detection circuit comprises:
And turns the common voltage to the AVEE voltage potential when the abnormal power source is turned off. 3. The method of claim 2,
Wherein the abnormal power-on detection circuit comprises:
Off state in response to a potential variation of the VDD voltage. 3. The method of claim 2,
Wherein the gate driver comprises:
A plurality of stages each including a Q node and a QB node,
In either stage,
A first transistor having a gate to which an ST signal is applied and a gate to which a gate high voltage is applied;
A second transistor to which the ST signal is applied to a gate and a gate low voltage is applied to a source;
A third transistor to which the ST signal is applied to the gate, a drain is connected to the QB node, and a gate low voltage is applied to the source;
A fourth transistor having an nth (n is a natural number) clock signal applied to a gate and a drain, and a source connected to a drain of the second transistor;
A fifth transistor having a gate to which a high voltage is applied, a drain to which the source of the first transistor is connected, and a source to which the Q node is connected;
A sixth transistor having a gate connected between a drain of the second transistor and a source of the fourth transistor, and a drain of which is supplied with an (n + 1) th clock signal;
A seventh transistor having a gate connected to the QB node, a drain connected to the source of the first transistor, and a gate low voltage applied to the source;
An eighth transistor having a gate to which the (n + 1) th clock signal is applied, a drain connected to the source of the sixth transistor, and a source connected to the QB node;
A first output transistor having a gate connected to the Q node, a drain connected to the n th clock signal, and a source connected to the next stage;
A second output transistor having a gate connected to the QB node, a drain connected to the next stage, and a gate low voltage applied to the source;
A pull-up transistor having a gate connected to the Q node, a drain connected to the n th clock signal, and a gate driving signal output through a source; And
A gate connected to the QB node, a gate driving signal output through a drain, and a gate low voltage applied to a source,
And the liquid crystal display device. 6. The method of claim 5,
Wherein the gate driver comprises:
A forward transistor which receives the output signal of the previous single stage and outputs the ST signal in response to the forward signal to drive each stage in the forward direction; And
A second stage stage in which the output signal of the next stage is applied and the ST signal is output in response to the reverse signal,
The liquid crystal display device further comprising: 6. The method of claim 5,
An initialization signal is applied to the gate, a drain is connected to the Q node, and an initialization transistor
The liquid crystal display device further comprising: 8. The method according to any one of claims 5 and 7,
Wherein the nth clock signal is shifted to a gate low voltage potential when an abnormal power source is turned off. 8. The method according to any one of claims 5 and 7,
Wherein the gate low voltage is shifted to a ground voltage potential when an abnormal power supply is turned off. 8. The method according to any one of claims 5 and 7,
Wherein the initialization signal is transitioned to the gate high voltage potential during the driving period of the one or two gate wirings when the abnormal power supply is off. The method according to claim 1,
Wherein the data line is transited to a ground voltage potential at an abnormal power-off state. The method according to claim 1,
Wherein the data driver includes a plurality of channels having a smaller number than the data lines,
A plurality of data lines, each of which is connected between the channel and the data line,
The liquid crystal display device further comprising: 13. The method of claim 12,
Wherein the abnormal power-on detection circuit comprises:
Wherein when the abnormal power-off occurs, the control signal of the mux portion is changed to the gate high voltage potential.

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