KR20140146633A - Back contact solar cells using aluminum-based alloy metallization - Google Patents

Abstract

A photovoltaic rear-facing solar cell structure and method having multi-level metallization with at least one aluminum-silicon alloy metallization layer is disclosed.

Description

TECHNICAL FIELD [0001] The present invention relates to a back contact solar cell using an aluminum-based alloy metallization. BACKGROUND OF THE INVENTION [

Cross reference of related application

This application claims the benefit of U.S. Provisional Application No. 61 / 617,023, filed March 28, 2012, and 61 / 725,981, filed November 13, 2012, the entire contents of which are incorporated herein by reference.

This application claims the benefit of US Provisional Application No. 13 / 204,626, filed on August 5, 2011, and 13 / 731,112, filed December 31, 2012, the entire contents of which are incorporated herein by reference .

The present invention relates generally to photovoltaic (PV) cells, and more specifically to back-contacting solar cells.

High conversion efficiency, along with low manufacturing costs, is a key requirement to accelerate the worldwide growth of photovoltaic (PV) systems as an alternative to renewable energy solutions and carbon-based fuels. Equally important is increasing solar cell energy yields for high energy harvesting from PV modules. Over the years, the technology of standard crystal silicon solar cells has used silicon substrates 150-200 micrometers thick, which often serve as a major contributor to silicon solar PV cells and modules at high cost and relatively high cost. The cost of standard silicon wafers formed by wire sawing from ingots or cast bricks is relatively high because of the expensive, energy-intensive multiple fabrication steps (e.g., polysilicon, ingot, wire saw wafering) required for manufacturing such wafers .

The second most expensive material in a number of current standard over-contact crystalline silicon solar cell technologies is silver, which is particularly expensive because it is a precious metal. The silver paste is often used to contact the front n-type emitter of a p-type base solar cell.

In addition, in highly efficient interfaced back-to-back / backside bonded (IBC) crystal solar cells, metallization is often relatively expensive, such as electro-chemical plating (relatively thick, approximately 30-60 microns copper plating deposition) And lithography / screen printing wet-etch patterning. Manufacturing process tools required for these metallization processing sequences (including vacuum processing: physical vapor deposition, patterning, etching, and plating) have a high capital ratio and chemical plating / patterning processes use sacrificial consumables (e.g., resist patterning) And produce large output of hazardous waste (e.g., during copper plating). In addition, the relatively large amount of copper used in thick copper metallization in IBC can further contribute to the overall battery and module manufacturing costs. Thus, in order to enable low cost solar cells, lower cost metallization materials and processes are needed.

Therefore, there is an increasing need for improved back-contacting solar cell constructions and fabrication methods. A method, structure, for manufacturing an photovoltaic back-contacting solar cell having an aluminum-silicon alloy layer metallization, according to the disclosed subject matter, is disclosed, which relates to the cost and manufacturing disadvantages associated with the previously- Substantially eliminates or reduces < / RTI >

According to an aspect of the disclosed subject matter, a method of forming an interdigitated back-contacting solar cell structure on a crystalline semiconductor absorber layer is disclosed. In one embodiment, the passivation and anti-reflective coating is formed on the front side of the semiconductor absorber and comprises a thicker lightly doped n-type base layer and a thinner heavily doped p-type emitter And a thinner heavily doped p-type emitter junction is formed on the rear side of the semiconductor absorber. The backside structure is formed on the thicker lightly doped n-type base layer and the thinner heavily doped p-type emitter junction on the back side of the semiconductor absorber by the following steps: passivation structure with base and emitter contact openings and patterning Forming a rear side dielectric dopant source; Contacting the base and emitter regions through the base and emitter contact openings and contacting the base and emitter regions through the base and emitter contact openings through a passivation structure and a plurality of directly printed silicon containing aluminum fingers directly over the patterned rear dielectric dopant source Forming a meshed base and emitter metallization layer; Forming an electrically insulated backplane layer including a plurality of via holes landing on the first intertwined base and the emitter metallization layer, the backplane layer including a first patterned Bonded to the meshed base and the emitter metallization layer and the surface passivation structure and to the patterned rear dielectric dopant source; And forming a second interlocked base and emitter metallization layer on the electrically insulated backplane layer, the second interlocked base comprising a patterned conductor aligned substantially perpendicularly to the first interlocked base and emitter metallization layer .

According to another aspect of the disclosed subject matter, a method of forming a back-contacting solar cell structure meshed on a crystalline semiconductor absorber layer is disclosed. In one embodiment, a back-contacting solar cell is disclosed that includes a multi-level metallization structure. The multi-level metallization structure has a first aluminum-silicon alloy layer positioned on a backside of a semiconductor solar cell substrate, the aluminum-silicon alloy layer having a base region on the solar cell substrate and a base electrode And an emitter electrode. Wherein the backplane layer is drilled through the backplane layer and is contacted to the first metal layer without being punched through the first aluminum-silicon alloy layer, Silicon alloy layer in the first aluminum-silicon alloy layer at an optional location to form an emitter contact. A second layer of electrically insulating metal is placed on the electrical contact and electrically insulating backplane layer through the via hole to the first aluminum silicon alloy layer.

In addition, according to another aspect of the subject matter disclosed above, aluminum-silicon alloy particles in the form of a mixture of substantially flake-like particles and spherical particles to form an engaging rear contact base and an emitter contact metallization structure Containing aluminum alloy is disclosed.

These and other advantages of the disclosed subject matter as well as additional novel features will become apparent from the description provided herein. The purpose of this summary is not to provide a comprehensive description of the subject, but to provide a brief overview of some of the subject's features. Other systems, methods, features and advantages provided herein will become apparent to those skilled in the art upon review of the following drawings and detailed description. All the additional systems, methods, features, and advantages contained within this description are within the scope of the claims.

The features, characteristics, and advantages of the disclosed subject matter will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference numerals represent like features:
1 is a cross-sectional view of an IBC thin silicon solar cell having a dielectric backplane support and Al (Si) paste;
Figure 2 is a cross-sectional view of an IBC silicon solar cell having a dielectric backplane support and Al paste only on Al (Si) paste;
Figure 3 is a top view of an Al (Si) paste emitter and only an Al paste pad printed on a base separated finger;
Figure 4 is a top view of backplane metal emitter and base separated fingers on a dielectric backplane;
Figures 5A and 5B are schematics showing a back-side view of a dielectric backplane layer with metal first layer (M1) and vias, respectively;
Fig. 6 is a schematic showing a rear view of the metal two-layer (M2);
Figure 7 has two process flow schematic options for Al (Si) paste printing and annealing;
8 is a process flow diagram for fabricating thin silicon solar cells by laser splitting and lift-off separation of a thin silicon layer from a reusable silicon support wafer;
9 is a process flow diagram for fabricating thin silicon solar cells by laser splitting and lift-off separation of a thin epitaxial silicon layer from a reusable silicon support wafer;
10 is a process flow diagram for fabricating thin silicon solar cells by laser splitting and lift-off separation of an epitaxial silicon layer from a porous silicon layer;
11 is a process flow diagram for fabricating thin silicon solar cells by mechanical lift-off separation of a thin epitaxial silicon layer from a sacrificial porous silicon bilayer on a reusable silicon support wafer;
12 is a process flow diagram for fabricating a thin silicon solar cell by front side silicon etching and texturing of a silicon wafer;
Figure 13 is a process flow option for backplane metallization;
Figure 14 is a table summarization of the battery back side process flow options for each process flow option and optional emitter, the number is represented by the total number of APCVD tools, the number of laser tools for oxide removal, and the number of prints on the back side of the cell ;
15 illustrates the battery rear process flow option 130A. A schematic of a process flow of an Ex-Situ Emitter with APCVD Boron Oxide and Abutted Junction using adjacent junctions and APCVD boron oxides;
FIG. 16 illustrates a battery rear process flow option 130B. A schematic flow diagram of an X-ray diffuser using adjacent junctions and APCVD boron oxide;
FIG. 17 illustrates the battery rear process flow option 130C. A schematic flow diagram of an X-ray diffuser using adjacent junctions and APCVD boron oxide;
18 illustrates the battery rear process flow option 130D. A schematic flow diagram of an X-ray diffuser using adjacent junctions and APCVD boron oxide;
19 illustrates the battery rear process flow option 130E. A schematic flow diagram of an X-ray diffuser using adjacent junctions and APCVD boron oxide;
20 shows a battery rear process flow option 130F. A schematic flow diagram of an X-ray diffuser using adjacent junctions and APCVD boron oxide;
FIG. 21 illustrates a battery rear process flow option 130G. A schematic flow diagram of an X-ray diffuser using adjacent junctions and APCVD boron oxide;
FIG. 22 illustrates a battery rear process flow option 130H. A schematic flow diagram of an X-ray diffuser using adjacent junctions and APCVD boron oxide;
23 shows the battery rear process flow option 131A. APCVD Boron Oxide and Isolated Junction by APCVD Undoped Oxide (APCVD) using an APCVD undoped oxide and an APCVD boron oxide;
FIG. 24 illustrates a battery rear process flow option 131B. APCVD is a process flow diagram of an X-situ emitter using bonded oxide separated by undoped oxide and APCVD boron oxide;
25 illustrates the battery rear process flow option 131C. APCVD is a process flow diagram of an X-situ emitter using bonded oxide separated by undoped oxide and APCVD boron oxide;
FIG. 26 shows the battery rear process flow option 131D. APCVD is a process flow diagram of an X-situ emitter using bonded oxide separated by undoped oxide and APCVD boron oxide;
27 illustrates the battery rear process flow option 132A. A schematic of a process flow of an Ex-Situ Emitter with APCVD Boron Oxide and Isolated Junction by Printed USG using junction separated by printed USG and APCVD boron oxide;
28 illustrates the battery rear process flow option 132B. A process flow diagram of an X-ray diffractor using junctions separated by printed USG and APCVD boron oxide;
FIG. 29 illustrates a battery rear process flow option 132C. A process flow diagram of an X-ray diffractor using junctions separated by printed USG and APCVD boron oxide;
30 shows the battery rear process flow option 132D. A process flow diagram of an X-ray diffractor using junctions separated by printed USG and APCVD boron oxide;
FIG. 31 illustrates the battery rear process flow option 132E. A process flow diagram of an X-ray diffractor using junctions separated by printed USG and APCVD boron oxide;
32 illustrates the battery rear process flow option 132F. A process flow diagram of an X-ray diffractor using junctions separated by printed USG and APCVD boron oxide;
33 illustrates the battery rear process flow option 132G. A process flow diagram of an X-ray diffractor using junctions separated by printed USG and APCVD boron oxide;
34 shows the battery rear process flow option 132H. A process flow diagram of an X-ray diffractor using junctions separated by printed USG and APCVD boron oxide;
FIG. 35 shows the battery rear process flow option 133A. A process flow diagram of an In-Situ Emitter with a Boron-Doped Epi and an Isolated Junction by Laser Si Ablation using a junction separated by laser Si removal and a boron doped Epi;
36 shows the battery rear process flow option 133B. A process flow diagram of an in-situ emitter using a junction separated by laser Si removal and a boron doped epi (Epi);
37 shows the battery rear process flow option 133C. A process flow diagram of an in-situ emitter using a junction separated by laser Si removal and a boron doped epi (Epi).

The following description is not meant to be taken in a limiting sense, but rather to illustrate the general principles of the invention. The scope of the invention should be determined with reference to the claims. Embodiments of the present invention are illustrated in the figures, wherein like numerals are used to refer to like and corresponding parts in the various figures.

Significantly, the exemplary process flows, materials, and dimensions disclosed in connection with specific embodiments are those generally used when a solar cell is formed and devised according to the disclosed subject matter, and are provided as detailed in the specific embodiments. Those skilled in the art will recognize that the disclosed process flow and one side of the structure can be combined and / or added and removed in many different ways to fabricate solar cells according to the disclosed subject matter.

Further, although the present invention is described with reference to specific embodiments such as back contact solar cells using a single layer metallization layer of a disclosed material and a monocrystalline silicon substrate having a thickness in the range of 10-200 microns, those skilled in the art will appreciate that other semiconductor materials (E.g., gallium arsenide, germanium, polycrystalline silicon, etc.), metallization layers comprising metallization stacks, techniques, and / or the principles set forth in the examples.

Often, aluminum pastes used in industry standard front contact solar cell designs can be integrated directly to fabricate high efficiency IBC solar cells. General industry standard aluminum pastes are designed to be fired, or annealed, at high temperatures in a short time to produce a deep diffusion of aluminum into the silicon. In a standard solar cell having a p-type crystalline silicon absorber, deep diffused aluminum can provide a desirable back surface field. In n-type IBC solar cells, standard aluminum paste and fire annealing cause deterioration of battery efficiency or severe short circuit.

The present invention provides a process and a solution for manufacturing a high efficiency n-type IBC solar cell having an aluminum based paste / ink. Annealing process options with aluminum alloy paste / ink with silicone composition and battery integrated process flow options are disclosed to enable high efficiency solar cells and to minimize diffusion and spiking into silicon.

In addition, a manufacturing method combining a thin crystal silicon substrate with a simpler process and an aluminum-based metallization can significantly reduce the cost of a crystalline silicon solar cell. In addition, aluminum is the most common metal in Earth's crust and is a relatively inexpensive metal compared to silver or copper. The high efficiency battery structures and process flows that are formed with the simpler, lower cost method and which are provided with the backside IBC structures described herein reduce the processing cost (and silicon thickness in some instances) in the solar cell manufacturing process, Crystal silicon solar cells and modules. ≪ Desc / Clms Page number 2 >

The present invention relates to a method and apparatus for producing contact metallization on, for example, screen-printable aluminum-based alloy pastes, more particularly aluminum-silicon Al (Si) alloys, to form contact metallizations on emitter and base contacts and interfaced back- Various structures and manufacturing methods of a high-efficiency thin-type silicon solar cell using a paste are disclosed and described. An embodiment provides a monocrystalline silicon solar cell having an n-type base absorber and a p-type back emitter junction. The process requires a heavily doped p-type doped region (covering a relatively small portion of the emitter region) under the emitter contact to achieve a higher efficiency and an emitter junction region with a lighter p-type Lt; RTI ID = 0.0 > region). ≪ / RTI > All of the processes described herein may be compatible with producing a crystalline silicon absorber having a thickness as low as about 1 micrometer and a thickness as high as about 100 micrometers, which can be achieved using a reusable silicon support wafer and / or a laminated dielectric support Backplane structure (e.g., a flexible backplane). The final solar cell silicon absorbing layer can be splitted directly from the silicon supporting wafer by laser machining. Alternatively, the thin silicon absorber may be an epitaxial layer that is deposited thereon and then mechanically separated from the sacrificial porous silicon layer formed on the silicon support wafer and divided using a mechanical isolation / lift-off process. Alternatively, the structures, materials, and processes disclosed herein may be fabricated using crystalline wafers formed by wire sawing from single crystal ingots or cast quasi-mono bricks. Can be used on a battery. In addition to the first-level aluminum-alloy based printed paste metallization (metal 1 or M1) formed on the solar cell (on-cell), an electrically insulated backplane, such as a second layer monolithic metallization a low cost process option for monolithic metallization (Metal 2 or M2) is provided.

In addition, the exemplary fabrication methods and structures described herein are for producing high efficiency single crystal silicon solar cells having a silicon absorber thickness in the range of about 1 micron to about 100 microns (microns), although the embodiments and methods disclosed herein Can be used in solar cells using thicker absorbers based on starting silicon wafers made from CZ ingots or cast bricks. In many instances, the disclosed solar cell has a p-type emitter and an n-type base formed on the back side of the cell (in an IBC cell design). Since electrical contact to the emitter and base is made on the back side of the cell, the front side has no electrical contact and there is no optical shading. A thin silicon cell can be supported at any time during the fabrication process by a thick reusable silicon support wafer and / or a laminated dielectric backplane on or from it. In the process flow option using a reusable silicon support wafer, the solar cell backside machining can be completed prior to separation of the thin silicon absorbing layer from the silicon support wafer. Significantly, the methods and structures disclosed herein can be applied to solar cells manufactured using standard starting silicon wafers (and without the use of any reusable template).

Process flow alternatives and variations for fabricating and patterning IBC metallization layers and passivation and emitter junctions on the back side of solar cells are also provided. The described process flow variants include a printable aluminum based metallization, such as an aluminum-silicon Al (Si) alloy paste, to make electrical contact to the n-type base and p-type emitters and to form an on- use. Embodiments of the described process flow may be used to achieve higher cell efficiency by providing a relatively heavily doped p-type doped silicon region under the emitter contact (covering a relatively smaller portion of the emitter region) Lt; RTI ID = 0.0 > lighter < / RTI > doped emitter.

Process flow deformation is described to produce abutted junctions or separate junctions on the back side of the cell. Adjacent junctions have a sudden change in doping that occurs across a small void region between a p-type emitter and a heavily doped n-type contact. Separate junctions generally have a distance of less than 100 micrometers and have a low doped side-gap region separating the p-type emitter and the heavily doped n-type contact. Embodiments of the process flow of a cell having adjacent junctions can be simpler (at least one process step) as compared to process flow variations of a cell having a separate junction. However, cell efficiency can be compromised by the higher recombination rate of minority carriers at an abrupt abutted junction.

The described manufacturing process flow begins with a clean monocrystalline silicon support wafer. The wafers are wet cleaned, for example, using a dilute mixture of diluted potassium hydroxide (KOH) and hydrochloric acid (HCl) and hydrofluoric acid (HF). The silicon support wafer may have a starting thickness (e.g., a thickness of at least about 150-200 microns for a solar cell of 156 mm x 156 mm) that allows for a reliable mechanical treatment of the disruption to a minimum or negligible.

A thin silicon absorbing layer (e.g., having a thickness of less than about 100 micrometers, more specifically, in the range of about 25 to 75 microns, or thinner) can be used to directly scan silicon supported wafers (Or alternatively may be formed by etching back a thicker starting wafer to the ultimate desired absorber thickness).

At least a portion (or all) of the final silicon absorbing layer may contain an epitaxially deposited silicon layer. When the epitaxial silicon layer is deposited on a silicon support wafer having a sacrificial porous silicon bilayer, a relatively thin (e.g., a thickness in the range of about 20 to 80 microns) epitaxial silicon layer may be deposited on the silicon- And can be mechanically lifted and separated from the silicon support wafer after completion. The bilayer of porous silicon can be formed by a wet bipolar etching process on one side of a silicon support wafer (also referred to as a template). The porous silicon bilayer may have a lower porosity (e.g., less than about 40% porosity) of less than 5 micrometres thick on top of a porous silicon layer of a higher porosity (e.g., greater than about 50% porosity) A porous silicon layer. For example, the thickness of the total porous silicon bilayer may range from less than 1 micron to about 5 microns. An atmospheric pressure chemical vapor deposition (APCVD) epitaxial process is used to deposit an epitaxial silicon layer having a thickness of, for example, less than about 80 micrometers. The APCVD epitaxial silicon tool is often a low cost hardware choice compared to a vacuum based deposition tool. Trichlorosilane (TCS) can be used as a silicon precursor. In the case where the silicon support wafer has a porous silicon bilayer, during the initial hydrogen prebaking process and subsequent epitaxial deposition process, the porous silicon bilayer structure is developed and transformed to make it an excellent epitaxial seed and isolation layer. The porous silicon bilayer portion (lower porosity portion) is transformed into a quasi- monocrystalline silicon (QMS) layer on top of the higher porosity separating layer. During the initial in situ hydrogen pre-bake process (e.g., performed at a wafer temperature of about 1000 ° C to 1150 ° C), the pores on the porous silicon surface are closed (because the QMS layer is formed) and the porous silicon surface has a porous silicon bilayer Lt; RTI ID = 0.0 > epitaxial < / RTI > silicon deposition along with the single crystal structure of the underlying template wafer. The porous silicon bilayer suppresses the diffusion of dopants and impurities from the silicon supporting wafer into the epitaxial silicon layer and acts as a barrier. In addition, the porous silicon bilayer acts as a gettering sink to trap metallic impurities, enabling high-efficiency cell fabrication. An n-type front-field electric field (FSF) layer having a thickness of less than 15 micrometers and an in-situ doping concentration of between about 1 x 10 ¹⁷ cm ^-3 and 1 x 10 ¹⁹ cm ^-3 can be formed at a temperature of, for example, about 1050 캜 to about 1150 캜 Can be epitaxially deposited first by mixing TCS with phosphine gas (PH3) during epitaxial silicon deposition in the process. The n-type epitaxial base layer is then deposited to a thickness ranging from about 8 × 10 ¹⁴ cm ^-3 to about 3 × 10 ¹⁶ cm ^{-3 in} order to increase the total epitaxial layer thickness to a total thickness of the preferred range of about 30 to 80 micrometers Of the doping concentration.

In the wide field region on the back side of the cell, the p-type emitter can be formed in situ during epitaxial silicon deposition or can be ex-situ by drive-in diffusion from the deposited doped oxide thin film. In the in-situ epitaxial formation of the emitter, the epitaxial deposition process is changed from a phosphine gas to a p-type dopant gas such as diborane (B2H6) to form a p-type emitter having a thickness of, for example, . The peak borane surface concentration in the in-situ field emitter may range from about 1 x 10 ¹⁸ cm ^-3 to 1 x 10 ¹⁹ cm ^{-3 in} the selective emitter, but higher doping concentrations can be used without the optional emitter.

Ex-situ doping to form an emitter can be performed by diffusion of boron from a boron-doped oxide film having a thickness in the range of 20 to 100 nanometers, deposited by APCVD (e.g., using silane and oxygen) have. The APCVD oxide thin film may be borosilicate glass (BSG) or boron doped aluminum oxide (Al 2 O 3). Typical boron content is about 0.5% to 5% in the APCVD boron doped oxide film. A thinned undoped oxide layer less than 50 nanometers thick may also be deposited on top of the doped oxide to encapsulate the hygroscopic surface of the doped oxide. The thickness of the subsequent APCVD oxide film overlying the APCVD oxide thickness can be optimized for maximum backside optical (IR) reflectance while meeting the requirements of solid source doping and back passivation. The diffusion or drive of boron can be performed in a furnace with a high temperature thermal annealing and oxidation process. The annealing temperature and time are set to optimize the doping and diffusion of the field emitter. The temperature and time in the annealing process range from about 900 DEG C to 1150 DEG C for 10 to 90 minutes in a nitrogen (N2) atmosphere and optionally in an oxygen (02) atmosphere for 5 to 15 minutes. The peak boron surface concentration of the X-situ field emitter ranges from 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ¹⁹ cm ^-3 after drive diffusion in the selective emitter, but higher doping concentrations can be used without the optional emitter have.

In addition, the APCVD oxide thin film can act as a cell rear passivation layer on the emitter. For passivation, aluminum oxide (Al2O3 or non-stoichiometric AlOx) with a natural internal negative fixed charge is a well-known example of an underlying p-type emitter in which electrons are minority current carriers Thereby enabling enhanced field effect passivation. High temperature annealing and short time thermal oxidation oxidize the interface to increase the density of the APCVD film and further improve the passivation.

Patterned emitter formation may be achieved by pulsed (e.g., picosecond or femtosecond) laser ablation of the APCVD boron doped oxide film to pattern the oxide layer prior to diffusion annealing (in a cell having an X-ray emitter), or by epitaxial growth Doped in-situ emitter (when the emitter is formed in situ during the silicon epitaxy). Pulsed laser tools can have the ability to pulse picosecond or femtosecond laser pulses to minimize Heat-Affected Zone (HAZ). A "cold" pulsed pico second or femtosecond laser ablation process prevents diffusion of the dopant to silicon during the laser ablation process and minimizes the formation of HAZ. The laser ablation process eliminates the use of most consumables and enables fewer battery manufacturing process steps compared to the more expensive lithography and wet etch patterning processes.

Doping of the n-type base contact on the back side of the cell can be performed by diffusion of phosphorus from a doped oxide that is deposited, for example, by printing or APCVD. In APCVD, for example, a deposited film having a thickness in the range of about 20 to 100 nanometers may be a phosphorous silicate glass (PSG: this is phosphorus doped silicon dioxide) or phosphorus doped Al203 (or AlOx). The phosphorus content may range from about 3% to 7% in the phosphorus doped oxide. In addition, a thin undoped oxide (silicon dioxide and / or aluminum oxide) cap layer of less than 50 nanometers thick may be deposited on top of the APCVD doped oxide to encapsulate the hygroscopic surface of the APCVD doped oxide . The peak surface concentration may be ^greater than about 3 x 10 ¹⁹ cm ^-3 (eg, at least 1 x 10 ²⁰ cm ^-3 ) at the base contact after diffusion of the drive. In print-based processing, the available paste (or ink) is, for example, a doped PSG silicate paste (or ink). Optional tools for direct pattern printing include screen printing, inkjet printing, aerosol jet printing, or laser transfer printing. When the PSG paste is directly pattern printed as an alternative to APCVD, the laser pattern processing step can be eliminated to potentially reduce the cost of the manufacturing process flow.

The separation of the base and emitter junctions of the cell with the X-situ emitter can be performed by patterned alignment of the undoped oxide layer on the silicon region around the phosphorus doped oxide in contact with silicon prior to annealing in batch have. The APCVD undoped oxide acts as a diffusion barrier and prevents diffusion of the dopant into the silicon to maintain a thinly doped space region or side gap between the base diffusion and the emitter junction. The undoped oxide layer may be APCVD undoped silicate glass (USG) or APCVD undoped Al2O3 (or AlOx), or a combination thereof. In addition, the undoped oxide may be a printed USG silicate paste (or ink). Optional tools for direct pattern printing include screen printing, inkjet printing, aerosol jet printing, or laser transfer printing. If the USG paste is directly pattern printed as an alternative to the APCVD undoped oxide, the laser patterning step can be removed to potentially establish a lower manufacturing cost.

In cells using an in-situ emitter, high temperature annealing may not be used to prevent diffusion and redispersion of the epitaxial boron emitter. In a cell with an in-situ emitter, a high-temperature laser ablation process (e.g., using a pulsed nano-second laser tool) simultaneously removes the doped oxide and exposes contact openings to drive the dopant (e.g., from PSG) ≪ / RTI > The separation of the base and emitter junctions in a cell using an in-situ emitter can be accomplished by oversizing the openings during the low temperature pulsed laser removal of boron doped silicon and then by using a smaller recessed base contact opening in the overlying doped oxide ≪ / RTI >

The use of selective emitters (lighter boron-doped emitters) with higher doping of the emitter contacts, as compared to doping of the main emitter regions, reduces contact resistance to the emitters, improves emitter passivation, The battery efficiency can be increased. Four exemplary methods are provided for implementing an optional emitter. One method includes high temperature laser ablation of boron doped oxide (APCVD BSG) during contact opening (e.g., using pulsed nano-second laser processing). Boron from BSG is driven to emitter contact simultaneously during high temperature removal of boron doped oxide (BSG).

A second processing method using the X-situ emitter is a second APCVD boron doped oxide (APCVD BSG) layer having a thickness in the range of about 20 to 100 nanometers on the rear side of the cell and a relatively high boron content of about 6 to 10% And this second BSG layer is selectively in contact with the underlying silicon through the patterned openings in the underlying first APCVD boron doped oxide layer and then the major less heavily doped field emitter (To cover a smaller area of the emitter region) and to drive the boron to silicon simultaneously to form a heavily doped emitter contact (covering a smaller portion of the emitter region). A thin undoped oxide layer less than about 50 nanometers thick may be deposited on top of the doped oxide to encapsulate the high-grayscopic surface of the doped oxide. In this scheme, the emitter having a first 2 APCVD boronic higher boron content of the boron peak surface concentration of greater than 3 × 10 ¹⁹ cm ^-3 (e.g., at least 1 × 10 ²⁰ cm ^-3) on the doped oxide (BSG) layer emitter And is optimized to obtain a higher doping concentration on the contact.

After the oxide layer is deposited, patterned, or printed on the back side of the cell, and after driving the diffusion of the dopant (boron and phosphorus) according to a previously designed emitter and base pattern, and after contact of the emitter and base region with the openings (A relatively low silicon content, for example, a silicon content of about 1% to 20% by weight, and in some cases, a silicon content of less than 12%, after the final laser removal process of the oxide layer for the oxide layer) The paste finger line (which contains most of the aluminum it has) is aligned and printed directly on the emitter and base contact openings. The thickness of the printed Al (Si) finger line may be less than about 30 micrometers (e.g., in the range of about 1 micrometer to about 15 micrometers). Optional tools for direct pattern printing include screen printing, inkjet printing, aerosol jet printing, or laser transfer printing. The Al (Si) paste of the high-efficiency IBC cell is a silicon absorbent layer that is between 1% and 20% (e.g., between about 1% and 3%) to minimize mixing of silicon and aluminum at the under-silicon contact during spiking and post- Purity aluminum particles having a silicon content in the range of from 0.1 to 20 wt% (Al-Si alloy particles embedded and alloyed in aluminum particles or mixed with aluminum particles as silicon particles).

Also, without silicon, only the Al-only paste can be aligned and printed directly on an Al (Si) paste (having only Al paste that does not directly contact the silicon contact). Only the Al paste print pattern may be a finger line tailored to an underlying Al (Si) finger pattern, or it may be a laser drilled, hollaized pad of a backplane. Only Al paste can help to stop laser drilling of holes in the backplane, reduce line resistance, and reduce contact resistance to backplane metallization. The thickness of the Al finger lines or pads of this type may be selected to be less than about 25 micrometers.

After printing, Al (Si) paste only Al paste can be thermally annealed to dry or vaporize the solvent, burn-out the binder, and sinter for low line resistance.

The third and fourth portions forming a selective emitter (with a light boron doping in the main emitter region describing a larger portion of the emitter region and a heavy boron doping in the emitter contact region to account for a smaller portion of the emitter region) The fourth method involves thermal eutectic mixing of aluminum from printed Al (Si) paste. Aluminum is a p-type dopant in silicon and can be used to fabricate heavily doped emitter contact regions as part of selective emitter structures and processes.

A third method for forming heavily doped contacts in selective emitter structures is to use an emitter contact (patterned anneal) phase to a higher temperature (above the eutectic temperature of the aluminum-silicon) compared to an Al (Si) A pulsed laser beam, for example, a pulsed nano-second laser beam, is used to selectively heat the Al (Si) paste. The higher temperature on the Al (Si) over the emitter contact (due to the pulse nano second laser irradiation on this region) will cause heavy p + doping by the aluminum in the underlying silicon emitter contact region. In a significant aluminum doping in silicon, the temperature at the interface between the Al (Si) paste and the underlying silicon needs to be close to or higher than the aluminum-silicon eutectic temperature, which is about 577 ° C.

A fourth method for forming heavily doped emitter contacts with less heavily doped selective emitters is by double printing and double annealing of Al (Si) paste. In this method, Al (Si) (or ink) is first printed and annealed on the emitter contact openings (at a higher temperature, e.g., at a temperature higher than the eutectic temperature of the aluminum-silicon). The second Al (Si) is then printed and annealed on the base contact opening (at a lower temperature, e.g., slightly lower than the eutectic temperature of the aluminum-silicon). The total thermal budget of Al (Si) on the emitter contact using the two anneals is higher, which can cause more and heavier aluminum doping to form a heavily doped contact region with the selectively doped emitter (With lighter doping in the main emitter region). In addition, the first anneal with Al (Si) on the emitter has an emitter contact (P < ++ > heavily doped emitter contact), typically less than 600 < 0 > C, For example, at a temperature of about 577 [deg.] C to 650 [deg.] C for a heavier aluminum doping of the catalyst (e.g.

After printing and annealing of the Al (Si) paste and the selective only Al paste, processing of the rear side of the battery on the silicon absorbing layer can be completed. Next, a backplane sheet (e.g., a prepreg sheet having a thickness in the range of about 20 to 300 micrometers, e.g., in the range of 50 to 100 micrometers) is aligned, permanently laminated, and cured on the back side of the cell. Low cost (and very low cost compared to silicon) electrically insulated backplane materials with suitable properties (such as thermal expansion coefficient, thermal and chemical stability, etc.) are selected for good adhesion on the back side of the cell and to reduce mechanical stress on the silicon . Backplane materials without electrical conductivity are chosen to prevent electrical shorting of the emitter and base metallization and to enable a dual level of battery metallization structure. The optional backplane material has a relatively low in-plane thermal expansion coefficient (CTE) close to the CTE of silicon (e.g., backplane sheet material CTE of about 2 to 5 ppm / 占 폚) and includes some flexibility / resilience at the interface on the silicon cell At least some resilient / flexible plastic, paste, and / or flexible polymer resins and plastics. Further, in the post-backplane lamination process of thin silicon solar cells, the backplane material is chemically resistant, compatible with wet chemistry for cleaning and texturing of silicon, and is at least 200 [deg.] C Thermal stability and tolerance up to 300 ° C, compatible with laser drilling to make via holes, and finally selected to meet industry-standard solar module reliability and safety requirements.

After laminating and curing the backplane on the silicon, a suitable laser (e.g., a pulsed laser source) is used to define and scribe / cut the edge borders of the thin silicon cell. In addition, the laser will define the edge borders of the thin silicon cells that are lifted off and separated from the silicon support wafer (when using a reusable wafer / template).

When a bulk wafer for a solar cell (for example, a CZ wafer) is used, there is no lift-off separation step, and there is no reusable template. The starting wafer acts as a solar cell absorber without any reuse.

In the case of a reusable wafer / template process, the separation process and tool can be done by laser splitting of the thin silicon layer directly from the silicon wafer template. The separation of the thin silicon during lift off occurs in a plane in the silicon support wafer that is splitted by a transmissive, focused scanning laser tool.

Alternatively, in the case of an epitaxial silicon layer on a porous silicon bilayer on a silicon support wafer (reusable template), the isolation process may be performed using a single vacuum-clamp (or electrostatic clamp) chuck, for example on the silicon support wafer side, A second vacuum-clamp (or electrostatic clamp) chuck on the silicon back plane support, and then mechanically lifting off the thin silicon from the silicon support wafer. The separation of a laminated solar cell having an epitaxial silicon absorber during lift-off separation occurs at a higher porosity porous silicon interface with a reusable template.

After separation of the backplane laminated thin silicon solar cell, the silicon wafer support can be reconditioned / cleaned for subsequent reuse in a series of multiple reuse cycles. Maintenance and cleaning may include one or a combination of edge grinding and polishing, surface grinding and polishing and / or wet cleaning. After template maintenance / cleaning, the silicon supporting wafer (or template) is reused to make another solar cell. The solar cell manufacturing cost can be further reduced by increasing the number of template reuse of the silicon wafer support (or template).

After lamination and separation (in the case of an epitaxial silicon solar cell or a laser-split solar cell based on a reusable template), or without any separation (without reusable wafers) After lamination for the solar cell, the front side of the silicon solar cell is wet etched / textured with alkalinity (including, for example, KOH or NaOH) and cleaned. Industry standard wet chemical solutions can be used for surface texturing and cleaning. For example, a wet process sequence of texturing and DI rinsing with a solution of HF dipping, deionized wafer (DI) rinsing, hot KOH and a suitable surfactant (such as IPA) results in silicon etching and any pyramidal- To form a surface. After the wet etch texturing, the wet process sequence of cleaning, final DI rinsing and drying with rinsing, diluted HF / HCl solution (or other proven surface cleaning chemicals, such as RCA cleaning) Lt; / RTI > In some cases, optimization of cleaning, rinsing, and drying of the textured silicon surface may be important to achieve good surface passivation.

The textured and cleaned front of the cell can then be coated with a PECVD film optimized for antireflective (AR) and surface passivation (resulting in very low surface recombination rates). The PECVD process temperature may be selected at a temperature low enough to be compatible with the thermal stability of the backplane support material (e.g., at a temperature of < RTI ID = 0.0 &gt; 300 C). The first deposition may be performed using a combination of intrinsic (undoped) amorphous silicon (? -Si: H), amorphous silicon oxide (? -SiOx: H), or an amorphous silicon oxycarbide (? -SiOxCy: H) layer (e.g., having a thickness in the range of about 1 nm to 5 nanometers). The deposition of this first layer can then be optimized to minimize the defect state density (Dit) at the interface. The second deposition is an n-type (doped) amorphous silicon (? -Si: H) with an electrical conductivity in the range of about 0.001-0.1 Siemens / cm which is optimized for improved front passivation quality and stability, an amorphous silicon oxide SiOx: H), or amorphous silicon oxycarbide (? -SiOxCy: H) (thickness <10 nanometers). This wide bandgap doped second layer can enable reduced optical absorption at blue wavelengths (400-600 nanometers), a common issue for standard amorphous silicon, alpha -Si: H. The third and final layer is an amorphous silicon nitride, a-SiNx: H (thickness in the range of 30 to 100 nanometers) with positive fixed charge for improved field effect passivation on the underlying n-type crystalline silicon, Is optimized to minimize. Alternatively, a selective fourth layer on the? -SiNx: H phase, amorphous silicon oxide,? -SiOx: H (30-100 nanometers thick) .

Thermal annealing to 300 캜 may be performed after PECVD deposition to further improve passivation. Such thermal annealing may be performed in an in-situ or subsequent follow-on annealing process in a PECVD tool.

Next, the laser tool drills the via hole through the backplane to enable electrical connection to the underlying Al (Si) or only Al sintered paste. Optimized laser drilling processes or endpoint detectors can be used for interruption either on or within Al (Si) or only Al paste.

The non-conductive backplane is then metallized to connect to the emitter Al (Si) fingers and to each other to the base Al (Si) fingers. For example, one or a combination of the following four backplane metallization process flow options may be used: metal paste, thermal spray, only physical vapor deposition (PVD), and plating with PVD seed layer. In backplane metallization options using metal pastes and thermal spray, selective dry or wet etching may be performed prior to backplane metallization to clean and remove carbon residues and oxides from the via openings.

In backplane metallization using metal pastes, Al (Zn) alloys or Cu (Sn) or solder pastes with flux have via openings with finger patterns aligned at right angles to the underlying Al (Si) fingers and directly on the backplane Can be printed. The thickness of the metal paste may be at least a few micrometers (e.g., a few tens of micrometers) to provide sufficient electrical conductivity. Optional tools for direct pattern printing of fingers and connected busbars include stencil printing, screen printing, inkjet printing, aerosol jet printing, or laser transfer printing. Fluxes in metal pastes, such as chlorinated fluxes, can be used to remove aluminum oxide from Al (Si) or only Al paste at the bottom of via holes and to clean via holes. After printing of the metal paste, annealing may be performed to sinter the metal paste. The typical annealing temperature for sintering the metal solder paste is less than 250 ° C.

In backplane metallization using thermal spray, the atmospheric thermal spray process may be used to align and directly pattern aluminum and / or copper alloys such as aluminum-zinc (AlZn) alloy fingers on the via openings and backplane. Al (Zn) alloys can be used to make soldering easier. The width of the Al (Zn) fingers can be increased and the number of Al (Zn) fingers can be increased by aligning in the direction of the Al (Zn) fingers perpendicular to the direction of the underlying Al (Si) Can be reduced by considerable factors, such as from about 5x to about 30x (compared to on-cell printed paste metallization M1), to make a more manufacturable thermal spray patterning process. Note that the laser-drilled via holes in the backplane are designed to align and connect the underlying Al (Si) finger pattern and the overlying Al (Zn) finger pattern. In addition, the Al (Zn) busbar for connecting the emitter lines and the Al (Zn) busbar for connecting the baseline can be pattern sprayed directly onto the backplane to reduce the number of soldering points.

In backplane metallization using only PVD processes, selective sputter etching may be performed first to clean via holes. Then, one or a combination of aluminum, nickel vanadium, copper and tin having a thickness of a few micrometers (the total thickness may be as large as 10 micrometers) may be deposited by plasma sputtering or evaporation (or a combination thereof) have. The PVD layer can then be patterned to form separate base and emitter fingers and connecting bus bars. The metal fingers on the backplane can be patterned (perpendicularly) at right angles to the underlying Al (Si) fingers. Direct patterning can be done by laser removal of the metal layer. Patterning can also be done by applying a patterned sacrificial mask and wet etch.

In backplane metallization using plating and PVD seed layers, sputter etching is first performed to clean the via holes. Plating seeds of a suitable metal such as nickel vanadium (NiV) on aluminum are then deposited to a thickness of a few micrometers (e.g., total thickness less than 5 micrometers). Metal patterning to form isolated base and emitter fingers and connecting bus bars can be done by laser ablation of the PVD seed. In addition, patterning can be done by applying a patterned sacrificial resist mask on the PVD seed layer. The metal fingers on the backplane are patterned (perpendicular to the metal 1 or M1) at right angles to the underlying fingers. Prior to plating, a sacrificial barrier layer may be applied on the front side of the cell. The electroplating process is then followed by plating a tin capping layer having a thickness from a few micrometers to a few tens of micrometers (e.g., less than 100 micrometers), followed by a thickness of a few micrometers (e.g., less than 10 micrometers) Lt; / RTI &gt; The electroplating process can be optimized to reduce the bowing of solar cells and reduce stress. After electroplating, the sacrificial layer and the mask can be removed by wet etching (if the seed layer is not patterned using laser ablation prior to the plating process).

If necessary, the final process steps in the process flow can be selectively annealed to improve solar cell efficiency (by improving passivation and / or improving the overall electrical conductivity of the metallized structure). The annealing temperature is lowered to be compatible with the backplane support material. The annealing temperature may be less than 300 ° C. (eg, in the range of about 100 ° C. to 300 ° C.) and the cell may be a foaming gas having N 2 mixed with air, nitrogen (N 2), or 3% to 5% forming gas atmosphere or a vacuum.

The finished IBC thin silicon solar cell was then ready for electrical testing, sorting, and lamination to the solar module using industry standard module building techniques.

1 is a cross-sectional view of a backplane-laminated IBC thin silicon solar cell having an electrically insulated backplane support 9 and Al (Si) pastes 2 and 3. The n-type silicon absorber base layer 1 may be of a thickness of less than about 80 micrometers (or, in some instances, less than about 80 micrometers) when the backplane-laminated cell is made using a starting wafer without re- And may be as thick as 150 micrometers) and doped to a concentration of about 8 x 10 ¹⁴ cm ^-3 to about 3 x 10 ¹⁶ cm ^-3 . The p-type field emitter 5 has a depth of less than 1 micrometer and has a thickness between about 1 x ¹⁰¹⁸ cm- ³ and 1 x ¹⁰¹⁹ cm- ³ (in an optional emitter; a higher doping concentration can be used without an optional emitter) Lt; RTI ID = 0.0 &gt; of &lt; / RTI &gt; The boron-doped oxide 7 is a dopant source for diffusion of boron as a p-type field emitter 5. Heavily doped p-type contact region 4 has a thickness ^greater than 3 x 10 ¹⁹ cm ^-3 (and in some cases ^greater than 1 x 10 ²⁰ cm ^-3 ), for example, in selective emitter structures having a depth of less than about 3 micrometers, Of boron or aluminum peak concentration. The heavily doped n-type base contact region 6 has a depth of less than about 3 micrometers and is doped with a phosphorus concentration of greater than 3 x 10 ¹⁹ cm ^-3 (also ^greater than, for example, 1 x 10 ²⁰ cm ^-3 ). Phosphorous doped oxide 8 is a dopant source for phosphorous diffusion to produce a heavily doped n-type base contact region 6. Some methods for fabricating selective field emitter regions 5, heavily doped emitter contact regions 4, and base contact regions 6 in selective emitters are described in FIG. The Al (Si) paste 2 is contacted with the heavily doped emitter contact region 4 and the Al (Si) paste 3 is contacted with the n-type base contact region 6. The electrically insulated backplane 9 can have a thickness in the range of about 20 to 300 micrometers (e.g., 50 to 100 micrometers) and can act as a mechanical support for the thin silicon absorber 1. The emitter metal 15 is comprised of a backplane metal 10 which is a part of a second level metal known as metal 2 which is connected to the Al (Si) paste 2 through a via hole in the backplane 9. The base metal 16 consists of a backplane metal 11 which is part of a second level metal known as metal 2 which is connected to the Al (Si) paste 3 through a via hole in the backplane 9. The emitter metal 15 and the base metal 16 are electrically insulated. Several methods of making the backplane metal layers 10 and 11 are described in FIG. The front side of the silicon absorber 1 is surface textured and has a unique surface roughness such as a-Si: H or? -SiOx: H or? -SiOxCy: H and n-type? -Si: H or? H and have a bilayer antireflective coating of? -SiN: H and? -SiO2: H or an overlying single layer antireflective coating of? -SiN: H.

2 is a cross-sectional view of a backplane-laminated IBC thin silicon solar cell having additional Al pastes 13 and 14 on Al (Si) pastes 2 and 3, respectively. All other characteristics of FIG. 2 are the same as in FIG.

Figure 3 shows the alignment and alignment of the Al (Si) paste emitter 2 and base 3 separated fingers, which are formed on the solar cell silicon absorber 1 with surface oxide layers 7 and 8, Lt; RTI ID = 0.0 &gt; M1 &lt; / RTI &gt;

4 is a top view of a backplane metal (M2 layer) including emitter-separated fingers 10 and backplane metal-base separated fingers 11 on a dielectric backplane 9. [ The backplane metal (metal 2) fingers monolithically interconnect only Al paste pads 13 and 14 and Al (Si) paste fingers 2 and 3 via vias in the backplane. As shown in FIG. 4, the M2 finger can be patterned at right angles to the M1 finger-that is, the M1 and M2 fingers are right angled.

5A and 5B are schematic diagrams showing the back level of the solar cell-that is, the top view of the dielectric backplane with vias and the first metal layer M1. 6 is a diagram showing the level of the rear side of the metal two-layer (M2) of the solar cell. As a general example, metal 1 is in contact with the base (N +) and emitter (P +) regions on the solar cell substrate through a stack or oxide layer (e.g., selective doping to form base and emitter regions on the epitaxial silicon substrate Undoped silicate glass USG, borosilicate glass BSG, and / or silicate glass stack). 5A is a schematic representation of a rear solar cell of a metal 1 pattern (metal 1 patterning or metal 1 printing) comprising a metal 1 base finger and a metal 1 emitter finger. Figure 5b is a schematic representation of a patterned laser drilled via and a back side solar cell of a dielectric backplane (e.g., prepreg) that provides a two-layer metal contact / contact with the underlying metal one layer.

FIG. 6 shows a schematic view of a metal 2 emitter fingers and metal 2 base fingers and corresponding metal 2 base and emitter booth (not shown) after metal 2 formation (e.g., by plating, thermal spray arc plasma spraying, sputtering, 2 is a schematic diagram showing a back side solar cell of a metal two-layer structure including a bar. M2 contacts the exposed area of metal 1 through the via in the dielectric backplane. As shown, the two metal layers are patterned at right angles to the underlying metal layer - the metal one finger and the metal two finger are two-dimensionally right angled. In addition, the M2 pattern may comprise substantially fewer fingers compared to M1, and may generally be formed in a coarser pattern.

The following are considerations and suggestions for printable Al (Si) alloy pastes for high efficiency meshed back contact (IBC) solar cells; However, this list should be used as a guideline because certain materials may not meet all the proposals and other considerations may determine the paste characteristics. The Al (Si) paste may be screen printable or stencil printable. The Al (Si) paste of the high efficiency IBC cell may be used in an amount ranging from 1% to 20% (e.g., 1% to 3%) to minimize spiking and mixing of silicon and aluminum at the under- Silicon content. Another major prerequisite for the Al (Si) paste is a maximum particle size of less than about 10 micrometers (e.g., less than about 2 micrometers); Line resistivity of less than 300 micro-ohm-cm (e.g., less than 30 micro-ohm-cm) after sinter annealing; Contact specific resistivity less than 0.001 ohm.cm on silicon contact 6 and silicon emitter contact 4 without Al (Si) paste break through Si02 or Al2O3; High purity with trace metal concentrations of Fe, Cu, Zn, Cr, and other silicon contaminants of less than 500 ppm per element (e.g., less than 10 ppm per element); Excellent adhesion to silicon, Si02, Al2O3, Al-paste and backplane materials; And maximized reflectivity of the laser wavelength used to laser drill holes through the backplane material. The Al (Si) particles may be approximately spherical or flake-like, and this type of mixing may be used to lower the printed and cured metal resistivity after annealing. The sintering annealing temperature may be less than 650 degrees C (more specifically less than 600 degrees C). Optionally, certain additives such as Ge, Co, Sr, V may be mixed with Al (Si) paste to further reduce the paste resistivity. The printed thickness of the Al (Si) paste in a typical IBC battery design is less than 30 micrometers (e.g., in the range of about 1 micrometer to about 15 micrometers).

The following are considerations and suggestions for a printable only Al paste for selective printing on Al (Si) alloy paste; However, this list should be used as a guideline because certain materials may not meet all the proposals and other considerations may determine the paste characteristics. Generally, only Al paste (e.g., pure Al particles) paste has similar printing, adhesion, purity and annealing proposals / requirements to Al (Si) alloy paste, but larger size particle- Such as less than 15 micrometers, more particularly in the range of about 5 to 10 micrometers, which can improve integration with backplane 9 and backplane metal or with metal-2 10 and 11. Only the Al paste can be screen printable or stencil printable. Only the print pattern of the Al paste can be a finger or pad (with a pad pattern conforming to the via drill pattern) that is aligned on the Al (Si) finger. Only the Al fingers can help reduce the total line resistance of the printed metal fingers for metal-one metallization. The larger Al particles alone can further increase the reflectivity of the laser beam at the wavelengths used for laser drilling of the via holes through the prepreg backplane material 9 and only the Al material can be deposited on the overlaid backplane metals 10 and 11 Lt; RTI ID = 0.0 &gt; contact resistivity. &Lt; / RTI &gt; The resistivity requirement of the Al pad is less than 500 micro-ohm-cm and only the electrical current through the Al pads 13 and 14 passes through the pads 13 and 14 and through the conductive via plugs vertically It is higher than Al (Si) paste because it needs to travel a relatively short distance. The printed thickness of the Al paste may be less than about 30 micrometers, more particularly less than about 25 micrometers. The sintering annealing temperature may be less than about 650 degrees C (more particularly less than 600 degrees C). Other considerations / requirements for Al paste only include:

- resistivity after sinter annealing < 500 ohm-cm;

- no break of Al paste only through Al2O3 or Si02;

Contact resistance on Al (Si) paste < 0.001 ohm / cm2;

- High purity → Trap <500 ppm (eg <10 ppm) per metal contaminant element

Good adhesion to Al (Si) paste, Si02, Al203 and backplane materials.

As used herein, the term paste describes a substance that can be screen printed, and the term ink describes materials that can be either ink jet printed or aerosol jet printed, and both can be applied. Thus, the paste will have a higher viscosity compared to the ink; Since paste alloys or ink alloys can be applied to M1 metallization, in most cases the terms can be used interchangeably. In addition, the Al (Si) alloy (ink and paste) described herein may be formed from a combination of a flake Al (Si) particle alloy and a spherical Al (Si) particle alloy in combination with an organic solvent and an organic binder . In some instances, other types of particle-mixed flake phases and spherical particle-Al (Si) alloys may further reduce the resistivity. Additionally, after application / deposition with the M1 layer, an Al (Si) alloy, such as a mixed flake phase and a spherical particle Al (Si) alloy, can be dried to evaporate the solvent material and then burn off the binder residue Can be heated in a furnace containing a reducing oxidation atmosphere. In addition, Al (Si) alloys, for example Al (Si) alloys in the form of mixed particles, can be heat treated to fuse the particles together to increase the alloy density.

The process flow below is provided in detail to form a rear contact solar cell with Al (Si) metallization. Those skilled in the art will recognize that process flows and structural aspects described in numerous and various ways to form solar cells according to the disclosed subject matter may be combined and / or added or removed.

Figure 7 shows Al (Si) paste printing and annealing options. First process flow option 20-one burn-out anneal and sinter anneal- includes printing # 1 21 (21) of Al (Si) paste emitter and base separating fingers 2 and 3, respectively. With clean dry air at a temperature less than about 300 ° C, drying # 1 (22) at a drying time in the range of about 30 seconds to 5 minutes removes the solvent from the printed Al (Si) paste. Print # 2 23 is for only Al fingers that are aligned on Al paste pads 13 and 14 or Al (Si) paste fingers 2 and 3, respectively. Dry # 2 (24) under conditions similar to Dry # 1 (22) removes the solvent from the Al paste only. Burnout annealing (25) in a clean dry air (or oxidizing atmosphere) at a temperature of less than about 550 ° C, for a time in the range of about 30 seconds to 5 minutes, burns off and removes residual organics from the printed and dried paste. Annealing in a nitrogen gas or a mixture of nitrogen and hydrogen gas (i.e., a forming gas atmosphere) at a temperature in a range of less than about 600 占 폚 (for example, in a range of more than about 550 占 폚 and less than about 600 占 폚) The metal layer 26 may be formed of a metal such as aluminum or aluminum to achieve reduced cured paste resistivity without diffusion or spiking of the aluminum to the silicon contacts 4 and 5 or aluminum break through the surface oxide layers 7 and 8. [ Coalesces the particles.

The second process flow option 30 - two burnout and two sinter anneal for selective emitter formation - enables the formation of a heavily doped contact region 4 in silicon with optional emitter process and structure do. Print # 1 31 is for Al (Si) paste emitter separated fingers 2. Dry # 1 32 removes the solvent from the Al (Si) paste. Burnout annealing # 2 33 burns and removes organic matter from the Al (Si) paste. Sinter annealing # 1 (35) in a nitrogen gas or a mixture of nitrogen and hydrogen gas (forming gas) at a temperature of less than about 650 ° C, for a time in the range of about 30 seconds to 30 minutes, And to selectively diffuse the emitter silicon contact region 4 through the eutectic aluminum-silicon formation in the emitter contact region. Print # 2 is for the Al (Si) paste-based fingers 3. Dry # 2 36 removes the solvent from the Al (Si) paste base finger 3. Print # 3 37 is only for Al fingers aligned on Al paste pads 13 and 14 or Al (Si) paste fingers 2 and 3. Dry # 3 (38) removes the solvent from the Al paste only. Burnout # 2 39 burns and removes organics from Al (Si) paste base fingers 3 and only Al paste. The final sinter anneal 40 at a temperature less than about 600 캜 (e.g., less than the aluminum-silicon eutectic temperature of 577 캜) diffuses or spikes aluminum into the silicon contacts 4 and 5, And (8), without breaking aluminum.

8 illustrates a process flow diagram for fabricating a silicon solar cell by laser splitting and lift-off separation of a thin silicon layer from a reusable silicon support wafer (e.g., a support wafer having a thickness in the range of about 300 to 1000 micrometers) . In addition, the deformation of the drawing is applied to produce a thin silicon wafer cell from the starting silicon wafer without any lift-off separation (acting as part of the final backplane-laminated solar cell) without any re-usable silicon wafer support. First, the silicon wafer is subjected to wet cleaning 50 with a mixed solution of hydrochloric acid (HCl) and hydrofluoric acid (HF), for example, after a potassium hydroxide (KOH) solution. In addition, this initial etching process can act as a SDR (Saw Damage Removal) process step. The rear side of the battery is then processed to form a rear oxide passivation layer 7 and patterned doped regions: selective emitter contact region 4, field emitter region 5, (51); Followed by patterning printing and annealing 20 and 30 of Al (Si) paste 2 (3) and selective Al paste 13 (14). FIG. 14 summarizes the battery rear process flow option 51. When the battery rear side processing is completed, the dielectric backplane 9 is aligned, adhered, laminated, and cured on the rear side of the battery.

When manufacturing a solar cell using lift-off separation from a reusable support wafer (template), the laser can be trenched to define an edge release border. A transmissive scanning laser is then used to split the thin silicon layer from the silicon support wafer. The thin silicon cell is then lifted and separated from the reusable support wafer and the edges of the silicon cell and backplane can be laser cut and trimmed. After detachment, the silicon support wafer is reused and can be cleaned after maintenance, e.g., by grinding and polishing the edge and / or surface. The silicon support wafer may undergo several reuse cycles 58. After the separation of the thin silicon 59, the front side of the silicon cell is processed as described hereinafter. In the case of manufacturing a solar cell from a starting wafer without using a lift-off separation and without a reusable supporting wafer (template), the laser splitting, lift-off separation and edge trimming processes are not performed, Likewise, it proceeds directly from the backplane lamination process to the front side processing of the silicon battery.

The front side of the silicon cell is wet etched / textured, for example, by HF dipping and DI water rinsing to remove the surface oxide first, followed by a high temperature 50 to 100 占 폚 mixed solution of KOH and a surfactant for silicon etching and arbitrary pyramidal surface texturing (54), it is rinsed and washed with, for example, a mixed solution of HF and HCl, and finally subjected to DI water washing and drying. The front side of the silicon cell is then coated with a low temperature (≤ 300 ° C) PECVD thin film for passivation and anti-reflection (55). The first thin film may be formed from an intrinsic (undoped) amorphous silicon (a-Si: H) or a-SiOx: H or a-SiOxCy : H can be. The second layer thin film may be n-type (doped) amorphous silicon (? -Si: H) or? -SiOx: H or? -SiOxCy: H thinner than 10 nm thick for improved field effect passivation and stable passivation have. The capping may be amorphous SiOxNy: H with a thickness and refractive index optimized for a minimized reflectivity or SiOx: H on a bilayer SiNx: H. When the cell frontside machining is complete, the backplane is machined (56) by a laser to drill the buried Al (Si) and the via holes to open contact up to Al paste only. The patterned metallization (metal 2) 57 on the dielectric backplane and via holes forms a second metal layer to connect and collect current from the embedded Al (Si) and only Al paste. Figure 13 summarizes the backplane metallization process flow option (57). Thin silicon cells with backplanes will be processed for final laser edge trimming, testing and sorting. Note that the thin silicon cell is mechanically supported by the silicon support wafer through the process step prior to separation and is mechanically supported by the dielectric backplane 9 through the post-separation process step.

9 shows a process flow diagram for fabricating thin silicon solar cells by laser splitting and lift-off separation of an epitaxial silicon layer from a silicon supporting wafer (e.g., a thickness in the range of 300 to 1000 micrometers). The process flow begins in the same manner as in Fig. 8 using the wet cleaning 50 of the silicon support wafer. The epitaxial film is then deposited to a total thickness of 80 micrometers (71). The epitaxial layer is first formed to a thickness of less than 15 micrometers which is optimal for fabricating a selective in-situ surface field (FSF) in a thin silicon cell, with an n-type doping concentration of about 1 x 10 ¹⁷ cm ^-3 to 1 x 10 ¹⁹ cm ^-3 . &Lt; / RTI &gt; On the FSF epitaxial layer, the epitaxial process is changed for an optimized n-type base doping concentration ranging from 8 × 10 ¹⁴ cm ^-3 to 3 × 10 ¹⁶ cm ^-3 . The total thickness of the epitaxial layer is less than about 80 micrometers. After epitaxial deposition 71, the process flow is the same as shown in Fig.

10 shows a process flow diagram for fabricating thin silicon solar cells by laser splitting and lift-off separation of an epitaxial silicon layer from a porous silicon layer. The process flow begins in the same manner as Figures 8 and 9 using the wet cleaning 50 of the silicon support wafer. A bi-layer of porous silicon is then formed 70 on one side of the silicon support wafer prior to epitaxial deposition 71 of the absorber layer. The bilayer of porous silicon defines the plane on which the epitaxial layer is to be separated from the silicon supporting wafer. In addition, the porous silicon bilayer can improve the absorption of laser energy used in the laser splitting 52 of the thin silicon layer. The subsequent process steps in FIG. 10 are the same as in FIG.

11 shows a process flow diagram for fabricating a thin silicon solar cell by mechanical lift-off separation of an epitaxial silicon layer from a porous silicon layer. 11 is the same as FIG. 10 except that step 72 in which the thin silicon cell is mechanically lifted and separated from the silicon support wafer. In this process flow, the thickness and the porous density of the porous silicon bilayer are optimized to enable mechanical separation of the epitaxial silicon layer.

12 shows a process flow diagram for fabricating a thin silicon solar cell by front side silicon etching and texturing of a silicon wafer (e.g., a thickness in the range of about 100 to 200 micrometers). Fig. 12 is the same as Fig. 8 with the exception of step 73 in which there is no splitting of the thin silicon layer. Process step 54 for the process flow of FIG. 12 is optimized to etch the front side of the silicon wafer to a thin silicon thickness of, for example, 30 to 70 microns optimized for maximum cell efficiency.

Figure 13 shows four selective backplane metallization process flows. Process Flow Option # 1 (57A) uses a printable metal paste. The process flow begins with a selective wet or dry etch 84 to clean the via holes. The cleaning may be designed to remove any remaining organic backplane residue from the laser drilling process 56, for example. The cleaning can also be designed to remove surface oxides, for example, from Al (Si) pastes 2 and 3 or only Al pastes 13 and 14. The solder metal paste is then printed directly on the via openings and the backplane 9. The printed pattern of the backplane metal separated emitter 10 and base 11 fingers is aligned on the via openings and the backplane to connect the underlay emitter and base Al (Si) and only Al paste fingers to each other. The metal solder paste may consist of Al (Zn) (aluminum-zinc) alloy particles or Cu (Sn) (copper-tin) alloy particles. Also, for lower contact resistance, the metal solder paste may have a chlorine containing flux added to reduce the surface oxide on the underlying Al (Si) or only Al paste. A final anneal 86 at a temperature less than 300C is performed to sinter the metal solder paste for low resistance. In addition, the final anneal 86 can improve surface passivation by the front side SiOxCy: H thin film 12. Process Flow Option # 2 (57B) uses thermal spray to apply backplane metal. The process flow begins the same as (57A) using selective wet or dry etch 84 to clean the via holes. The thermal spray process is then used to directly pattern and align Al (Zn) (aluminum-zinc) alloy metal on the backplane and via openings. The shadow mask may be used to directly pattern the backplane metal discrete emitter 10 and base 11 fingers. Selective final annealing 86 may improve front surface passivation. Process Flow Option # 3 (57C) uses a PVD layer for backplane metallization. The PVD process 88 can be initiated using sputter etching to remove surface oxide from Al (Si) or only Al paste in the via hole. The PVD double layer is then deposited with a thickness of 2 to 5 micrometers of aluminum followed by 10 to 400 nanometers of nickel-vanadium (NiV). Alternatively, the PDV bilayer of copper (Cu) is deposited to a thickness of 1 to 3 micrometers and then to tin (Sn) of a thickness of 10 to 400 nanometers. Thicker PVD metals can be evaporated, and thinner PVD metals can be sputtered. After PVD, selective annealing 86 may be performed to improve forward passivation. The PVD metal layer is then patterned by using a sacrificial mask or by laser removal from the dielectric backplane and wet etched to form the backplane metal separated emitter 10 and base 11 fingers. Process flow option # 4 uses plating and PVD seed layers for backplane metallization. PVD machining 90 can begin sputter etching. The PVD double layer is then deposited with Al of 0.1 to 2 micrometers in thickness, followed by NiV of 10 to 100 nanometers in thickness. After PVD, selective annealing 86 may be performed to improve forward passivation. The metal is then patterned by application of a patterned sacrificial dielectric mask that is later removed or by laser removal from the backplane. The sacrificial dielectric barrier layer 92 is applied on the front side of the cell, prior to the electroplating 93 of a copper layer (thickness of 10 to 50 micrometers) and a tin capping layer (thickness of less than 1 micrometer). Finally, the wet etch selectively removes the sacrificial layer (94).

Figure 14 shows a tabular summary of the battery rear process flow option 51 for an optional emitter. The tabular summary is divided into the dopant source option 100, the bond separation option 101, the Al (Si) paste printing and annealing option 102, and the number of process tools 103 in the process flow. The dopant circle option 100 is further classified into a field emitter region 104, an optional emitter contact region 105, and a base contact region 106. The table lists the number of flow options 128 along with the process flow name 129, which will be described in more detail later in the drawings.

15 shows a battery backside process flow option 130A for an ex situ emitter using an adjacent junction 116 and APCVD boron doped oxide. In this process flow option 130A, the selective emitter contact region is doped (109) by high temperature laser ablation of the APCVD boron doped oxide (109) and doped (113) by annealing to the base contact region of APCVD doped oxide. The process flow begins at atmospheric pressure chemical vapor deposition (APCVD) 150 of an undoped silicate glass (USG) of borosilicate glass (BSG) or boron doped Al2O3 or an undoped oxide capping layer of undoped Al2O3 do. The undoped capping layer protects the under-doped layer from chemical reactions with moisture at atmospheric pressure. The APCVD boron oxide layer stack is then patterned (151) by pulsed laser desorption to open the base contact area on the silicon. Damage to silicon can be reduced by optimized laser processes with pulse times from femtosecond to few picoseconds. APCVD phospho-silicate glass (PSG) or phosphorus doped Al2O3, then undoped layer, is deposited 152 on the base contact opening and the boron doped layer stack. The cell is then annealed and oxidized (153) in the furnace with temperature and time to drive the boron to the field emitter region, phosphorus to the base contact region. Thermal oxidation can improve rear surface passivation by APCVD layers. A boron concentration of 0.5% to 3% in the APCVD boron oxide layer is optimized to form a sheet resistance of 100-300 ohm / square in the field emitter region after thermal diffusion. Phosphorus concentration in the APCVD oxide layer is optimized to form a sheet resistance of less than 20 ohm / square at the base contact region after thermal diffusion. Patterning of the oxide stack and pulsed laser desorption are then performed (154) to selectively boron-dope and open the emitter contact region on the silicon. The high temperature laser ablation process is optimized to drive the boron to form a sheet resistance of less than 20 ohm / square at the emitter contact area. Patterning of the oxide stack and pulsed laser desorption are performed 155 to reopen the base contact area. The battery backside machining is completed by Al (Si) printing and annealing option # 1 (20) as shown in FIG. The Al (Si) paste makes contact with the emitter and base, and enables the battery rear reflector.

FIG. 16 shows a battery backside process flow option 130B for an adjacent junction 116 and for an X-ray emitter employing APCVD boron doped oxide. In this process flow option 130B, the selective emitter contact region is doped 110 by annealing of a second boron doped APCVD oxide layer having a high boron concentration and the base contact region is annealed to APCVD doped oxide (113). The process flow begins with APCVD 150 of an undoped oxide capping layer followed by a boron doped oxide layer with a boron concentration between 0.5% and 3% optimized for doping the field emitter region. The APCVD boron oxide layer stack is then patterned 163 by pulsed laser desorption to open the emitter contact area on the silicon. A second APCVD boron doped oxide layer is deposited (156) at a higher boron concentration of 5% to 10%, which is optimized for doping the emitter contact region. The APCVD boron oxide layer stack is then patterned 151 by pulsed laser desorption to open the base contact area on the silicon, and a doped oxide layer, APCVD, is deposited on the base contact opening and the boron oxide layer stack (152). The cell is then annealed and oxidized (157) in a furnace along with temperature and time to drive the silicon into the silicon field emitter region and the silicon emitter contact region to phosphorus into the silicon base contact region. Annealing and APCVD doping concentrations are optimized to form a sheet resistance of less than 20 ohm / square at the silicon emitter and base contact regions after thermal diffusion, and a sheet resistance of 100 to 300 ohm / square at the silicon field emitter region. Patterning of the oxide stack and pulsed laser desorption are done 158 to reopen the emitter contact area and reopen the base contact area. The battery backside processing is completed by Al (Si) printing and annealing option # 1 (20) as shown in FIG.

Figure 17 shows a battery backside process flow option 130C for an adjacent junction 116 and for an x-ray emitter employing APCVD boron doped oxide. In this process flow option 130C, a selective emitter contact region is doped 111 by laser annealing of the Al (Si) paste and doped 113 by doping of the doped oxide which is the APCVD base contact region. The process flow includes APCVD 150 of the boron oxide layer, pulsed laser desorption 151 of oxide to open the base contact region, APCVD 152 of phosphorus oxide layer, and base contact doping and field emitter doping formation Lt; RTI ID = 0.0 &gt; 153 &lt; / RTI &gt; Patterning of the oxide stack and pulsed laser desorption are then performed to reopen the base contact region on silicon and to open the emitter contact region on silicon (159). Al (Si) printing and annealing option # 1 processing 20 is then performed as shown in FIG. The anterior and posterior processing is completed by selectively annealing the Al (Si) emitter fingers to drive the aluminum to silicon and form optional emitters (160). The laser annealing process is optimized to form a sheet resistance of less than 20 ohm / square in the emitter contact area and to drive the aluminum.

FIG. 18 shows a battery backside process flow option 130D for an adjacent junction 116 and an X-ray emitter employing APCVD boron doped oxide. In this process flow option 130D, a selective emitter contact region is doped 112 by sintering annealing of Al (Si) paste, and the base contact region is doped 113 by AP annealing to a doped oxide. The process flow includes APCVD 150 of the boron oxide layer, pulsed laser desorption 151 of oxide to open the base contact region, APCVD 152 of phosphorus oxide layer, and base contact doping and field emitter doping formation Lt; RTI ID = 0.0 &gt; 153 &lt; / RTI &gt; Patterning of the oxide stack and pulsed laser desorption are then performed to reopen the base contact region on silicon and to open the emitter contact region on silicon (159). Al (Si) printing and annealing option # 2 processing 30 is performed as shown in FIG. The sintered # 1 anneal 34 is optimized to form a sheet resistance of less than 20 ohm / square at the emitter contact area and drive the aluminum.

19 shows a battery backside process flow option 130E for an ex situ emitter using an adjacent junction 116 and APCVD boron doped oxide. In this process flow option 130E, the selective emitter contact region is doped (109) by high temperature laser ablation of the APCVD boron doped oxide (109) and the base contact region is doped by doping of the printed phosphosilicate glass (115). The process flow begins with direct patterning and alignment printing 162 of PSG paste-separated fingers on the base contact area of silicon. The width of printed PSG paste fingers is less than 150 micrometers. Direct pattern printing Optional tools include screen printing, inkjet printing, aerosol jet printing, or laser transfer printing. After printing, the PSG paste is dried and annealed in air to burn out the organic binder material. Next, the APCVD boron doped oxide layer is deposited (150) and then annealed and oxidized (153) for base contact doping and field emitter doping formation. The phosphorus concentration in the PSG paste is optimized for a sheet resistance of less than 20 ohm / square in the silicon base contact region after thermal diffusion. Patterning of the oxide stack and pulsed laser high temperature removal is done to selectively boron-doped and open the emitter contact region on the silicon (154). Patterning of the oxide stack and pulsed laser desorption are performed to open the base contact area (151). The battery backside processing is completed by Al (Si) printing and annealing option # 1 (20) as shown in FIG.

FIG. 20 shows a battery backside process flow option 130F for an adjacent junction 116 and an X-ray emitter employing APCVD boron doped oxide. In this process flow option 130F, the selective emitter contact region is doped 110 by annealing of a second boron doped APCVD oxide layer of high boron concentration, and the base contact region is doped with a printed phosphosilicate glass (PSG) paste (115). &Lt; / RTI &gt; The process flow is followed by direct patterning and alignment printing 162 of the PSG paste-separated fingers on the base contact area of the silicon to form a boron-doped oxide &lt; RTI ID = 0.0 &gt; Layer APCVD &lt; RTI ID = 0.0 &gt; 150 &lt; / RTI &gt; The APCVD boron oxide layer stack is then patterned 163 by pulsed laser desorption to open the emitter contact area on the silicon. A second APCVD boron doped oxide layer is deposited (156) at a higher boron concentration that is optimized to dope the emitter contact region. The cell is then annealed and oxidized 157 to the silicon field emitter region and the silicon emitter contact region, along with the temperature and time to drive the boron to the silicon base contact region. Patterning of the oxide stack and pulsed laser desorption are performed 164 to open the base contact area and reopen the emitter contact area. The battery backside processing is completed by Al (Si) printing and annealing option # 1 (20) as shown in FIG.

Figure 21 shows a battery backside process flow option 130G for an ex situ emitter using an adjacent junction 116 and APCVD boron doped oxide. In this process flow option 130G, the selective emitter contact region is doped 111 by laser annealing of Al (Si) paste and the base contact region is doped by annealing to a printed phosphosilicate glass (PSG) paste (115). The process flow begins with APCVD 150 of the boron doped oxide layer optimized to dope the field emitter region after direct patterning and alignment printing 162 of the PSG paste isolated finger on the base contact region of silicon . Subsequently, furnace annealing and oxidation drive boron for the base contact doping (153) to form the field emitter doping. Patterning of the oxide stack and pulsed laser desorption are then performed to open the base contact region on silicon and open the emitter contact region on silicon (165). Al (Si) printing and annealing option # 1 processing 20 is then performed as shown in FIG. The battery backside machining is completed (160) by selectively annealing the Al (Si) emitter fingers to drive the aluminum with silicon and form an optional emitter.

FIG. 22 shows a cell rear side process flow option 130H for an adjacent junction 116 and an X-ray diffuser using APCVD boron doped oxide. In this process flow option 130H, a selective emitter contact region is doped 112 by sintering annealing of Al (Si) paste and the base contact region is doped by annealing to a printed phosphosilicate glass (PSG) paste (115). The process flow begins with APCVD 150 of the boron doped oxide layer optimized to dope the field emitter region after direct patterning and alignment printing 162 of the PSG paste isolated finger on the base contact region of silicon . Subsequently, furnace annealing and oxidation drive boron for the base contact doping (153) to form the field emitter doping. Patterning of the oxide stack and pulsed laser desorption are then performed to open the base contact region on silicon and open the emitter contact region on silicon (165). Al (Si) printing and annealing option # 2 processing 30 is performed as shown in FIG. The sintered # 1 anneal 34 is optimized to drive the aluminum and form a sheet resistance of less than 20 ohm / square in the emitter contact area.

23 shows a cell rear side process flow option 131A for an X-ray emitter using APCVD undoped oxide 117 separated junctions and APCVD boron oxide. In this process flow option 131A, the selective emitter contact region is doped (109) by high temperature laser ablation of the APCVD boron doped oxide (109) and doped (113) by annealing to the base contact region of APCVD doped oxide. The process flow starts APCVD 150 of the boron oxide layer. The patterning of the oxide stack and pulsed laser desorption are then performed 166 to open the emitter-base isolation region on the silicon. An undoped APCVD oxide layer of undoped silicate glass (USG) or undoped Al2O3 is deposited (167). The undoped oxide layer may be a passivation layer and a barrier layer to prevent diffusion of the dopant into the emitter-base isolation region on the silicon. The APCVD oxide layer stack is then patterned (151) by pulsed laser desorption to open the base contact area on silicon (152) and a doped oxide layer, APCVD, is deposited (152). The furnace annealing and oxidation then drives the boron for the base contact doping (153) and the base-emitter isolation region on the undoped silicon to form the field emitter doping. Patterning of the oxide stack and pulsed laser high temperature removal is done to selectively boron-doped and open the emitter contact region on silicon (154). The APCVD boron oxide layer stack is then patterned (155) by pulsed laser desorption to reopen the base contact region on the silicon. The battery backside processing is completed by Al (Si) printing and annealing option # 1 (20) as shown in FIG.

FIG. 24 shows a cell rear process flow option 131B for an X-ray diffuser using APCVD undoped oxide 117 and APCVD boron oxide. In this process flow option 131B, the selective emitter contact region is doped 110 by annealing to a second boron doped APCVD oxide layer of high boron concentration and the base contact region is annealed to APCVD doped oxide (113). The process flow begins with APCVD 150 of the boron oxide layer and is then patterned 163 by pulsed laser desorption to open the emitter contact area on the silicon. A second APCVD boron doped oxide layer is deposited (156) at a higher boron concentration that is optimized to be doped with the emitter contact region. The patterning of the oxide stack and pulsed laser desorption are then performed to open the emitter-base region on silicon (166). Next, an undoped APCVD oxide layer is deposited (167) followed by patterning of the oxide stack and pulsed laser desorption to open the base contact area on silicon (151). A doped oxide layer, APCVD, is deposited on the base contact opening and the boron oxide layer stack (152). The cell is then annealed and oxidized 157 with the temperature and time to drive the boron to the silicon field emitter region and the silicon emitter contact region to drive the phosphorus to the silicon base contact region (157), the undoped silicon Leaving a base-emitter isolation region on the substrate. Patterning of the oxide stack and pulsed laser desorption are performed to reopen the emitter contact area and reopen the base contact area (158). The battery backside processing is completed by Al (Si) printing and annealing option # 1 (20) as shown in FIG.

FIG. 25 shows a cell rear side process flow option 131C for an X-ray emitter using junctions separated by APCVD undoped oxide 117 and APCVD boron doped oxide. In this process flow option 131C, the selective emitter contact region is doped 111 by laser annealing of the Al (Si) paste and doped 113 by doping of the doped oxide, which is APCVD, with the base contact region. The process flow starts APCVD 150 of the boron oxide layer. The patterning of the oxide stack and pulsed laser desorption are then performed to open the emitter-base region on silicon (166). An undoped APCVD oxide layer is then deposited (167) and the APCVD oxide layer stack is patterned (151) by pulsed laser desorption to open the base contact area on the silicon. After the APCVD doped oxide layer is deposited 152, furnace annealing and oxidation may be performed for the base contact doping, driving the boron for field emitter doping formation 153, Leaving an emitter isolation region. Patterning of the oxide stack and pulsed laser desorption are then performed 159 to open the emitter contact region on the silicon and reopen the base contact region on the silicon. Al (Si) printing and annealing option # 1 processing 20 is performed as shown in FIG. The battery backside machining is completed (160) by forming a selective emitter and selectively annealing the Al (Si) emitter fingers to drive the aluminum into silicon.

FIG. 26 shows a battery rear process flow option 131D for an X-ray diffuser using APCVD undoped oxide 117 separated junction and APCVD boron doped oxide. In this process flow option 131C, the selective emitter contact region is doped 112 by sintering annealing of the Al (Si) paste, and the base contact region is doped 113 by doping of the doped oxide which is APCVD. The process flow is the same as process flow option 131C except that the last two steps are replaced by Al (Si) printing and annealing option # 2 processing (30), as shown in FIG. The sintered # 1 anneal 34 is optimized to form a sheet resistance of less than 20 ohm / square at the emitter contact area and drive the aluminum.

FIG. 27 shows a cell rear side process flow option 132A for an X-ray emitter using junction 118 separated by a printed USG and APCVD boron doped oxide. In this process flow option 132A, the selective emitter contact region is doped (109) by high temperature laser ablation of the APCVD boron doped oxide (109) and doped (113) by annealing to the base contact region of APCVD doped oxide. The process flow begins with direct patterning and alignment printing 168 of USG paste-separated fingers on the base contact area of silicon. The width of the printed USG finger is 50 to 300 micrometers and is optimized to form an emitter base isolation region on silicon. Optional tools for direct pattern printing include screen printing, inkjet printing, aerosol jet printing, or laser transfer printing. After printing, the USG paste is dried and annealed in air to burn out the organic binder material. After USG printing, the process flow is the same as process flow option 130A. The USG paste is a barrier layer during annealing to prevent diffusion of the dopant into the emitter-base isolation region on silicon, and after annealing, the USG paste is a passivation layer on the emitter-base isolation region on silicon.

28 shows the junction 118 separated by the printed USG and the battery backside process flow option 132B for the X-ray emitter using APCVD boron doped oxide. In this process flow option 132B, the selective emitter contact region is doped 110 by annealing of a second boron doped APCVD oxide layer having a high boron concentration and the base contact region is annealed to APCVD doped oxide (113). The process flow begins with direct patterning and alignment printing 168 of USG paste separated fingers having a width of 50 to 300 micrometers on the base contact area of silicon. After USG printing, the process flow is the same as process flow option 130B. The USG paste is a barrier layer during low annealing to prevent diffusion of the dopant, which is the drive, and defines an emitter-base region on silicon.

FIG. 29 shows a junction 118 separated by a printed USG and a battery backside process flow option 132C for an X-ray emitter using APCVD boron doped oxide. In this process flow option 132C, the selective emitter contact region is doped 111 by laser annealing of the Al (Si) paste and the base contact region is doped 113 by doping of the doped oxide which is APCVD. The process flow begins (168) with direct patterning and alignment printing of a USG paste separated finger having a width of 50 to 300 micrometers on the base contact area of silicon. After USG printing, the process flow is the same as process flow option 130C. The USG paste is a barrier layer during furnace annealing to prevent drift, which is the drive of the dopant, and defines an emitter-base isolation region on silicon.

Figure 30 shows a junction 118 separated by a printed USG and a battery backside process flow option 132D for an X-ray emitter using APCVD boron doped oxide. In this process flow option 132D, a selective emitter contact region is doped 112 by sintering annealing of Al (Si) paste and the base contact region is doped 113 by AP annealing to a doped oxide. The process flow begins (168) with direct patterning and alignment printing of a USG paste separated finger having a width of 50 to 300 micrometers on the base contact area of silicon. After USG printing, the process flow is the same as process flow option 130D. The USG paste is a barrier layer during furnace annealing to prevent drift, which is the drive of the dopant, and defines an emitter-base isolation region on silicon.

31 shows a cell rear side process flow option 132E for an X-ray emitter using junction 118 separated by a printed USG and APCVD boron doped oxide. In this process flow option 132E, the selective emitter contact region is doped (109) by high temperature laser ablation of the APCVD boron doped oxide (109) and the base contact region is doped (115) by annealing of the printed PSG paste. The process flow begins (169) with direct patterning and alignment printing of PSG paste-separated fingers having a width less than 150 micrometers on the base contact area of silicon. PSG paste is dried after printing. The USG paste lines are then aligned and printed 170 on the PSG finger. Printing of the USG paste line is optimized to a minimum thickness and width to fully encapsulate the PSG paste line. The USG paste is then dried, and the PSG and USG paste are annealed in air to burn out the organic binder material. The width of the emitter-base isolation region on the silicon is defined by the extra USG line width extending beyond the edge of the underlying PSG paste. After printing and annealing, the process flow is identical to process flow option 130E, except for the first step (162). The USG paste is a barrier layer during furnace annealing and prevents drive diffusion of the dopant into the emitter-base isolation region.

32 shows the junction 118 separated by the printed USG and the battery backside process flow option 132F for the X-ray emitter using APCVD boron doped oxide. In this process flow option 132F, the selective emitter contact region is doped 110 by annealing of a second boron doped APCVD oxide layer having a high boron concentration, and the base contact region is annealed by annealing of the printed PSG paste (113). The process flow begins (169) with direct patterning and alignment printing of PSG paste-separated fingers on the base contact area of silicon. The PSG paste is dried after printing, after which the USG paste line is aligned and printed 170 to encapsulate the PSG finger. The USG paste is then dried, and the PSG and USG paste are annealed in air to burn out the organic binder material. The width of the emitter-base isolation region on the silicon is defined by the extra USG paste line width extending beyond the edge of the underlying PSG paste. After printing and annealing, the process flow is identical to process flow option 130F except for the first step (162). The USG paste is a barrier layer during furnace annealing and prevents drive diffusion of the dopant into the emitter-base isolation region.

33 shows a cell rear side process flow option 132G for an X-ray emitter using junction 118 separated by a printed USG and APCVD boron doped oxide. In this process flow option 132G, the selective emitter contact region is doped 111 by laser annealing of the Al (Si) paste and the base contact region is doped 115 by annealing of the printed PSG paste. The process flow begins (169) with direct patterning and alignment printing of PSG paste-separated fingers on the base contact area of silicon. The PSG paste is dried after printing, after which the USG paste line is aligned and printed 170 to encapsulate the PSG finger. The USG paste is then dried, and the PSG and USG paste are annealed in air to burn out the organic binder material. The width of the emitter-base isolation region on the silicon is defined by the extra USG paste line width extending beyond the edge of the underlying PSG paste. After printing and annealing, the process flow is identical to process flow option 130G except for the first step (162). The USG paste is a barrier layer during furnace annealing and prevents drive diffusion of the dopant into the emitter-base isolation region.

Figure 34 shows a junction 118 separated by a printed USG and a battery backside process flow option 132H for an X-ray emitter using APCVD boron doped oxide. In this process flow option 132H, the selective emitter contact region is doped 112 by sintering annealing of the Al (Si) paste and the base contact region is doped 115 by annealing of the printed PSG paste. The process flow begins (169) with direct patterning and alignment printing of PSG paste-separated fingers on the base contact area of silicon. The PSG paste is dried after printing, after which the USG paste line is aligned and printed 170 to encapsulate the PSG finger. The USG paste is then dried, and the PSG and USG paste are annealed in air to burn out the organic binder material. The width of the emitter-base isolation region on the silicon is defined by the extra USG paste line width extending beyond the edge of the underlying PSG paste. After printing and annealing, the process flow is identical to process flow option 130H except for the first step (162). The USG paste is a barrier layer during furnace annealing and prevents drive diffusion of the dopant into the emitter-base isolation region.

35 shows a battery rear process flow option 133A for a junction 119 separated by a laser ablation of an in-situ emitter 108 and a boron doped silicon from a boron doped silicon epitaxy. In this process flow option 133A, the selective emitter contact region is doped (109) by high temperature laser ablation of the APCVD boron doped oxide (109) and the base contact region is doped (114) by high temperature laser ablation of doped oxide which is APCVD, . The process flow may include epitaxial deposition of a selective insitu doped silicon layer at a doping concentration of about 1 x 10 ¹⁷ cm ^-3 to 1 x 10 ¹⁹ cm ^-3 that will act as a front field in the final cell, Start. The doped epitaxial base layer with a doping concentration of 8 x 10 ¹⁴ cm ^-3 to 3 x 10 ¹⁶ cm ^-3 is then deposited to increase the total epitaxial thickness to less than 80 micrometers. The final in situ boron doped field emitter is deposited 180 to a boron concentration of 1 x 10 ¹⁸ cm ^-3 to 1 x 10 ¹⁹ cm ^-3 , less than 1 micrometer. The APCVD boron doped oxide layer is then deposited 150 to a boron concentration of 5% to 10%, which is optimal for doping the emitter contact region. Patterning of the oxide stack and boron doped silicon and pulsed laser desorption are then performed 190 to open the emitter-base isolation region on the silicon. The removed silicon thickness is less than one micrometer exposing the doped base silicon. A doped oxide, APCVD, is then deposited (152) on the boron doped oxide and silicon openings. Patterning of the oxide stack and pulsed laser desorption are then performed (154) to selectively boron-dope and open the emitter contact region on the silicon. Patterning of the phosphorus doped oxide stack and pulsed laser desorption are performed 200 to selectively doping and opening the base contact region on the previously removed silicon region. The high temperature laser ablation process is optimized to drive boron and phosphorus to form a sheet resistance of less than 20 ohm / square at the emitter and base contact regions. The battery backside processing is completed by Al (Si) printing and annealing option # 1 (20) as shown in FIG.

36 shows a cell rear process flow option 133B for a junction 119 separated by an in-situ emitter 108 and a boron doped silicon laser removal from boron doped silicon epitaxy. In this process flow option 133B, the selective emitter contact region is doped 111 by laser annealing of Al (Si) paste and doped 114 by a high temperature laser ablation of the doped oxide which is APCVD. The process flow begins (180) with the epitaxial silicon deposition of the base layer and the in-situ emitter layer after the selective front entire layer. The APCVD undoped oxide layer is then deposited (167). Patterning of the oxide stack and boron doped silicon and pulsed laser desorption are then performed 190 to open the emitter-base isolation region on the silicon. The removed silicon thickness is less than one micrometer exposing the doped base silicon. A doped oxide, APCVD, is then deposited (152) on the APCVD oxide and silicon openings. The APCVD oxide layer stack is then patterned (163) by pulsed laser desorption to open the emitter contact area on the silicon. Patterning of the phosphorus doped oxide stack and pulsed laser desorption are performed 200 to selectively doping and opening the base contact region on the previously removed silicon region. The high temperature laser ablation process is optimized to drive phosphorus to form a sheet resistance of less than 20 ohm / square at the base contact area. Al (Si) printing and annealing option # 1 (20) is performed as shown in FIG. The battery backside machining is completed 160 by driving the aluminum with silicon and selectively laser annealing the Al (Si) emitter fingers to form a selective emitter. The laser annealing process is optimized to drive the aluminum to form a sheet resistance of less than 20 ohm / square in the emitter contact area.

37 shows a cell rear process flow option 133C for a junction 119 separated by an in-situ emitter 108 from boron doped silicon epitaxy and by laser ablation of boron doped silicon. In this process flow option 133C, the selective emitter contact region is doped 112 by sintering annealing of Al (Si) paste and the base contact region is doped 114 by high temperature laser ablation of doped oxide, APCVD, . The process flow is the same as the process flow option 133B except that the last two steps are replaced by Al (Si) printing and annealing option # 2 processing (30) as shown in FIG. The sintered # 1 anneal 34 is optimized to form a sheet resistance of less than 20 ohm / square at the emitter contact area and drive the aluminum.

The foregoing description of the embodiments is provided to enable those skilled in the art to make or use the claimed subject matter. Various modifications to this embodiment will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without resorting to innovative efforts. Accordingly, the claimed subject matter is not limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (22)

A first aluminum-silicon alloy layer on the rear side of the semiconductor solar cell substrate, the first aluminum-silicon alloy layer including a base electrode and an emitter electrode connected to the base region and the emitter region on the semiconductor solar cell substrate;
An electrically insulated backplane layer on said first aluminum-silicon alloy layer, said via-hole including a via-hole approaching said first aluminum-silicon alloy layer, said via hole forming base contact and emitter contact to said first metal layer Wherein the first aluminum-silicon alloy layer is drilled through the backplane layer and is interrupted at the first aluminum-silicon alloy layer at an optional location without being punched through the first aluminum-silicon alloy layer; And
A second metal layer of electrically conductive metal on the electrically insulated backplane layer that is in electrical contact with the first aluminum silicon alloy layer through the via hole;
/ RTI &gt; solar cell structure.
A surface passivation and antireflective coating layer on the front side of the semiconductor absorber;
A heavily doped n-type base layer and a thinner heavily doped p-type emitter junction on the back side of the semiconductor absorber; And
Rear structure;
And a crystal semiconductor absorber layer formed on the semiconductor substrate,
The rear structure comprising: a surface passivation structure having a patterned backside dielectric dopant source and a base and an emitter contact opening;
A first interlocked base and emitter contacted with the base and emitter regions through the base and emitter contact openings and comprising a plurality of directly printed silicon containing aluminum fingers directly over the passivation structure and the patterned rear dielectric dopant source, Metal layer;
The first patterned meshing base and emitter metallization layer including a plurality of via holes landed on the first meshed base and emitter metallization layers and a second patterned mesated base and emitter metallization layer on the surface passivation structure and the patterned rear dielectric dopant source An electrically insulated backplane layer attached to the solar cell structure; And
A second interlocked base and an emitter metallization layer formed on the electrically insulated backplane layer, the patterned conductor including a patterned conductor aligned substantially perpendicular to the first interlocked base and the emitter metallization layer ,
Engaged back contact solar cell structure.
3. The method of claim 2,
Wherein the first interlocked base and emitter metallization layer has a greater number of base and emitter metallization fingers as compared to the second interlocked base and emitter metallization layer.
3. The method of claim 2,
Wherein the semiconductor absorber front passivation and anti-reflective coating layer comprises at least one combination of an amorphous silicon hydrogen compound, an amorphous silicon nitride compound, and an amorphous silicon dioxide compound.
3. The method of claim 2,
Wherein the semiconductor absorber front passivation and antireflective coating layer comprises a combination of at least one of an amorphous silicon oxide compound and an amorphous silicon nitride compound.
3. The method of claim 2,
Wherein the semiconductor absorber front passivation and anti-reflective coating layer comprises a combination of at least one of an amorphous silicon carbide compound and an amorphous silicon nitride compound.
3. The method of claim 2,
Wherein the semiconductor absorber front passivation and antireflective coating layer comprises at least one layer of an amorphous silicon compound having one or a combination of hydrogen, oxygen, and carbon atoms, and at least one layer of an amorphous silicon nitride and an amorphous silicon dioxide compound Interfaced solar cell structure.
3. The method of claim 2,
Wherein the semiconductor absorber front passivation and antireflective coating layer comprises a combination of an amorphous silicon hydrogen compound and an amorphous silicon nitride hydride compound.
Forming a passivation and antireflection coating on the front side of the semiconductor absorber;
Forming a thicker lightly doped n-type base layer and a thinner heavily doped p-type emitter junction on the back side of the semiconductor absorber;
Forming a thicker lightly doped n-type base layer on the rear side of the semiconductor absorber and a rear structure on a thinner heavily doped p-type emitter junction,
Wherein the step
Forming a passivation structure having a base and an emitter contact opening and a patterned backside dielectric dopant source;
A first interlocked base and emitter contacted with the base and emitter regions through the base and emitter contact openings and comprising a plurality of directly printed silicon containing aluminum fingers directly over the passivation structure and the patterned rear dielectric dopant source, To form a metal layer;
The first patterned meshing base and emitter metallization layer including a plurality of via holes landed on the first meshed base and emitter metallization layer and a second patterned mesated base and emitter metallization layer on the surface passivation structure and the patterned rear dielectric dopant source Forming an electrically insulated backplane layer attached to the solar cell structure; And
Forming a second interlocked base and emitter metallization layer on the electrically insulated backplane layer, the patterned conductor including a patterned conductor aligned substantially perpendicular to the first intertwined base and the emitter metallization layer Step;
Contacting the photovoltaic cell structure with the crystalline semiconductor absorber layer.
10. The method of claim 9,
Wherein the first meshed base and the emitter metallization layer are formed by screen printing. &Lt; RTI ID = 0.0 &gt; 11. &lt; / RTI &gt;
10. The method of claim 9,
Wherein the first intertwined base and the emitter metallization layer are formed by ink jet printing. &Lt; Desc / Clms Page number 20 &gt;
10. The method of claim 9,
Wherein the first meshed base and emitter metallization layers are formed by aerosol jet printing. &Lt; RTI ID = 0.0 &gt; 18. &lt; / RTI &gt;
10. The method of claim 9,
Wherein the first intertwined base and the emitter metallization layer are formed by laser transfer printing. &Lt; Desc / Clms Page number 20 &gt;
10. The method of claim 9,
The first interlocked base and emitter metallization layer is formed by direct printing of the silicon-containing aluminum finger directly on the patterned rear dielectric dopant source and passivation structure, drying the paste, burning off the solvent, Contact solar cell structure is formed by subsequent heat treatment of the printed paste for hardening / low resistivity of the structure.
15. The method of claim 14,
Wherein the heat treatment is performed in an in-line belt immediately after metal paste printing and instrument drying, wherein the solvent is burned off and the paste is used to reduce cure / resistivity. Lt; / RTI &gt;
10. The method of claim 9,
Wherein the plurality of direct printed silicon-containing aluminum fingers are formed using an ink comprising aluminum-silicon alloy particles in the form of an aluminum silicon alloy paste or substantially flake-like particles. Lt; / RTI &gt;
10. The method of claim 9,
Wherein the plurality of direct printed silicon-containing aluminum fingers are formed using an ink comprising aluminum-silicon alloy particles in the form of an aluminum silicon alloy paste or substantially spherical particles. How to.
10. The method of claim 9,
Wherein the plurality of direct printed silicon-containing aluminum fingers are formed using an ink comprising aluminum-silicon alloy particles in the form of an aluminum silicon alloy paste or a mixture of substantially flake-like particles and spherical particles. Method for forming a contact solar cell structure.
A silicon-containing aluminum alloy for forming a meshed rear contact base and an emitter contact metallization structure comprising aluminum-silicon alloy particles substantially in the form of a mixture of flake phase particles and spherical phase particles.
20. The method of claim 19,
Wherein the alloy is a paste applicable to screen printing.
20. The method of claim 19,
Wherein the alloy is an ink applicable to ink jet printing.
20. The method of claim 19,
Wherein the alloy is an ink applicable to aerosol jet printing.

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