KR20140126225A

KR20140126225A - Memory device with masked write operation

Info

Publication number: KR20140126225A
Application number: KR1020130101275A
Authority: KR
Inventors: 정회주; 박철성; 오태영; 유장우; 이찬용; 장태성; 한공흠
Original assignee: 삼성전자주식회사
Priority date: 2013-04-18
Filing date: 2013-08-26
Publication date: 2014-10-30
Also published as: KR102032371B1; KR20140126220A

Abstract

The present invention provides a memory device performing a masked write operation. The masked write operation method of the memory device comprises the steps of receiving a masked write command and written data masked after write latency, from a memory controller; generating an internal read command according to the write latency and generating an internal write command according to the masked write data, in response to the masked write command; reading data stored in a plurality of memory cells configured to store the masked write data and performing error detection and correction on the read data, in response to the internal read command; and storing the masked write data in memory cells in response to the internal write command. The internal read command is generated on a rising or falling edge of a set clock more in advance than the write latency and the internal write command is generated after the last data of the masked write data is inputted.

Description

[0001] The present invention relates to a memory device with a masked write operation,

The present invention relates to semiconductor memory devices, and more particularly, to performing a mask write operation in a memory device to improve performance of the memory device.

The memory device employs an ECC (Error Correction Code) circuit to recover error bits. The memory device may perform a masked write operation in which data is not written to a part of the memory cell block constituting the memory cell array in the writing operation. In the masked write operation, a part of the memory cell block in which data is not written holds the existing data, and the new data is written in the remaining memory cell block. In the masked write operation, the existing data is read, the parity bits are modified through the ECC circuit for the existing data and the new data, and the new data and the modified parity bits are written This is important. There is a demand for a memory device capable of safely performing a mask write operation.

SUMMARY OF THE INVENTION The present invention provides a memory device that performs a mask write operation.

A method of operating a memory device in accordance with an aspect of the invention includes the steps of receiving a masked write command, receiving a masked write command and receiving masked write data after a write latency, Reading the data stored in the memory cells corresponding to the address and corresponding to the addressed masked write data in response to the internal read command and detecting and correcting the error with respect to the read data; Generating an internal write command after the last data of the masked write data is input in response to the write command, and storing the masked write data in the memory cells in response to the internal write command.

According to embodiments of the present invention, an internal read command may be generated prior to a predetermined clock rise or falling edge rather than a write latency.

According to embodiments of the present invention, the internal read command may be generated before the tCCD timing rather than the write latency.

According to embodiments of the present invention, an internal read command may be generated in accordance with operating frequency information according to the data rate of the memory device.

According to embodiments of the present invention, a method of operating a memory device includes activating a column select signal and an ECC decode signal coupled to memory cells in response to an internal read command, storing the ECC decode signal in memory cells in response to the column select signal And reading and erasing the data read in response to the ECC decoding signal and data read using the first parity bits.

According to embodiments of the present invention, a method of operating a memory device includes activating a column select signal and an ECC encoded signal that are coupled to memory cells in response to an internal write command, writing the masked write data in response to the ECC encoded signal Generating second parity bits for the read data corresponding to the masked portion of the masked write data among the error corrected read data, and writing the masked write data and the second parity bits in response to the column select signal to the column select signal In the memory cells selected by the memory cell.

According to embodiments of the present invention, the masked write data may be generated by a data mask signal that is input together with the write data input via the data input / output pad (DQ).

A method of operating a memory device according to another aspect of the present invention includes receiving a masked write command and an address, receiving a masked write command and receiving write data masked after a write latency, responding to a masked write command Generating an internal read command after the first data of the write data is input; reading data stored in the memory cells in response to the internal read command corresponding to the address and storing the masked write data; Generating an internal write command after a predetermined time delay by inputting the last data of the write data in response to the masked write command and storing the masked write data in the memory cells in response to the internal write command .

A method of operating a memory device in accordance with another aspect of the present invention includes receiving a masked write command and an address, receiving a masked write command and write data masked after a write latency, Generating an internal read command in response to a clock received in response to an address, reading data stored in memory cells corresponding to the address and masked write data in response to an internal read command, Generating an internal write command after the last data of the write data is input in response to the masked write command and storing the masked write data in the memory cells in response to the internal write command, .

A method of operating a memory device in accordance with yet another aspect of the present invention includes receiving a masked write command and an address, receiving a masked write command and receiving masked write data corresponding to a burst length after a write latency, Generating first and second internal read commands in response to a write latency in response to a masked write command, storing data corresponding to an upper burst length of the write data corresponding to the address in response to the first internal read command Reading and reading the first data stored in the first memory cells to be erroneously detected and corrected for the first data read out; The second data stored in the second memory cells to which the corresponding data is to be stored Generating first and second internal write commands in response to the masked write data in response to the masked write command, generating a first internal write command in response to the first internal write command, Storing the masked write data of the upper burst length in the first memory cells and storing the masked write data of the lower burst length in the second memory cells in response to the second internal write command.

According to embodiments of the present invention, the first and second internal readout instructions may be generated prior to a predetermined clock rising or falling edge rather than a write latency.

According to embodiments of the present invention, the first internal read command may be generated before the 2 * tCCD timing rather than the write latency, and the second internal read command may be generated before the tCCD timing rather than the write latency.

According to embodiments of the present invention, the first internal read command is generated after the first data of the data corresponding to the upper burst length is input, and the second internal read command is generated when the first data of the data corresponding to the lower burst length is input Gt; < / RTI >

According to embodiments of the present invention, a first internal read command is generated in response to a clock received with an address, and a second internal read command is generated after a first internal read command is generated and tCCD timing.

According to embodiments of the present invention, the first internal read command is generated before the tCCD timing rather than the write latency, and the second internal read command is generated after the first internal read command is generated and after the tCCD timing.

According to embodiments of the present invention, the first internal write command is generated after the last data of the data corresponding to the upper burst length is input, and the second internal write command is generated when the last data of the data corresponding to the lower burst length is input Gt; < / RTI >

According to embodiments of the present invention, the first internal write command is generated after the last data of the data corresponding to the upper burst length is input and delayed by a predetermined time, and the second internal write command is generated at the end of the data corresponding to the lower burst length And may be generated after data is input and after a predetermined time delay.

According to embodiments of the present invention, a method of operating a memory device includes activating a first column select signal and a first ECC decode signal coupled to first memory cells in response to a first internal read command, Reading first data and first parity bits stored in first memory cells in response to a select signal, reading first data and first parity bits stored in first memory cells using first data read in response to a first ECC decoded signal, And detecting and correcting errors of the data.

According to embodiments of the present invention, a method of operating a memory device includes activating a second column select signal and a second ECC decode signal coupled to second memory cells in response to a second internal read command, Reading the second data and the second parity bits stored in the second memory cells in response to the select signal, and using the second data and the second parity bits read in response to the second ECC decoded signal, 2 < / RTI > data.

According to embodiments of the present invention, a method of operating a memory device includes activating a first column select signal and a first ECC encoded signal coupled to first memory cells in response to a first internal write command, Generating third parity bits for data corresponding to a masked write data of an upper burst length and a masked write data of an upper burst length of an error corrected first data in response to an encoded signal, And storing the masked write data of the upper burst length and the third parity bits in the memory cells selected by the first column select signal in response to the one column select signal.

According to embodiments of the present invention, a method of operating a memory device includes activating a second column select signal and a second ECC encoded signal coupled to second memory cells in response to a second internal write command, Generating fourth parity bits for the data corresponding to the masked write data of the lower burst length and the masked write data of the lower burst length of the error corrected second data in response to the encoded signal, And storing the masked write data of the lower burst length and the fourth parity bits in the memory cells selected by the second column select signal in response to the second column select signal.

And provides a smooth interface between the memory controller and the memory device through the mask write operations of the present invention.

1 is a diagram illustrating a memory system including a memory device that performs a mask write operation in accordance with various embodiments of the present invention.
Figure 2 is a block diagram illustrating a memory device in accordance with various embodiments of the present invention.
FIG. 3 is a diagram specifically illustrating the bank A in the memory device of FIG. 2. FIG.
Figure 4 is a first example of a timing diagram illustrating the normal read operation of a memory device in accordance with various embodiments of the present invention.
5 is a first example of a timing diagram illustrating a normal write operation of a memory device according to various embodiments of the present invention.
6 is a diagram illustrating a data masking scheme of a memory device in accordance with various embodiments of the present invention.
Figure 7 is a first example of a timing diagram illustrating the mask write operation of a memory device in accordance with various embodiments of the present invention.
Figure 8 is a second example of a timing diagram illustrating the normal read operation of a memory device in accordance with various embodiments of the present invention.
9 is a second example of a timing diagram illustrating a normal write operation of a memory device according to various embodiments of the present invention.
10 is a second example of a timing diagram illustrating a mask write operation of a memory device in accordance with various embodiments of the present invention.
11 is a third example of a timing diagram illustrating a mask write operation of a memory device in accordance with various embodiments of the present invention.
12 is a fourth example of a timing diagram illustrating a mask write operation of a memory device in accordance with various embodiments of the present invention.
13 is a first example of a diagram illustrating a command control logic portion according to various embodiments of the present invention.
14 is a fifth example of a timing diagram illustrating a mask write operation of a memory device in accordance with various embodiments of the present invention.
15 is a sixth example of a timing diagram illustrating a mask write operation of a memory device in accordance with various embodiments of the present invention.
16 is a seventh example of a timing diagram illustrating a mask write operation of a memory device in accordance with various embodiments of the present invention.
17 is an eighth example of a timing diagram illustrating a mask write operation of a memory device according to various embodiments of the present invention.
18 is a second example diagram illustrating a command control logic portion in accordance with various embodiments of the present invention.
19 through 21 are diagrams illustrating a memory module including a DRAM performing a mask write operation in accordance with various embodiments of the present invention.
22 is a diagram illustrating a semiconductor device having a stacked structure including DRAM semiconductor layers for performing a mask write operation according to various embodiments of the present invention.
23 is a diagram illustrating a memory system including a DRAM that performs a mask write operation in accordance with various embodiments of the present invention.
24 is a diagram illustrating a data processing system including a DRAM that performs a mask write operation in accordance with various embodiments of the present invention.
25 is a diagram illustrating a server system including a DRAM that performs a mask write operation in accordance with various embodiments of the invention.
26 is a diagram illustrating a computer system equipped with a DRAM that performs a mask write operation in accordance with various embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are, unless expressly defined in the present application, in an ideal or excessively formal sense It is not interpreted.

The memory capacity of a semiconductor memory device such as a dynamic random access memory (DRAM) is increasing due to the development of manufacturing process technology. As the refinement process technology progresses, the number of defective memory cells also increases. In addition, the DRAM is a memory having finite data retention characteristics. As the process scaling of the DRAM continues, the capacitance value of the cell capacitor becomes smaller, and the bit error rate (BER) increases accordingly . The defective memory cells may be replaced with redundant memory cells and repaired. The redundant repair scheme may not provide sufficient yield. Accordingly, a method of remedying error bits by applying an ECC (Error Correction Code) algorithm to the DRAM has been proposed.

The ECC algorithm detects errors that may occur in the process of writing and reading data, and provides an ECC function that can correct itself. In order to provide data integrity, the DRAM may employ an ECC engine. The ECC engine can perform an ECC operation using parity bits in the process of detecting / correcting errors. Embodiments of the present invention employ an ECC engine in a memory device to relieve error bits to ensure data integrity of a semiconductor memory device.

1 is a diagram illustrating a memory system including a memory device that performs a mask write operation in accordance with various embodiments of the present invention.

The memory system includes a memory controller (100) and a memory device (200). The memory controller 100 controls the memory device 200. The memory controller 100 outputs control signals and data DQs such as a clock CLK, an instruction CMD, an address ADDR, a data strobe signal DQS and a data mask signal DM to the memory device 200, And receives the data strobe signal DQS and the data DQs from the memory device 200. [ The memory controller 100 can issue a read command READ, a write command WRITE and a masked write command MWR to the memory device 200. [

The memory device 200 includes a command control logic unit 220 and an ECC engine unit 260. The command control logic unit 220 can receive a command CMD issued by the memory controller 100 and generate an internal command INT_CMD that controls the operation of the memory device 200 in accordance with the command CMD .

The memory device 200 performs the read operation in response to the read command READ and performs the write operation in response to the write command WRITE and performs the mask write operation in response to the masked write command MWR can do. The mask write operation includes an operation of masking data to be written in a part of the memory cell block constituting the memory cell array in the write operation.

The command control logic unit 220 generates an internal read command INT_RD and an internal write command INT_WR in accordance with the read command READ of the memory controller 100, the write command WRITE or the masked write command MWR . According to the internal read command INT_RD and the internal write command INT_WR, the read operation, the write operation, and the mask write operation of the memory device 200 can be performed.

The ECC engine unit 260 can detect / correct error bits generated in the read data by using parity bits and data read from the memory cells in response to an internal read command INT_RD during a read operation.

The ECC engine unit 260 may perform an ECC encoding operation and generate parity bits for write data to be stored in the memory cells in response to an internal write command during a write operation.

In the masked write operation, the ECC engine unit 260 reads data and first parity bits stored in memory cells in which write data masked in response to an internal read command is stored, and outputs the read data and the first parity The error detection and correction of the read data can be performed using the bits. The ECC engine 260 generates second parity bits for the read data corresponding to the masked write data and the masked write data of the error corrected read data in response to the internal write command, And store the write data and the second parity bits in the memory cells.

Figure 2 is a block diagram illustrating a memory device in accordance with various embodiments of the present invention.

2, the memory device 200 includes a command / address input buffer 210, a command / address control logic 220, bank controllers 230A-230D, memory cell arrays 240A-240D, Driver and data input / output sense amplifier units 250A to 250D, ECC engine units 260A to 260D, an input / output data buffer 270, and an input / output circuit unit 280. [

The memory cell arrays 240A-240D may include banks A through D where a plurality of memory cells are arranged in rows and columns. Each of the banks A to D (240A to 240D) may be connected to a row decoder and a column decoder for selecting word lines and bit lines connected to memory cells. Although an example of a memory device 200 including four banks is illustrated in this embodiment, the memory device 200 may include any number of banks in accordance with embodiments.

In accordance with embodiments, the memory device 200 may be implemented as a DDR SDRAM, a Low Power Double Data Rate (SDPRD) SDRAM, a Graphics Double Data Rate (SDRAM) SDRAM, a Rambus Dynamic Ramdom Access A dynamic random access memory (DRAM) such as a memory, or a memory device performing a masked write operation.

The command / address input buffer 210 can receive the clock (CLK), the command (CMD) and the address (ADDR) received from the memory controller. The command CMD and the address ADDR may be input through the same terminals, so-called CA pads. The command CMD and the address ADDR can be sequentially inputted through the CA pads. The command CMD issued by the memory controller includes a read command RAED, a write command WRITE, and a masked write command MWR. The read command READ indicates a read operation of the memory device 200 and the write command WRITE indicates a write operation of the memory device 200. [ The masked write command MWR instructs a mask write operation to mask data in a part of the memory cell block constituting the memory cell array in the write operation so that data is not written.

In the masked write operation, the existing data is read from the memory cells in which the masked write data is to be stored, and the parity bits are changed through the ECC engine units 260A to 260D for the write data masked with the existing data And may perform an operation of writing the masked write data and the modified parity bits. The masked write operation is called a read-mode pi-write operation by performing a read-modify-write operation in the memory device internally.

The command / address control logic unit 220 receives the command CMD and the address ADDR received through the command / address input buffer 210 to generate an internal command INT_CMD and generate an address signal. The internal command INT_CMD may include an internal read command INT_RD and an internal write command INT_WR. The address signal may include a bank address BA, a row address RA, and a column address CA. The internal command INT_CMD and the address signal BA / RA / CA may be provided to the bank controllers 230A-230D.

Each of the bank control units 230A to 230D may be activated corresponding to the bank address BA. The activated bank control units 230A to 230D can generate the bank control signals in response to the internal command INT_CMD, the row address RA and the column address CA. In response to the bank control signals, the row decoder and the column decoder of the banks A to D (240A to 240D) connected to the activated bank controllers 230A to 230D can be activated.

The row decoders of banks A through D (240A through 240D) can decode the row address RA to enable the word line corresponding to the row address RA. The column addresses CA of the banks A to D (240A to 240D) can be temporarily stored in the column address latches. The column address latch can gradually increase the column address CA in the burst mode. The temporarily stored or progressively increased column address CA may be provided to a column decoder. The column decoder may decode the column address CA to activate the column selection signal CSL corresponding to the column address CA.

Each of the bank controllers 230A to 230D includes an ECC encoding signal ENC for controlling the operation of the ECC engine units 260A to 260D connected to the banks A to D 240A to 240D in response to the bank control signal, Signal (DEC).

The write driver and the data input / output sense amplifier units 250A to 250D sense and amplify the read data output from each of the banks A to D (240A to 240D), and write the data to be stored in each of the banks A to D (240A to 240D) Data can be transmitted.

The ECC engine units 260A to 260D are used for writing data to be stored in each of the banks A to D (240A to 240D) in response to the ECC encoded signal ENC output from the bank controllers 230A to 230D in the write operation An ECC encoding operation may be performed to generate parity bits.

The ECC engine units 260A to 260D read the data read from each of the banks A to D 240A to 240D in response to the ECC decoding signal DEC output from the bank controllers 230A to 230D and the parity bits It is possible to perform an ECC decoding operation to detect / correct error bits generated in the read data.

The ECC engine units 260A to 260D are configured to write data stored in the memory cells in which the masked write data is to be stored in response to the ECC decode signal DEC output from the bank control units 230A to 230D The first parity bits can be read out and the data read out using the read data and the first parity bits can be error-detected and corrected. In addition, the ECC engine units 260A to 260D store the masked write data in response to the ECC encoded signal ENC output from the bank controllers 230A to 230D and the masked write data in the error corrected read data Generate the second parity bits for the corresponding read data, and store the masked write data and the second parity bits in the memory cells.

The input / output data buffer 270 includes circuits for gating data input / output to / from the banks A to D (240A to 240D), data output from the data masking control unit, banks A to D (240A to 240D) And write data latches for writing data to banks A through D (240A-240D).

The input / output data buffer 270 may convert the parallel data bits output from the banks A to D (240A-240D) to the serial data bits through the read data latches. The input / output data buffer 270 may convert write data received serially using the write data latches into parallel data bits. The data masking control unit performs a masking operation on the corresponding data among the write data received via the data input / output pads (DQ [0: 7]) in response to the data masking information (DM_INFO), and sends the masked write data to the ECC engine unit 260A-260D).

The input / output circuit unit 280 receives the serial data bits output from the input / output data buffer 270 and sequentially arranges the serial data bits corresponding to the burst length BL to output the data input / output pads DQ [ 0: 7]). The input / output circuit unit 280 can receive write data corresponding to the burst length BL input from the memory controller and input serially through the data input / output pads DQ [0: 7] together with the data strobe signal DQS . The input / output circuit unit 280 may provide write data of the burst length BL received serially to the input / output data buffer unit 270. [

The input / output circuit unit 280 may provide the data masking information DM_INFO for the write data input together with the data mask signal DM to the data masking control unit through the input / output data buffer 270.

FIG. 3 is a diagram specifically illustrating the bank A in the memory device of FIG. 2. FIG.

3 illustrates the bank controller 240A, the write driver and data input / output sense amplifier 250A, and the ECC engine 260A connected to the bank A 240A, the bank A 240A, and the bank A 240A of FIG. 3 shows a command / address buffer 210 for controlling the operation of the bank A 240A, a command / address control logic 220, an input / output data buffer 270, an input / output circuit 280 and a data masking controller 320 will be described. The description of bank A (240A) can be applied to the remaining banks 240B-240D.

Referring to FIG. 3, bank A 240A includes a plurality of cell block regions 311-314 in which a plurality of memory cells are arranged in rows and columns. These cell block regions 311-314 can be defined in various forms. For example, the cell block areas 311-314 may be defined as areas where data stored in the memory cells of the cell block areas 311-314 are input / output corresponding to the corresponding data input / output pad DQ, May be defined as areas to be input / output corresponding to a burst length (BL) for a write operation.

In this embodiment, the cell block areas 311 to 314 are defined as areas to be input / output corresponding to the burst length BL. The burst length BL means the maximum number of memory cells that can be accessed for the corresponding read or write command. The burst length can be variously set to BL = 4, BL = 8, BL = 16, BL = 32, and the like. For example, if BL = 16, for convenience of description, a cell block in which data corresponding to the first burst length BL0 is written / read in the cell block area 311-314 is referred to as a BL0 cell block 311, A cell block for which data corresponding to the second burst length BL1 is written / read is referred to as a BL1 cell block 312 and a cell block for which data corresponding to the 16th burst length BL15 is written / Quot; BL15 cell block 313 ".

In addition, the cell block areas 311 to 314 may include cell blocks in which parity bits used in the process of detecting / correcting errors according to the ECC operation are stored. For convenience of explanation, a cell block in which a parity bit is stored is referred to as an ECCP cell block 314.

The cell block areas 311-314 may include BL0-BL15 cell blocks 311-313 and an ECCP cell block 314. The BL0 to BL15 cell blocks 311 to 313 and the ECCP cell block 314 may be connected to the write driver and the data input and output sense amplifier unit 250A and the first data lines GIO and GIOP.

Each of the first data lines GIO and GIOP consists of a pair of data lines that are in a complementary relationship with each other. BL15 cell blocks 311-313 and ECCP cell block 314 when the memory device 200 includes eight data input / output pads, so called eight DQ pads DQ [0: 7] Each of which may be connected to eight first data lines GIO and GIOP. In this embodiment, read data transfer from the BL0-BL15 cell blocks 311-313 and the ECCP cell block 314 via the eight first data lines GIO and GIOP and the transfer of read data from the BL0- 311-313) and the ECCP cell block 314, the eight first data lines GIO and GIOP are separately displayed.

The total number of the first data lines GIO connected to the BL0-BL15 cell blocks 311-313 is 16 * 8 = 128, and these first data lines GIO ultimately have eight DQ pads (DQ [0: 7]). That is, 128-bit data on the first data lines GIO connected to the BL0-BL15 cell blocks 311-313 are connected to the memory device 200 through eight DQ pads DQ [0: 7] And can be input / output to / from the outside. At this time, each DQ pad (DQ [0: 7]) can input / output 16-bit data corresponding to the burst length BL = 16.

The number of the first data lines GIOP connected to the ECCP cell block 314 is eight. This is in accordance with a Hamming ECC algorithm using 8-bit parity bits for the operation of detecting and correcting error bits for 128-bit data of BL0-BL15 cell blocks 311-313.

Depending on the ECC algorithm applied to perform error detection and correction, the number of error correction unit data bits and the number of parity bits may vary. For example, 6-bit parity bits may be used for 32-bit data and 7-bit parity bits may be used for 64-bit data. Therefore, the number of first data lines GIO connected to the BL0-BL15 cell blocks 311-313 and the number of first data lines GIOP connected to the ECCP cell block 314 is determined by the ECC algorithm Can be designed differently.

The command / address input buffer 210 can receive a read command (RAED), a write command (WRITE), or a masked write command (MWR) issued by the memory controller and receive the address ADDR.

The command / address control logic unit 220 receives the read command RAED, the write command WRITE or the masked write command MWR and the address ADDR through the command / address input buffer 210, (INT_CMD) and generate the address signal BA / RA / CA.

The bank control unit 230A is activated in response to the bank address BA and can generate the bank control signals in response to the internal command INT_CMD, the row address RA and the column address CA. In response to the bank control signal, the bank controller 230A can activate the row decoder and the column decoder of the bank A 240A. The row decoder can decode the row address RA to enable the word line corresponding to the row address RA. The column decoder may decode the column address CA to activate the column selection signal CSL corresponding to the column address CA. The bank control section 230A may generate an ECC encoding signal ENC and an ECC decoding signal DEC that control the operation of the ECC engine section 260A in response to the bank control signal.

The write driver and the data input / output sense amplifier unit 250A receive the data bits read from the BL0-BL15 cell blocks 311-313 and the ECCP cell block 314 corresponding to the row address RA and the column address CA, And transmit the write data bits and the parity bits to be stored in the BL0-BL15 cell blocks 311-313 and the ECCP cell block 314, respectively. The 128-bit parallel data bits read out from each of the BL0 to BL15 cell blocks 311 to 313 can be transferred to the first data line GIO through the data input / output sense amplifier. The 8-bit parity bits read out from the ECCP cell block 314 are detected and amplified by the data input / output sense amplifier and transferred to the first data line (GIOP). The sense amplified data transferred to the first data lines GIO and GIOP are provided to the ECC engine unit 260A.

The ECC engine unit 260A reads out the read data from each of the BL0 to BL15 cell blocks 311 to 313 corresponding to the row address RA and the column address CA in response to the ECC decoding signal DEC Error detection and correction operations can be performed using 128-bit parallel data bits and 8-bit parity bits read from the ECCP cell block 111. [ The ECC engine unit 260A generates syndrome data by calculating 128-bit parallel data bits and 8-bit parity bits, and generates syndrome data using 128 bits on the first data lines GIO [0: 127] To detect error bit positions, to correct error bit data, and to output error corrected parallel data bits. The error-corrected parallel data bits may be transferred to the input / output data buffer 270 and the data masking control unit 320 via the second data lines FDIO.

The ECC engine unit 260A writes data to be stored in the BL0 to BL15 cell blocks 311 to 313 corresponding to the row address RA and the column address CA in response to the ECC encoding signal ENC in the write operation And generate parity bits for the data. The ECC engine unit 260A may transmit the parity bits to the ECCP cell block 314 through the first data line GIOP and the write driver.

In the masked write operation, the ECC engine unit 260A, in response to the ECC decoding signal DEC, outputs the row address RA and column address CA in each of the BL0 to BL15 cell blocks 311 to 313 corresponding to the column address CA The parallel data bits of 128 bits to be read and the first parity bits of 8 bits to be read out of the ECCP cell block 111 can be received. The ECC engine 260A may perform error detection and correction on 128 bits of parallel data bits read out using 128 bits of parallel data bits and 8 bits of first parity bits. In response to the ECC encoding signal ENC, the ECC engine unit 260A reads the masked write data provided from the input / output data buffer 270 and the read data corresponding to the masked portion of the write data masked in the error corrected read data To generate the second parity bits. The ECC engine unit 260A is provided with data masked in the memory cells of the BL0-BL15 cell blocks 311-313 and the ECCP cell block 111 corresponding to the row address RA and the column address CA, Bits.

The error-corrected parallel data bits output from the ECC engine 260A may be provided to the input / output data buffer 270 via the second data line FDIO. The input / output data buffer 270 receives the 128-bit error-corrected parallel data bits in response to the clock signal and the address signal, and converts the serial data bits into, for example, 64-bit serial data bits. Or the input / output data buffer 270 may receive and output 128-bit error-corrected parallel data bits, for example, 32-bit or 16-bit serial data bits.

The input / output data buffer 270 may convert the write data received serially through the input / output circuit unit 280 into parallel data bits. The input / output data buffer 270 may convert, for example, data bits of burst length BL = 16, which are received serially into eight data input / output pads DQ [0: 7], into 128 bits of parallel data bits. The input / output data buffer 270 may convert the data into the burst length data in response to the clock signal and the address signal. That is, data (DATA_BL0) corresponding to the first burst length, data (DATA_BL1) corresponding to the second burst length, , And data (DATA_BL15) corresponding to the 16th burst length, into 128-bit parallel data bits. Each of the data DATA_BL0 to DATA_BL15 corresponding to the first to the 16th burst lengths may be provided to the data masking control unit 320 through the third data lines SDIO.

The input / output circuit unit 280 receives the serial data bits output from the input / output data buffer 270 and sequentially arranges the serial data bits corresponding to the burst length BL = 16, for example, with the data strobe signal DQS, (DQ [0: 7]).

The input / output circuit unit 280 receives write data, for example, corresponding to the burst length BL = 16, input serially through the data input / output pads DQ [0: 7] together with the data strobe signal DQS from the memory controller . The input / output circuit unit 280 can provide write data of the burst length BL = 16 received serially to the input / output data buffer unit 270.

The input / output circuit unit 280 may provide the data masking information for the write data input together with the data mask signal DM to the data masking control unit 320 through the input / output data buffer 270. The data mask signal DM is a signal that is input serially through the data input / output pads DQ [0: 7], for example, selectively masking the data bits of the burst length BL = 16. Accordingly, the data masking information is information on the corresponding burst length that is selectively masked. The first burst length masking signal DM_BL0, the second burst length masking signal DM_BL1, , And a 16th burst length masking signal DM_BL15.

The data masking control unit 320 receives the data corresponding to the first to the 16th burst lengths received through the third data lines SDIO in response to the first to the 16th burst length masking signals DM_BL0, DM_BL1 and DM_BL15 Data_BL0 to DATA_BL15) can be masked with respect to the corresponding burst length. The masked write data is provided to the ECC engine unit 260A, and the ECC operation according to the mask write operation can be performed.

The read operation, the write operation, and the mask write operation of the memory device 200 according to the read command (READ), the write command (WRITE) and the masked write command (MWR) of the memory controller are specifically described do.

4 to 18, in order to distinguish from the masked write operation, for convenience of explanation, the read operation is referred to as a normal read operation and the write operation is referred to as a normal write operation. 4 to 18, the normal read operation, the normal write operation, or the mask write operation of the memory device 200 is described in connection with the bank A (240A) of FIG.

The memory device 200 can input / output data corresponding to the burst length BL to eight DQ pads DQ [0: 7]. For convenience of explanation, FIG. 4 to FIG. 18 show the timing of input / output of data corresponding to the burst length BL to one DQ pad.

The memory device 200 may receive an address signal including a bank address, a row address, and a column address. 4 to 18, the address signal CAS2 is described as a column address, and the column selection signal CSL corresponding to the column address is described as being activated.

The operation of the memory device 200 can be divided into high frequency operation and low frequency operation. 4 to 18, high frequency operation is set when operating at a data rate of about 3200 Mpbs, and low frequency operation is set when operating at a data rate of about 533 Mbps. According to embodiments, the high frequency operation and the low frequency operation of the memory device 200 may be variously configured at 2400, 2133, 1867, 1600, 800 Mbps data rates, and so on.

The read latency RL of the memory device 200 means a clock cycle delay between the read command READ and the first bit of valid output data and the write latency WL indicates a write command WRITE, Or the clock cycle delay between the masked write command (MWR) and the first bit of valid write data. 4 to 18, the readout latency RL is a period of time from the last rising edge of the clock CLK received together with the address signal CAS2 after the read command READ and the address signal CAS2 are sequentially input, And the clock cycle delay between bits. In addition, the write latency WL is a write address from the last rising edge of the clock CLK received together with the address signal CAS2 after the write command WRITE or the masked write command MWR and the address signal CAS2 are sequentially inputted, And the clock cycle delay between the first bits of data.

4 to 18, the read latency RL or the write latency WL is described as the clock cycle delay between the first bit of valid read or write data from the last rising edge of the clock CLK received together with the address signal CAS2, The command CMD and the address ADDR are input through the CA pads of the memory device 200. [

Figure 4 is a first example of a timing diagram illustrating the normal read operation of a memory device in accordance with various embodiments of the present invention.

Referring to FIG. 4, a high frequency normal read operation of the memory device is described. The normal read operation may be initiated by receiving a read command (READ) issued from the memory controller. The memory device can receive the read command READ in accordance with the rising or falling edge of the clock CLK and can receive the address signal CAS2 following the read command READ.

Read data corresponding to the burst length BL may be output to the DQ pad after the clock (CLK) cycle of the read latency (RL) from the last rising edge of the clock (CLK) received together with the address signal (CAS2) . The read data (0-1-2-3-4-5-6-7-8-9-abcdef) corresponding to the burst length BL output to the DQ pad corresponds to the rise and fall edges of the data strobe signal DQS Can be output. In this embodiment, the read latency RL = 28 is set as an example, and the burst length BL is set to 16.

An internal read command INT_RD may be generated in response to the last rising edge of the clock CLK received together with the address signal CAS2 in the memory device before outputting the read data to the outside of the memory device via the DQ pad. In response to the internal read command INT_RD, the column select signal RD_CSL connected to the memory cells corresponding to the address signal CAS2 can be activated. Also, the ECC decoding signal DEC can be generated in response to the internal read command INT_RD.

The column selection signal RD_CSL may be activated after the time tRD2CSL required from the last rising edge of the clock CLK received together with the address signal CAS2 to the activation of the column selection signal RD_CSL. In response to the activation of the column selection signal RD_CSL, the data stored in the BL0-BL15 cell blocks and the parity bits stored in the ECCP cell block can be read out.

In response to the ECC decoding signal DEC, the ECC engine unit generates syndrome data using the read data output from the BL0-BL15 cell blocks and the parity bits output from the ECCP cell block, calculates the error bit position, The data corresponding to the bit position can be corrected, and the error-corrected data can be output.

The error-corrected data is sequentially arranged with data bits (0-1-2-3-4-5-6-7-8-9-abcdef) corresponding to the burst length BL = 16, and the data strobe signal DQS and Can be output to the data input / output pads DQ [0: 7].

5 is a first example of a timing diagram illustrating a normal write operation of a memory device according to various embodiments of the present invention.

Referring to Fig. 5, the normal write operation of the high frequency of the memory device is described. The normal write operation can be started by receiving a write command (WRITE) issued from the memory controller. The memory device can receive the write command WRITE in accordance with the rising or falling edge of the clock CLK and can receive the address signal CAS2 following the write command WRITE.

The write data corresponding to the burst length BL can be input to the DQ pad after the write latency (WL) from the last rising edge of the clock (CLK) received together with the address signal (CAS2). The write data (0-1-2-3-4-5-6-7-8-9-abcdef) corresponding to the burst length BL input through the DQ pad is supplied to the rising and falling edges of the data strobe signal DQS And can be input in accordance with. In this embodiment, the write latency WL is set to 28, and the burst length BL is set to 16, for example.

When the write data corresponding to the burst length BL = 16 is input through the DQ pad, the internal write command INT_WR may be generated in accordance with the rising edge of the clock CLK after the last write data is input in the memory device . The ECC encoding signal ENC may be generated in response to the internal write command INT_WR. In response to the internal write command INT_WR, the column select signal WR_CSL connected to the memory cells corresponding to the address signal CAS2 can be activated. The column selection signal WR_CSL can be activated after the time tLastDataIn2CSL required from the rising edge of the clock CLK to the activation of the column selection signal WR_CSL after the last write data input.

In response to the ECC encoding signal ENC, the ECC engine unit generates parity bits for the write data (0-1-2-3-4-5-6-7-8-9-abcdef) input via the DQ pad . The write data (0-1-2-3-4-5-6-7-8-9-abcdef) and the parity bits are applied to the BL0-BL15 cell blocks selected by the column select signal (WR_CSL) and the ECCP cell block Lt; / RTI >

6 is a diagram illustrating a data masking scheme of a memory device in accordance with various embodiments of the present invention.

Referring to FIG. 6A, in accordance with the masked write command (MWR) of the memory controller, a mask write operation can be performed in which some of the write data of the memory device is masked so as not to be written. The write data (0-1-2-3-4-5-6-7-8-9) corresponding to the burst length BL, for example, BL = 16, is written into eight DQ pads DQ [0: 7] -abcdef) can be input serially. The data mask signal DM can be input together with the write data input to the DQ pads DQ [0: 7]. For example, the data mask signal DM may be input at a logic high level (i.e., "1") to mask data corresponding to the second burst length BL1 in the write data.

The memory device controls so that data corresponding to the second burst length BL1 of the write data is not written to the BL1 cell block and the remaining write data other than the data of the second burst length BL1 is written to the BL0 and BL2 to BL15 cell blocks . The memory device can write the write data in which the data corresponding to the second burst length BL1 is masked into the BL0, BL2-BL15 cell blocks.

Figure 7 is a first example of a timing diagram illustrating the mask write operation of a memory device in accordance with various embodiments of the present invention.

Referring to Fig. 7, the high frequency masked write operation of the memory device is described. The masked write operation may be initiated by receiving a masked write command (MWR) issued from the memory controller.

On the other hand, the memory controller issues a write command (WRITE) in order to instruct the normal write operation of the memory device in Fig. In the normal write operation of FIG. 5, the write data may be stored in the BL0-BL15 cell blocks selected by the column select signal WR_CSL after tLastDataIn2CSL time after the last write data input. In the mask write operation of the present embodiment, it can be expected that the masked write data is stored in the BL0-BL15 cell blocks selected by the column select signal WR_CSL after the last write data input tLastDataIn2CSL. As a result, it can be expected that the normal write operation end and the masked write operation end of the memory device can be performed at the same time after the write data input. Thus, in the memory controller, a command for the next operation of the memory device can be issued without distinguishing between the normal write operation and the masked write operation. That is, a smooth interface between the memory controller and the memory device will be possible.

The memory device can receive the masked write command MWR in accordance with the rising or falling edge of the clock CLK and receive the address signal CAS2 following the masked write command MWR.

Write data can be input to the DQ pad after the write latency WL from the last rising edge of the clock (CLK) received with the address signal (CAS2). (0-1-2-3-4-5-6) corresponding to the burst length BL, for example, BL = 16, in accordance with the rising and falling edges of the data strobe signal DQS after the write latency WL, -7-8-9-abcdef) can be input to the DQ pad.

The data mask signal DM may be input at a logic high level (i.e., "1") to mask data corresponding to the second burst length BL1 in the write data. Accordingly, write data in which data corresponding to the second burst length BL1 is masked can be input.

The memory device can control to perform a Read-Modify-Write operation internally in response to a MWR command received from the memory controller. The memory device may generate an internal read command INT_RD and an internal write command INT_WR in response to the masked write command MWR.

The internal read command INT_RD may be generated before a predetermined clock (CLK) rising or falling edge than the write latency WL = 14. For example, the internal read command INT_RD may be generated before the tCCD timing than the write latency WL = 14. The tCCD timing can be defined as a cascade-to-cascade delay time.

In response to the internal read command INT_RD, the column selection signal RD_CSL corresponding to the address signal CAS2 and connected to the memory cells into which the write data is written can be activated, and the ECC decode signal DEC can be generated. The column selection signal RD_CSL may be activated after the time tRD2CSL required from the last rising edge of the clock CLK received together with the address signal CAS2 to the activation of the column selection signal RD_CSL. In response to the activation of the column selection signal RD_CSL, the data stored in the BL0-BL15 cell blocks and the parity bits stored in the ECCP cell block can be read out.

In response to the ECC decoding signal DEC, the ECC engine unit can perform error bit detection / correction using the read data output from the BL0-BL15 cell blocks and the parity bits output from the ECCP cell block. Thus, the ECC engine unit can hold the read data of the error-corrected BL0-BL15 cell blocks.

The internal write command INT_WR can be generated in accordance with the rising edge of the clock CLK after the last data of the write data corresponding to the burst length BL = 16 is input through the DQ pad.

The ECC encoding signal ENC may be generated in response to the internal write command INT_WR. In response to the internal write command INT_WR, the column select signal WR_CSL connected to the memory cells corresponding to the address signal CAS2 can be activated

The column selection signal WR_CSL activated by the internal write command INT_WR is the same column selection signal as the column selection signal RD_CSL activated by the internal read command INT_RD. This is because the RD_CSL and WR_CSL column selection signals are activated in response to the same address signal CAS2. For convenience of explanation, it is referred to as an RD_CSL column selection signal in relation to a read operation and is referred to as a WR_CSL column selection signal in relation to a write operation.

In response to the ECC encoding signal (ENC), the ECC engine compares the data corresponding to the second burst length BL1 with the masked write data and the ECC decoded signal (DEC) to obtain BL1 It is possible to generate parity bits for the read data of the cell block.

After the time tLastDataIn2CSL required from the rising edge of the clock CLK to the activation of the column select signal WR_CSL after the last write data input, the column select signal WR_CSL can be activated.

In response to the column select signal WR_CSL, the write data and the parity bits masked with the data corresponding to the second burst length BL1 are input to the BL0, BL2-BL15 cell blocks and the ECCP cell block Lt; / RTI >

The mask write operation of the memory device according to the present embodiment may involve timing constraints as shown in Tables 1 and 2 in the interface with the memory controller. Table 1 shows the relationship between the write command WRITE or the write command WRITE for the same bank after the memory controller applies the current normal write command WRITE or the masked write command MWR to one bank of the memory device. (MWR) is applied.

Current command Next Command Write command
(WRITE) Masked Light Command
(RMW) Write command
(WRITE) tCCD tCCDMW Masked Light Command
(RMW) tCCD tCCDMW

In Table 1, it can be seen that the tCCD timing constraint is accompanied after applying the current normal write command WRITE or the masked write command MWR until the next write command WRITE is applied. It can be seen that the tCCDMW timing constraint is accompanied after applying the current normal write command WRITE or the masked write command MWR until the next masked write command MWR is applied. The tCCD timing can be defined as a cascade-to-cascade delay time. The tCCDMW timing is the time required to complete the write operation of the write data, and can be defined as 4 * tCCD timing.

Table 2 shows the relationship between the write command WRITE and the mask write command WRITE for the other bank after the memory controller applies the current normal write command WRITE or the masked write command MWR to one bank of the memory device. (MWR) is applied.

Current command Next Command Write command
(WRITE) Masked Light Command
(RMW) Write command
(WRITE) tCCD tCCD Masked Light Command
(RMW) tCCD tCCD

In Table 2, it can be seen that the tCCD timing constraint is followed until the next write command WRITE is applied after the current normal write command WRITE or the masked write command MWR is applied. It can be seen that the tCCD timing constraint is accompanied even after the application of the current normal write command WRITE or the masked write command MWR until the next masked write command MWR is applied. Thereby, the memory controller can issue a command for the next write operation of the memory device without timing restriction according to the normal write command WRITE and the masked write command MWR, so that a smooth interface between the memory controller and the memory device It will be possible.

Figure 8 is a second example of a timing diagram illustrating the normal read operation of a memory device in accordance with various embodiments of the present invention.

Referring to Fig. 8, a low frequency normal read operation of the memory device is described. The normal read operation may be initiated by receiving a read command (READ) issued from the memory controller. The memory device can receive the read command READ in accordance with the rising or falling edge of the clock CLK and can receive the address signal CAS2 following the read command READ. In this embodiment, the read latency RL = 10 is set as an example, and the burst length BL is set to 16.

Corresponding to the burst length BL = 16 after a clock (CLK) cycle of readout latency RL = 10 from the last rising edge of the clock CLK received together with the address signal CAS2, 4-5-6-7-8-9-abcdef) may be output to the DQ pad. The read data (0-1-2-3-4-5-6-7-8-9-abcdef) corresponding to the burst length BL output to the DQ pad corresponds to the rise and fall edges of the data strobe signal DQS Can be output.

An internal read command INT_RD may be generated in response to the last rising edge of the clock CLK received together with the address signal CAS2 in the memory device before outputting the read data to the outside of the memory device via the DQ pad. The internal read command INT_RD may be generated in response to the last rising edge of the clock CLK received with the address signal CAS2 based on the read latency RL = 10 information.

In response to the internal read command INT_RD, the column select signal RD_CSL connected to the memory cells corresponding to the address signal CAS2 can be activated. Also, the ECC decoding signal DEC can be generated in response to the internal read command INT_RD.

In response to the ECC decoding signal DEC, the ECC engine unit generates syndrome data using the read data output from the BL0-BL15 cell blocks and the parity bits output from the ECCP cell block, calculates the error bit position, It is possible to correct the data corresponding to the position and output the error-corrected data.

9 is a second example of a timing diagram illustrating a normal write operation of a memory device according to various embodiments of the present invention.

Referring to Fig. 9, the normal write operation of the low frequency of the memory device is described. The normal write operation can be started by receiving a write command (WRITE) issued from the memory controller. The memory device can receive the write command WRITE in accordance with the rising or falling edge of the clock CLK and can receive the address signal CAS2 following the write command WRITE. In this embodiment, the write latency WL is set to 6, and the burst length BL is set to 16, for example.

After the write latency WL = 6 from the last rising edge of the clock (CLK) received together with the address signal (CAS2), write data (0-1-2-3-4-5-6- 7-8-9-abcdef) may be input to the DQ pad. The write data (0-1-2-3-4-5-6-7-8-9-abcdef) corresponding to the burst length BL input through the DQ pad is supplied to the rising and falling edges of the data strobe signal DQS And can be input in accordance with.

When the write data (0-1-2-3-4-5-6-7-8-9-abcdef) corresponding to the burst length BL = 16 is inputted through the DQ pad, the last write data is input in the memory device The internal write command INT_WR may be generated in accordance with the rising edge of the clock CLK. The internal write command INT_WR may be generated in accordance with the last rising edge of the clock CLK received together with the address signal CAS2 based on the write latency WL = 6 information.

The ECC encoding signal ENC may be generated in response to the internal write command INT_WR. In response to the internal write command INT_WR, the column select signal WR_CSL connected to the memory cells corresponding to the address signal CAS2 can be activated. The column selection signal WR_CSL can be activated after the time tLastDataIn2CSL required from the rising edge of the clock CLK to the activation of the column selection signal WR_CSL after the last write data input.

The ECC engine unit may generate parity bits for the write data (0-1-2-3-4-5-6-7-8-9-abcdef) input via the DQ pad in response to the ECC encoding signal ENC have. The write data (0-1-2-3-4-5-6-7-8-9-abcdef) and the parity bits are applied to the BL0-BL15 cell blocks selected by the column select signal (WR_CSL) and the ECCP cell block Lt; / RTI >

10 is a second example of a timing diagram illustrating a mask write operation of a memory device in accordance with various embodiments of the present invention.

Referring to FIG. 10, the low frequency masked write operation of the memory device is described. The masked write operation may be initiated by receiving a masked write command (MWR) issued from the memory controller. The memory device can receive the masked write command MWR in accordance with the rising or falling edge of the clock CLK and receive the address signal CAS2 following the masked write command MWR. In this embodiment, the write latency WL is set to 6, and the burst length BL is set to 16, for example.

Write data can be input to the DQ pad after the write latency WL = 6 from the last rising edge of the clock (CLK) received with the address signal (CAS2). After the write latency WL = 6, the write data (0-1-2-3-4-5-6-7-8-9) corresponding to the burst length BL = 16 in accordance with the rising and falling edges of the data strobe signal DQS -abcdef) can be input to the DQ pad.

In response to the masked write command (MWR), the memory device can issue an internal read command (INT_RD) and an internal write command (INT_WR).

The internal read command INT_RD may be generated in response to the rising edge of the clock CLK after the first data of the write data corresponding to the burst length BL = 16 is input through the DQ pad. The internal read command INT_RD may be generated in accordance with the rising edge of the clock CLK after the first data of the write data is input based on the write latency WL = 6 information.

In response to the internal read command INT_RD, the column selection signal RD_CSL connected to the memory cells corresponding to the address signal CAS2 is activated, and the ECC decoding signal DEC can be generated. The column selection signal RD_CSL may be activated after the time tRD2CSL required from the last rising edge of the clock CLK received together with the address signal CAS2 to the activation of the column selection signal RD_CSL. In response to the activation of the column selection signal RD_CSL, the data stored in the BL0-BL15 cell blocks and the parity bits stored in the ECCP cell block can be read out.

The internal write command INT_WR can be generated in accordance with the rising edge of the clock CLK after the last data of the write data corresponding to the burst length BL = 16 is input through the DQ pad. The internal write command INT_WR may be generated in accordance with the rising edge of the clock CLK after the last data of the write data is inputted based on the write latency WL = 6 information.

The column selection signal WR_CSL can be activated after the time tLastDataIn2CSL required from the rising edge of the clock CLK to the activation of the column selection signal WR_CSL after the last write data input.

11 is a third example of a timing diagram illustrating a mask write operation of a memory device in accordance with various embodiments of the present invention.

Referring to Fig. 11, the high frequency masked write operation of the memory device is described. The masked write operation may be initiated by receiving a masked write command (MWR) issued from the memory controller. The memory device can receive the masked write command MWR in accordance with the rising or falling edge of the clock CLK and receive the address signal CAS2 following the masked write command MWR. In this embodiment, the write latency WL is set to 14 and the burst length BL is set to 16 as an example.

After the write latency WL = 14 from the last rising edge of the clock (CLK) received with the address signal (CAS2), the write data (0-1-2-3-4-5-6-7-8-9 -abcdef) can be input. After the write latency WL = 14, the write data (0-1-2-3-4-5-6-7-8-9) corresponding to the burst length BL = 16 in accordance with the rising and falling edges of the data strobe signal DQS -abcdef) can be input to the DQ pad.

The internal read command INT_RD may be generated in response to the rising edge of the clock CLK after the first data of the write data corresponding to the burst length BL = 16 is input through the DQ pad.

The internal write command INT_WR may be generated in accordance with the rising edge of the clock CLK after the last data of the write data corresponding to the burst length BL = 16 is input through the DQ pad and delayed by a predetermined time tdelay.

The column selection signal WR_CSL can be activated after the time tDelayLastDataIn2CSL required from the rising edge of the clock CLK to the activation of the column selection signal WR_CSL after the last write data input.

12 is a fourth example of a timing diagram illustrating a mask write operation of a memory device in accordance with various embodiments of the present invention.

Referring to Fig. 12, a high frequency masked write operation of the memory device is described. The masked write operation may be initiated by receiving a masked write command (MWR) issued from the memory controller. The memory device can receive the masked write command MWR in accordance with the rising or falling edge of the clock CLK and receive the address signal CAS2 following the masked write command MWR. In this embodiment, the write latency WL is set to 14 and the burst length BL is set to 16 as an example.

After the write latency WL = 14 from the last rising edge of the clock (CLK) received with the address signal (CAS2), the write data (0-1-2-3-4-5-6-7-8-9 -abcdef) can be input. After the write latency WL = 14, the write data (0-1-2-3-4-5-6-7-7) corresponding to the burst length BL, for example, BL = 16, is written in accordance with the rising and falling edges of the data strobe signal DQS, 8-9-abcdef) can be input to the DQ pad.

The internal read command INT_RD may be generated along with the last rising edge of the clock CLK received with the address signal CAS2.

13 is a first example of a diagram illustrating a command control logic portion according to various embodiments of the present invention. The command control logic unit can generate an internal command INT_CMD on the command CMD received from the memory controller. In this embodiment, a command control logic unit that generates an internal read command INT_RD and an internal write command INT_WR in response to a masked write command MWR will be described. The operation of the command control logic section can be described in connection with the masked write operation described in Figs. 7, 10, 11, and 12.

13, the command control logic section may include a plurality of flip-flops 1310, 1320, 1330, 1340 and NAND gates 1360, ogates 1370, and read range control 1380 . Each of the flip-flops 1310, 1320, 1330, 1340, 1350 may generate a control signal for the corresponding write latency WL in response to a clock CLK. NAND gates 1360 may perform a logical AND operation on the masked write command (MWR) and the corresponding write latency WL. The corresponding write latency WL = 0, 1, ... The output signal of NAND gate 1360 generated according to n, n may be provided to OR gate 1370. The output signal of the NAND gate 1360 generated for the write latency WL = n is input to the OR gate 1370 and the OR gate 1370 outputs the output signal of the NAND gate 1360 and the write latency WL = n- 1 < / RTI > The output of the O gate 1370 is provided to a flip flop 1310 and the flip flop 1310 performs a gating operation on the output of the O gate 1370 in response to the clock CLK to generate a write latency WL = A control signal can be generated.

7, 11, 12, and 13, which explain the mast write operations of the present invention, the case of the write latency WL = 14 is described. For the write latency WL = 14, the flip-flop 1330 generates a control signal of the write latency WL = 14, the flip-flop 1320 generates a control signal of the write latency WL = (14-8) (1340) may generate a control signal of write latency WL = (14 + 8).

The control signal of the write latency WL = (14-8) is a signal preceded by 8 clock (CLK) cycles of the control signal of the write latency WL = 14, and is a signal preceded by tCCD before the write latency WL = 14. The control signal of the write latency WL = (14 + 8) is a signal 8 clock (CLK) cycles later than the control signal of the write latency WL = 14 and is a signal tCCD behind the write latency WL = 14.

The control signal of the write latency WL = (14-8) output from the flip-flops 1320 and 1330 and the control signal of the write latency WL = 14 may be provided to the read range control unit 1380. The read range control unit 1380 performs a logical operation on the control signals of the write latency WL = (14-8), WL = 14 of the flip-flops 1320 and 1330 and the frequency information signal INFO_FREQ, (INT_RD). The frequency information signal INFO_FREQ may be provided based on high frequency operation or low frequency operation according to the data rate of the memory device.

The readout range control unit 1380 can generate the internal read command INT_RD by being controlled by the latency information signal INFO_WL instead of the frequency information signal INFO_FREQ. The latency information signal INFO_WL is provided based on the latency, and the internal read command INT_RD may be generated in conjunction with the latency.

The control signal of the write latency WL = (14 + 8) output from the flip-flop 1340 can be generated as the internal write command INT_WR.

14 is a fifth example of a timing diagram illustrating a mask write operation of a memory device in accordance with various embodiments of the present invention.

14, the masked write operation for the high frequency burst length BL = 32 of the memory device is described. The masked write operation may be initiated by receiving a masked write command (MWR) issued from the memory controller.

Write data can be input to the DQ pad after the write latency WL from the last rising edge of the clock (CLK) received with the address signal (CAS2). After the write latency WL, for example, WL = 28, two groups of write data (0-1-2-3-4-5-6) corresponding to the burst length BL = 32 are set in accordance with the rising and falling edges of the data strobe signal DQS -7-8-9-abcdef) may be input to the DQ pad. For convenience of explanation, the write data (0-1-2-3-4-5-6-7-8-9-abcdef) of the first group is referred to as upper BL write data, and the write data of the second group 0-1-2-3-4-5-6-7-8-9-abcdef) is referred to as lower BL write data.

The data mask signal DM is a logic high signal for masking the data corresponding to the second burst length BL1 in the upper BL write data (0-1-2-3-4-5-6-7-8-9-abcdef) Level (i.e., "1"). Thus, the upper BL write data in which the data corresponding to the second burst length BL1 is masked can be input.

In response to the masked write command MWR, the memory device may generate the first and second internal readout instructions INT_RD0 and INT_RD1 and the first and second internal write instructions INT_WR0 and INT_WR1. The first internal read command INT_RD0 and the first internal write command INT_WR0 relate to the read operation and the write operation for the upper BL write data and the second internal read command INT_RD1 and the second internal write command INT_WR1, May be related to the read operation and the write operation for the lower BL write data.

The first and second internal readout instructions INT_RD0 and INT_RD1 may be generated prior to a predetermined clock (CLK) rising or falling edge than the write latency WL = 28. The second read command INT_RD1 may be generated after the generation of the first read command INT_RD0. For example, the first internal read command INT_RD0 may be generated before the write latency WL = 28 before the 2 * tCCD timing and the second internal read command INT_RD1 may be generated before the tCCD timing than the write latency WL = 28.

In response to the first internal read command INT_RD0, the first column select signal RD_CSL0 associated with the address signal CAS2 and associated with the memory cells to which the masked upper BL write data is to be written is activated, A signal DEC0 may be generated. The first column select signal RD_CSL0 may be activated after the time tRD2CSL0 required from the first internal read command INT_RD0 to the activation of the first column select signal RD_CSL0. In response to the activation of the first column select signal RD_CSL0, the data stored in the BL0-BL15 cell blocks and the parity bits stored in the ECCP cell block can be read out.

In response to the first ECC decoding signal DEC0, the ECC engine unit can perform error bit detection / correction using the read data output from the BL0-BL15 cell blocks and the parity bits output from the ECCP cell block. The ECC engine unit can use the latch to hold the upper BL readout data of the error-corrected BL0-BL15 cell blocks.

In response to the second internal read command INT_RD1, the second column select signal RD_CSL1 connected to the memory cells is activated in the lower BL write data corresponding to the address signal CAS2 and masked, and the second ECC decode signal DEC1) may be generated. The second column select signal RD_CSL1 may be activated after the time tRD2CSL1 required from the second internal read command INT_RD1 to the activation of the second column select signal RD_CSL1. In response to the activation of the second column selection signal RD_CSL1, the data stored in the BL0-BL15 cell blocks and the parity bits stored in the ECCP cell block can be read out.

In response to the second ECC decoding signal DEC1, the ECC engine unit may perform error bit detection / correction using the read data output from the BL0-BL15 cell blocks and the parity bits output from the ECCP cell block. The ECC engine unit can use the latch to hold the lower BL readout data of error-corrected BL0-BL15 cell blocks.

The first internal write command INT_WR0 is generated in accordance with the rising edge of the clock CLK after the last data of the upper BL write data is inputted through the DQ pad and the second internal write command INT_WR1 is generated through the DQ pad May be generated in accordance with the rising edge of the clock (CLK) after the last data of the lower BL write data is inputted.

The first ECC encoded signal ENC0 may be generated in response to the first internal write command INT_WR0. In response to the first internal write command INT_WR0, the first column select signal WR_CSL0 corresponding to the address signal CAS2 and connected to the memory cells to which the masked upper BL write data is to be written can be activated

In response to the first ECC encoded signal ENC0, the ECC engine unit compares the data corresponding to the second burst length BL1 with the masked upper BL write data and the first ECC decoded signal DEC0 in response to the error-corrected BL0- It is possible to generate parity bits for the read data of the BL1 cell block among the upper BL read data of the blocks.

The second ECC encoded signal ENC1 may be generated in response to the second internal write command INT_WR1. In response to the second internal write command INT_WR1, the second column select signal WR_CSL1 corresponding to the address signal CAS2 and connected to the memory cells to which the lower BL write data is to be written may be activated

In response to the second ECC encoded signal ENC1, the ECC engine section may generate parity bits for the lower BL write data.

The first column select signal WR_CSL0 may be activated after the time tLastDataIn2CSL0 required from the rising edge of the clock CLK to the activation of the first column select signal WR_CSL0 after the input of the upper BL last write data.

In response to the first column select signal WR_CSL0, the upper BL write data and the parity bits, in which data corresponding to the second burst length BL1 is masked, are selected by the first column select signal WR_CSL0, Blocks and ECCP cell blocks.

The second column select signal WR_CSL1 may be activated after the time tLastDataIn2CSL1 required from the rising edge of the clock CLK to the activation of the second column select signal WR_CSL1 after the input of the lower BL last write data.

In response to the second column select signal WR_CSL1, the lower BL write data and the parity bits may be stored in the BL0-BL15 cell blocks and the ECCP cell block selected by the second column select signal WR_CSL0.

15 is a sixth example of a timing diagram illustrating a mask write operation of a memory device in accordance with various embodiments of the present invention.

15, the masked write operation for the high frequency burst length BL = 32 of the memory device is described. The masked write operation may be initiated by receiving a masked write command (MWR) issued from the memory controller.

Write data can be input to the DQ pad after the write latency WL from the last rising edge of the clock (CLK) received with the address signal (CAS2). After the write latency WL, e.g., WL = 28, the upper BL write data (0-1-2-3-4-5-6-) corresponding to the burst length BL = 32 in accordance with the rising and falling edges of the data strobe signal DQS, 7-8-9-abcdef) and the lower BL write data (0-1-2-3-4-5-6-7-8-9-abcdef) may be input to the DQ pad.

In response to the masked write command MWR, the memory device may generate the first and second internal readout instructions INT_RD0 and INT_RD1 and the first and second internal write instructions INT_WR0 and INT_WR1.

The first internal read command INT_RD0 may be generated in response to the rising edge of the clock CLK after the first data of the upper BL write data is inputted through the DQ pad. The second internal read command INT_RD1 may be generated in response to the rising edge of the clock CLK after the first data of the lower BL write data is inputted through the DQ pad.

The first internal write command INT_WR0 is generated in accordance with the rising edge of the clock CLK after the last data of the upper BL write data is inputted through the DQ pad and is delayed by a predetermined time tdelay and the second internal write command INT_WR1 May be generated in accordance with the rising edge of the clock CLK after a predetermined time (tdelay) delay after the last data of the lower BL write data is inputted through the DQ pad.

The first column select signal WR_CSL0 may be activated after the time tDelayLastDataIn2CSL0 required from the rising edge of the clock CLK to the activation of the first column select signal WR_CSL0 after the input of the upper BL last write data.

The second column select signal WR_CSL1 may be activated after the time tDelayLastDataIn2CSL1 required from the rising edge of the clock CLK to the activation of the second column select signal WR_CSL1 after the input of the lower BL last write data.

16 is a seventh example of a timing diagram illustrating a mask write operation of a memory device in accordance with various embodiments of the present invention.

16, the masked write operation for the high frequency burst length BL = 32 of the memory device is described. The masked write operation may be initiated by receiving a masked write command (MWR) issued from the memory controller.

The first internal readout instruction INT_RD0 may be generated with the last rising edge of the clock CLK received with the address signal CAS2. The second internal readout instruction INT_RD1 may be generated in response to the rising edge of the clock CLK after a predetermined time delay when the first internal readout instruction INT_RD0 is generated. The second internal readout instruction INT_RD1 may be generated in response to the rising edge of the clock CLK after the first internal readout instruction INT_RD0 has been generated, for example, tCCD timing.

17 is an eighth example of a timing diagram illustrating a mask write operation of a memory device according to various embodiments of the present invention.

17, the masked write operation for the high frequency burst length BL = 32 of the memory device is described. The masked write operation may be initiated by receiving a masked write command (MWR) issued from the memory controller.

The first internal read command INT_RD0 may be generated before a predetermined clock (CLK) rising or falling edge than the write latency WL = 28. The second read command INT_RD1 may be generated after the generation of the first read command INT_RD0. For example, the first internal read command INT_RD0 may be generated before the tCCD timing than the write latency WL = 28, and may be generated in response to the last rising edge of the clock CLK received with the address signal CAS2. The second internal readout instruction INT_RD1 may be generated in response to the rising edge of the clock CLK after the first internal readout instruction INT_RD0 has been generated, for example, tCCD timing.

18 is a second example diagram illustrating a command control logic portion in accordance with various embodiments of the present invention.

18, the command control logic unit includes a plurality of flip-flops 1310, 1810 1820, 1830, 1840 and 1850 and NAND gates 1360, ogates 1370, a read range control unit 1880, And a range control unit 1890. Flip-flop 1310, NAND gate 1360 and gate 1370 are the same as described in FIG. That is, the output signal of the NAND gate 1360 generated for the write latency WL = n is input to the OR gate 1370, and the OR gate 1370 outputs the output signal of the NAND gate 1360 and the write latency WL = n- 1 and the flip-flop 1310 performs a gating operation on the output of the gate 1370 in response to the clock CLK to generate a control signal of the write latency WL = n have.

FIGS. 14, 15, 16, and 17, which describe the mast write operations of the present invention, describe the case where the write latency WL = 28. For write latency WL = 28, flip-flop 1830 generates a control signal of write latency WL = 28, flip-flop 1810 generates a control signal of write latency WL = (28-16) Flop 1840 generates a control signal of a write latency WL = (28-8), a flip flop 1840 generates a control signal of a write latency WL = (28 + 8), and a flip flop 1850 generates a write latency WL = (28 + 16).

The control signal of the write latency WL = (28-16) is a signal preceded by 16 clock (CLK) cycles before the control signal of the write latency WL = 28, and is a signal preceded by a timing of 2 * tCCD than the write latency WL = 28. The control signal of the write latency WL = (28-8) is a signal that precedes the control signal of the write latency WL = 28 by 8 clock (CLK) cycles, and is the signal preceded by the tCCD timing with respect to the write latency WL = 28. The control signal of the write latency WL = (28 + 8) is a signal after 8 clock (CLK) cycles of the control signal of the write latency WL = 28 and a signal after the tCCD timing of the write latency WL = 28. The control signal of the write latency WL = (28 + 16) is a signal 16 clock (CLK) cycles later than the control signal of the write latency WL = 28 and is a signal after the timing of 2 * tCCD than the write latency WL = 28.

The control signals of the write latency WL = (28-16), WL = (28-8), and WL = 28 output from the flip-flops 1810, 1820 and 1830 may be provided to the read range control unit 1380. The read range control unit 1880 controls the write latency WL = (28-16), WL = (28-8), WL = 28 of the flip-flops 1810, 1820 and 1830 and the frequency information signal INFO_FREQ (INT_RD0, INT_RD1) by performing a logical operation on the first internal read command (INT_RD0, INT_RD1). The frequency information signal INFO_FREQ may be provided based on high frequency operation or low frequency operation according to the data rate of the memory device.

The read range control unit 1880 may generate an internal read command INT_RD by being controlled by the latency information signal INFO_WL instead of the frequency information signal INFO_FREQ. The latency information signal INFO_WL is provided based on the latency, and the internal read command INT_RD may be generated in conjunction with the latency.

Control signals of the write latency WL = (28 + 8), WL = (28 + 16) output from the flip-flops 1840 and 1850 may be provided to the write range control unit 1890. The write range control unit 1890 can generate control signals of the write latency WL = (28 + 8) and WL = (28 + 16) with the first and second internal write commands INT_WR0 and INT_WR1.

19 through 21 are diagrams illustrating a memory module including a DRAM performing a mask write operation in accordance with various embodiments of the present invention.

19, the memory module 1900 includes a printed circuit board 1901, a plurality of DRAM chips 1902, and a connector 1903. A plurality of DRAM chips 1902 can be coupled to the upper surface and the lower surface of the printed circuit board 1901. The connector 1903 is electrically connected to a plurality of DRAM chips 1902 through conductive lines (not shown). Further, the connector 1903 can be connected to a slot of the external host.

The method of operating a masked write of each DRAM chip 1902 includes receiving masked write commands and addresses from a memory controller, receiving masked write commands and receiving masked write data after a write latency, Generating an internal read command in response to a write command in response to the write command, reading data stored in memory cells in which write data masked in response to an internal read command is to be stored, Generating an internal write command in accordance with the masked write data in response to the masked write command, and storing the masked write data in response to the internal write command in the memory cells.

The internal read command may be generated before a predetermined clock rising or falling edge than the write latency, before the tCCD timing than the write latency, or after the first data of the write data is input, or in response to a clock received with the address .

The internal write command may be generated after the last data of the masked write data is input, or may be generated after a predetermined time delay when the last data of the write data is input.

The method of operating a masked write of each DRAM chip 1902 includes receiving a masked write command and an address, receiving a masked write command, and receiving masked write data corresponding to a burst length after a write latency , Generating first and second internal read commands in response to a write latency in response to a masked write command, generating data corresponding to an upper burst length of the write data corresponding to the address in response to the first internal read command Reading the first data stored in the first memory cells to be stored and detecting and correcting the error with respect to the first data read out; generating a lower burst of write data corresponding to the address and masked in response to the second internal read command; The second data stored in the second memory cells to which the data corresponding to the length is to be stored Generating first and second internal write commands in response to the masked write data in response to the masked write command, generating a first internal write command in response to the first internal write command, Storing the masked write data of the upper burst length in the first memory cells and storing the masked write data of the lower burst length in the second memory cells in response to the second internal write command.

The first and second internal readout instructions may be generated prior to a predetermined clock rise or falling edge rather than a write latency. The first internal read command may be generated before the 2 * tCCD timing than the write latency and the second internal read command may be generated before the tCCD timing rather than the write latency. The first internal read command may be generated after the first data of the data corresponding to the upper burst length is input and the second internal read command may be generated after the first data of the data corresponding to the lower burst length is input. A first internal read command is generated in response to a clock received with an address, and a second internal read command is generated after a first internal read command is generated and tCCD timing. Alternatively, the first internal read command may be generated before the tCCD timing rather than the write latency, and the second internal read command may be generated after the first internal read command is generated and after the tCCD timing.

The first internal write command may be generated after the last data of the data corresponding to the upper burst length is input and the second internal write command may be generated after the last data of the data corresponding to the lower burst length is inputted. Alternatively, the first internal write command may be generated after the last data of the data corresponding to the upper burst length is input and delayed by a predetermined time, the last data of the data corresponding to the lower burst length is input, Lt; / RTI >

20, the memory module 2000 includes a printed circuit board 2001, a plurality of DRAM chips 2002, a connector 2003, and a plurality of buffer chips 2004. A plurality of buffer chips 2004 may be disposed between each DRAM chip 2002 and the connector 2003. The DRAM chips 2002 and the buffer chips 2004 may be provided on the upper and lower surfaces of the printed circuit board 2001, respectively. DRAM chips 2002 and buffer chips 2004 formed on the upper and lower surfaces of the printed circuit board 2001 may be connected through a plurality of via-holes.

A method of operating a masked write of each DRAM chip 2002 includes receiving a masked write command and address from a memory controller, receiving a masked write command and receiving masked write data after a write latency, Generating an internal read command in response to a write command in response to the write command, reading data stored in memory cells in which write data masked in response to an internal read command is to be stored, Generating an internal write command in accordance with the masked write data in response to the masked write command, and storing the masked write data in response to the internal write command in the memory cells.

A method of operating a masked write of each DRAM chip 2002 includes the steps of receiving a masked write command and an address, receiving a masked write command, and receiving masked write data corresponding to a burst length after a write latency , Generating first and second internal read commands in response to a write latency in response to a masked write command, generating data corresponding to an upper burst length of the write data corresponding to the address in response to the first internal read command Reading the first data stored in the first memory cells to be stored and detecting and correcting the error with respect to the first data read out; generating a lower burst of write data corresponding to the address and masked in response to the second internal read command; The second data stored in the second memory cells to which the data corresponding to the length is to be stored Generating first and second internal write commands in response to the masked write data in response to the masked write command, generating a first internal write command in response to the first internal write command, Storing the masked write data of the upper burst length in the first memory cells and storing the masked write data of the lower burst length in the second memory cells in response to the second internal write command.

21, the memory module 2100 includes a printed circuit board 2101, a plurality of DRAM chips 2102, a connector 2103, a plurality of buffer chips 2104, and a controller 2105. The controller 2105 communicates with the DRAM chips 2102 and the buffer chips 2104 and controls the operation mode of the DRAM chips 2102. The controller 2105 can control various functions, characteristics, and modes using the mode register of the DRAM chip 2105.

A method of operating a masked write of each DRAM chip 2102 includes receiving a masked write command and address from a memory controller, receiving a masked write command and receiving masked write data after a write latency, Generating an internal read command in response to a write command in response to the write command, reading data stored in memory cells in which write data masked in response to an internal read command is to be stored, Generating an internal write command in accordance with the masked write data in response to the masked write command, and storing the masked write data in response to the internal write command in the memory cells.

A method of operating a masked write of each DRAM chip 2102 includes the steps of receiving a masked write command and an address, receiving a masked write command, and receiving masked write data corresponding to a burst length after a write latency , Generating first and second internal read commands in response to a write latency in response to a masked write command, generating data corresponding to an upper burst length of the write data corresponding to the address in response to the first internal read command Reading the first data stored in the first memory cells to be stored and detecting and correcting the error with respect to the first data read out; generating a lower burst of write data corresponding to the address and masked in response to the second internal read command; The second data stored in the second memory cells to which the data corresponding to the length is to be stored Generating first and second internal write commands in response to the masked write data in response to the masked write command, generating a first internal write command in response to the first internal write command, Storing the masked write data of the upper burst length in the first memory cells and storing the masked write data of the lower burst length in the second memory cells in response to the second internal write command.

The DRAM modules 1900, 2000, and 2100 may be a single in-line memory module (SIMM), a dual in-line memory module (DIMM), a small-outline DIMM (SO-DIMM), a unbuffered DIMM (UDIMM) -buffered DIMMs, rank-buffered DIMMs, load-reduced DIMMs, mini-DIMMs, and micro-DIMMs.

22 is a diagram illustrating a semiconductor device having a stacked structure including DRAM semiconductor layers for performing a mask write operation according to various embodiments of the present invention.

Referring to FIG. 22, the semiconductor device 2200 may include a plurality of DRAM semiconductor layers LA1 to LAn. Each of the semiconductor layers LA1 to LAn may be a memory chip including memory cell arrays 2201 composed of DRAM cells and some of the semiconductor layers LA1 to LAn may be a master for interfacing with an external controller Chip, and the remainder may be a slave chip storing data. 22, the lowest semiconductor layer LA1 may be a master chip, and the remaining semiconductor layers LA2 to LAn may be slave chips.

The plurality of semiconductor layers LA1 to LAn transmit and receive signals through the through silicon vias TSV 1502. The master chip LA1 is connected to an external memory controller (not shown) through conductive means (not shown) &Lt; / RTI >

In addition, the transmission of signals between the semiconductor layers LA1 to LAn can be performed by an optical I / O connection. For example, a radio frequency (RF) wave or a radiative method using ultrasonic waves, an inductive coupling method using magnetic induction, or a non-radiative method using magnetic resonance, Can be connected to each other using a method.

The radial method is a method of wirelessly transmitting a signal using an antenna such as a monopole or a planar inverted-F (PIFA) antenna. When an electric field or a magnetic field which changes with time influences each other, radiation occurs, and when there is an antenna of the same frequency, a signal can be received according to the polarization characteristic of the incident wave. Inductive coupling is a method in which a coil is wound several times to generate a strong magnetic field in one direction and a coil that resonates at a similar frequency is brought close to generate coupling. The non-radiative method uses a evanescent wave coupling that moves electromagnetic waves between two mediums that resonate at the same frequency through a near field.

A method of operating a masked write of each of the semiconductor layers (LA1 to LAn) includes receiving a masked write command and an address from a memory controller, receiving a masked write command, and receiving masked write data after a write latency , Generating an internal read command in response to a write latency in response to a masked write command, reading data stored in memory cells in which write data masked in response to an internal read command is to be stored, Generating an internal write command in response to the masked write data in response to the masked write command, and storing the masked write data in memory cells in response to the internal write command.

A method of operating a masked write of each of the semiconductor layers (LA1 to LAn) includes receiving a masked write command and an address, receiving a masked write command, receiving masked write data corresponding to a burst length after a write latency Generating first and second internal read commands in response to a write latency in response to a masked write command, generating first and second internal read commands in response to a first internal read command corresponding to an upper burst length of the write data corresponding to the address and masked in response to a first internal read command Reading the first data stored in the first memory cells in which data is to be stored and detecting and correcting the error of the read first data; The data corresponding to the lower burst length is stored in the second memory cells to be stored Generating first and second internal write commands in accordance with the masked write data in response to the masked write command, reading the first data and the second internal write commands in response to the masked write command, Storing the masked write data of the upper burst length in the first memory cells in response to the write command and storing the masked write data of the lower burst length in the second memory cells in response to the second internal write command, .

In the module structures of FIGS. 19 to 21 described above, each DRAM chip may include a plurality of DRAM semiconductor layers LA1 to LAn.

23 is a diagram illustrating a memory system including a DRAM that performs a mask write operation in accordance with various embodiments of the present invention.

Referring to FIG. 23, the memory system 2300 includes optical connection devices 2301A and 2301B, a controller 2302, and a DRAM 2303. The optical connectors 2301A and 2301B interconnect the controller 2302 and the DRAM 2303. The controller 2302 includes a control unit 2304, a first transmitting unit 2305, and a first receiving unit 2306. The control unit 2304 transmits the first electric signal SN1 to the first transmission unit 2305. [ The first electrical signal SN1 may be composed of command signals, clocking signals, address signals or write data transmitted to the DRAM 2303.

The first transmission unit 2305 includes a first optical modulator 2305A and the first optical modulator 2305A converts the first electrical signal SN1 into a first optical transmission signal OTP1EC to form an optical connection unit 2301A ). The first optical transmission signal OTP1EC is transmitted through the optical connection device 2301A by serial communication. The first receiver 2306 includes a first optical demodulator 2306B and the first optical demodulator 2306B receives a second optical signal OPT2OC received from the optical connector 2301B as a second electrical signal SN2 And transmits it to the control unit 2304.

The DRAM 2303 includes a second receiving unit 2307, a memory area 2308 including a memory cell array, and a second transmitting unit 2309. A method of operating a masked write of DRAM 2303 includes receiving a masked write command and address from a memory controller, receiving a masked write command and receiving write data masked after a write latency, Generating an internal read command in response to a write latency, reading data stored in memory cells in which write data masked in response to an internal read command is to be stored, and detecting and correcting errors in the read data Generating an internal write command in accordance with the masked write data in response to the masked write command, and storing the masked write data in the memory cells in response to the internal write command.

Receiving a masked write command and receiving a masked write data corresponding to a burst length after a write latency; and performing a masked write command on the masked write command, Generating first and second internal read commands in response to a write command in response to a write command, generating first and second internal read commands in response to a write command, The method comprising the steps of: reading first data stored in one memory cell and detecting and correcting an error of the first data read out; reading the first data stored in the memory cells corresponding to the lower burst length of the masked write data in response to the second internal read command The second data stored in the second memory cells in which data to be stored is stored, Generating first and second internal write commands in response to the masked write data in response to the masked write command, generating an upper burst length in response to the first internal write command, Storing the masked write data of the lower burst length in the first memory cells and storing the masked write data of the lower burst length in the second memory cells in response to the second internal write command.

The second receiver 2307 includes a second optical demodulator 2307A and the second optical demodulator 2307A receives the first optical signal OPT1OC from the optical coupler 2301A as a first electrical signal SN1 And transfers the converted data to the memory area 2308.

In the memory area 2308, the write data is written to the memory cell in response to the first electrical signal SN1 or the data read from the memory area 2308 is transmitted as the second electrical signal SN2 to the second transmitter 2309 do. The second electrical signal SN2 may be composed of a clocking signal, read data, and the like transmitted to the memory controller 2302. [ The second transmitting unit 2309 includes a second optical modulator 2309B and the second optical modulator 2309B converts the second electrical signal SN2 into a second optical data signal OPT2EC to form an optical connection unit 2301B ). The second optical transmission signal OTP2EC is transmitted through the optical connection device 2301B by serial communication.

24 is a diagram illustrating a data processing system including a DRAM that performs a mask write operation in accordance with various embodiments of the present invention.

24, the data processing system 2400 includes a first device 2401, a second device 2402, and a plurality of optical connection devices 2403 and 2404. The first device 2401 and the second device 2402 can communicate optical signals through serial communication.

The first device 2401 includes a DRAM 2405A, a first light source 2406A, a first optical modulator 2407A capable of performing an electric-to-optical conversion operation, And an optical de-modulator 2408A capable of performing an optical to electric conversion (OPD) operation. The second device 2402 includes a DRAM 2405B, a second light source 2406B, a second optical modulator 2407B and a first optical demodulator 2408B.

The method of operating a masked write of DRAMs 2405A and 2405B includes receiving a masked write command and address from a memory controller, receiving a masked write command and receiving write data masked after a write latency, Generating an internal read command in response to a write command in response to a write command, reading data stored in memory cells to which write data masked in response to an internal read command is to be stored, Generating an internal write command in accordance with the masked write data in response to the masked write command, and storing the masked write data in the memory cells in response to the internal write command.

Receiving a masked write command and an address; receiving masked write data corresponding to a burst length after a write latency; and receiving the masked write command and address, Generating first and second internal read commands in response to a write latency in response to a masked write command, storing data corresponding to an upper burst length of the write data corresponding to the address in response to the first internal read command Reading the first data stored in the first memory cells to be erroneously detected and corrected for the first data read out; reading the lower burst length of the write data corresponding to the address and masked in response to the second internal read command The second data stored in the second memory cells to be stored in the memory Generating first and second internal write commands in accordance with the masked write data in response to the masked write command, generating first and second internal write commands in response to the first internal write command, Storing the masked write data of the upper burst length in the first memory cells and storing the masked write data of the lower burst length in the second memory cells in response to the second internal write command.

The second optical demodulator 2407A includes a second optical demodulator 2407A that receives the first optical signal OPT1OC from the optical coupler 2401A as a first electrical signal SN1 And transfers the converted data to the memory area 2408.

In the memory area 2408, the write data is written to the memory cell in response to the first electrical signal SN1 or the data read from the memory area 2408 is transmitted as the second electrical signal SN2 to the second transmitter 2409 do. The second electrical signal SN2 may be composed of a clocking signal, read data, and the like transmitted to the memory controller 2402. [ The second transmission unit 2409 includes a second optical modulator 2409B and the second optical modulator 2409B converts the second electrical signal SN2 into a second optical data signal OPT2EC to form an optical connection unit 2401B ). The second optical transmission signal OTP2EC is transmitted through the optical connection device 2401B by serial communication.

The first and second light sources 2406A and 2406B output an optical signal having a continuous waveform. The first and second light sources 2406A may be a multi-wavelength light source such as a Distributed Feed-Back Laser Diode (DFB-LD) or a Fabry-Perot Laser Diode Quot; FP-LD ") as a light source.

The first optical modulator 2407A converts the transmission data into an optical transmission signal and transmits the optical transmission signal to the optical connector 2403. The first optical modulator 2407A can modulate the wavelength of the optical signal received at the first light source 2406A according to the transmission data. The first optical demodulator 2408A receives and demodulates the optical signal output from the second optical modulator 2407B of the second device 2402 through the optical coupler 2404 and outputs the demodulated electrical signal.

The second optical modulator 2407B converts the transmission data of the second device 2402 into an optical transmission signal and transmits it to the optical connector 2404. The second optical modulator 2407B can modulate the wavelength of the optical signal received at the second light source 2406B according to the transmission data. The second optical demodulator 2408B receives and demodulates the optical signal output from the first optical modulator 2407A of the first device 2401 through the optical coupler 2403 and outputs the demodulated electrical signal.

25 is a diagram illustrating a server system including a DRAM that performs a mask write operation in accordance with various embodiments of the invention.

25, the server system 2500 includes a memory controller 2502 and a plurality of memory modules 2503. [ Each memory module 2503 may include a plurality of DRAM chips 2504.

A method of operating a masked write of a DRAM chip (2504) includes receiving a masked write command and address from a memory controller, receiving a masked write command and receiving write data masked after a write latency, Generating an internal read command in response to a command in response to a write latency, reading data stored in memory cells in which write data masked in response to an internal read command is stored, and detecting and correcting errors in the read data Generating an internal write command in accordance with the masked write data in response to the masked write command, and storing the masked write data in the memory cells in response to the internal write command.

Receiving a masked write command and receiving a masked write data corresponding to a burst length after a write latency; and applying a masked write command to the mask Generating first and second internal read commands in response to a write command in response to a write command; storing data corresponding to an upper burst length of write data corresponding to the address in response to the first internal read command in response to a write latency; Reading the first data stored in the first memory cells and detecting and correcting the error of the first data read out; reading the first data stored in the second memory cells in the lower burst length of the masked write data in response to the second internal read command Reads out the second data stored in the second memory cells to which the corresponding data is to be stored, Generating first and second internal write commands in accordance with the masked write data in response to the masked write command, generating an upper burst in response to the first internal write command, Length masked write data in the first memory cells and storing the masked write data of the lower burst length in the second memory cells in response to the second internal write command.

The server system 2500 may have a structure in which the second circuit board 2506 is coupled to the sockets 2505 of the first circuit board 2501. The server system 2500 can design a channel structure in which one second circuit board 2506 is connected to the first circuit board 2501 for each signal channel. However, the present invention is not limited thereto and may have various structures.

Meanwhile, the transmission of the signals of the memory modules 2503 can be performed by an optical I / O connection. For optical input / output connection, the server system 2500 may further include a pre-light conversion unit 2507, and each of the memory modules 2503 may further include a light-to-electricity conversion unit 2508.

The memory controller 2502 is connected to the electro-optic conversion unit 2507 via an electrical channel EC. The electro-optical conversion unit 2507 converts an electrical signal received from the memory controller 2502 through an electrical channel EC into an optical signal and transmits it to the optical channel OC side. Further, the electro-optical conversion unit 2507 performs signal processing for converting an optical signal received through the optical channel OC into an electrical signal and transmitting it to the electrical channel EC side.

The memory modules 2503 are connected to the electro-optic conversion unit 2507 through the optical channel OC. The optical signal applied to the memory module 2503 can be converted into an electrical signal through the opto-electronic conversion unit 2508 and transferred to the DRAM chips 2504. [ The server system 2500 including such optical connection memory modules can support high storage capacity and high processing speed.

26 is a diagram illustrating a computer system equipped with a DRAM that performs a mask write operation in accordance with various embodiments of the present invention.

26, the computer system 2600 may be mounted on a mobile device, a desktop computer, or the like. The computer system 2600 includes a modem 2608 such as a DRAM memory system 2601, a central processing unit 2605, a user interface 2607 and a baseband chipset, which are electrically connected to the system bus 2604 . The computer system 2600 may further be provided with an application chipset, a camera image processor (CIS), an input / output device, and the like.

The user interface 2607 may be an interface for transmitting data to or receiving data from the communication network. The user interface 2607 may be an interface for transmitting data to or receiving data from the communication network. The user interface 2607 may be in wired or wireless form and may include an antenna or a wired or wireless transceiver. Data provided via user interface 2607 or modem 2608 or processed by central processing unit 2605 may be stored in DRAM memory system 2601. [

The DRAM memory system 2601 may include a DRAM 2602 and a memory controller 2603. The DRAM 2602 stores data processed by the central processing unit 2605 or externally input data. A method of operating a masked write of a DRAM 2602 includes receiving a masked write command and address from a memory controller, receiving a masked write command and receiving write data masked after a write latency, Generating an internal read command in response to a write latency, reading data stored in memory cells in which write data masked in response to an internal read command is to be stored, and detecting and correcting errors in the read data Generating an internal write command in accordance with the masked write data in response to the masked write command, and storing the masked write data in the memory cells in response to the internal write command.

Receiving a masked write command and an address; receiving masked write data corresponding to a burst length after a write latency; and receiving the masked write command and address, Generating first and second internal read commands in response to a write command in response to a write command, generating first and second internal read commands in response to a write command, The method comprising the steps of: reading first data stored in one memory cell and detecting and correcting an error of the first data read out; reading the first data stored in the memory cells corresponding to the lower burst length of the masked write data in response to the second internal read command The second data stored in the second memory cells in which data to be stored is stored, Generating first and second internal write commands in response to the masked write data in response to the masked write command, generating an upper burst length in response to the first internal write command, Storing the masked write data of the lower burst length in the first memory cells and storing the masked write data of the lower burst length in the second memory cells in response to the second internal write command.

When the computer system 2600 is a device that performs wireless communications, the computer system 2600 may communicate with other devices, such as Code Division Multiple Access (CDMA), Global System for Mobile communications (GSM), North American Multiple Access (NADC) System. The computer system 2600 may be any device capable of communicating information such as a personal digital assistant (PDA), a portable computer, a web tablet, a digital camera, a Portable Media Player (PMP), a mobile phone, And can be mounted on a processing apparatus.

In the system, a cache memory having a high processing speed, a RAM and the like are separately provided and a memory for storing a large amount of data is separately provided. However, the above-mentioned memories can be replaced by one DRAM system according to an embodiment of the present invention. That is, a large amount of data can be quickly stored in a memory device including a DRAM, so that a computer system structure can be simplified.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims

(A) receiving a masked write command and an address;
(B) receiving the masked write command and receiving masked write data after a write latency;
(C) in response to the masked write command, generating an internal read command in accordance with the write latency;
(D) in response to the internal read command, reading data stored in the memory cells corresponding to the address and storing the masked write data, and detecting and correcting errors in the read data;
(E) in response to the masked write command, generating an internal write command after the last data of the masked write data is input; And
And (f) in response to the internal write command, storing the masked write data in the memory cells.

The method of claim 1, wherein in step (c)
Wherein the internal read command is generated prior to the predetermined clock rising or falling edge than the write latency.

The method of claim 1, wherein in step (c)
Wherein the internal read command is generated prior to the tCCD (CAS to CAS command delay) timing.

2. The method of claim 1, wherein step (d)
Activating a column select signal and an ECC decode signal coupled to the memory cells in response to the internal read command;
Reading data and first parity bits stored in the memory cells in response to the column select signal; And
And error detection and correction of the read data using the read data and the first parity bits in response to the ECC decoding signal.

2. The method of claim 1, wherein step (f)
Activating a column select signal and an ECC encoded signal coupled to the memory cells in response to the internal write command;
Generating second parity bits for the masked write data and the read data corresponding to the masked portion of the masked write data among the error corrected read data in response to the ECC encoded signal; And
And in response to the column select signal, storing the masked write data and the second parity bits in the memory cells selected by the column select signal.

The method according to claim 1,
Wherein the masked write data is generated by a data mask signal input with write data input via a data input / output pad (DQ).

(A) receiving a masked write command and an address;
(B) receiving the masked write command and receiving masked write data after a write latency;
(C) in response to the masked write command, generating an internal read command after the first data of the write data is input;
(D) in response to the internal read command, reading data stored in the memory cells corresponding to the address and storing the masked write data, and detecting and correcting errors in the read data;
(E) in response to the masked write command, the last data of the write data is input and an internal write command is generated after a predetermined time delay; And
And (f) in response to the internal write command, storing the masked write data in the memory cells.

8. The method of claim 7, wherein step (d)
Activating a column select signal and an ECC decode signal coupled to the memory cells in response to the internal read command;
Reading data and first parity bits stored in the memory cells in response to the read column select signal; And
And error detection and correction of the read data using the read data and the first parity bits in response to the ECC decoding signal.

8. The method of claim 7, wherein step (f)
Activating a column select signal and an ECC encoded signal coupled to the memory cells in response to the internal write command;
Generating second parity bits for the masked write data and the read data corresponding to the masked portion of the masked write data among the error corrected read data in response to the ECC encoded signal; And
And in response to the column select signal, storing the masked write data and the second parity bits in the memory cells selected by the column select signal.

(A) receiving a masked write command and an address;
(B) receiving the masked write command and receiving masked write data after a write latency;
(C) in response to the masked write command, generating an internal read command in accordance with a clock received with the address;
(D) in response to the internal read command, reading data stored in the memory cells corresponding to the address and storing the masked write data, and detecting and correcting errors in the read data;
(E) in response to the masked write command, generating an internal write command after the last data of the write data is input; And
And (f) in response to the internal write command, storing the masked write data in the memory cells.

11. The method of claim 10, wherein step (d)
Activating a column select signal and an ECC decode signal coupled to the memory cells in response to the internal read command;
Reading data and first parity bits stored in the memory cells in response to the column select signal; And
And error detection and correction of the read data using the read data and the first parity bits in response to the ECC decoding signal.

11. The method of claim 10, wherein step (f)
Activating a column select signal and an ECC encoded signal coupled to the memory cells in response to the internal write command;
Generating second parity bits for the masked write data and the read data corresponding to the masked portion of the masked write data among the error corrected read data in response to the ECC encoded signal; And
And in response to the column select signal, storing the masked write data and the second parity bits in the memory cells selected by the write column select signal.

(A) receiving a masked write command and an address;
(B) receiving the masked write command and receiving masked write data corresponding to a burst length after a write latency;
(C) in response to the masked write command, generating first and second internal read commands in accordance with the write latency;
Reads out first data stored in first memory cells to which data corresponding to an upper burst length of the masked write data corresponding to the address is to be stored in response to the first internal read command, (D1) detecting and correcting errors in the data;
Read out second data stored in second memory cells to which data corresponding to a lower burst length of the masked write data corresponding to the address is to be stored in response to the second internal read command, (D2) detecting and correcting errors in the data;
(E) in response to the masked write command, generating first and second internal write commands in accordance with the masked write data;
Storing the masked write data of the upper burst length in the first memory cells in response to the first internal write command (f1); And
And (f1) storing the masked write data of the lower burst length in the second memory cells in response to the second internal write command.

14. The method of claim 13, wherein step (c)
Wherein the first and second internal read instructions are generated prior to a predetermined clock rise or falling edge than the write latency.

14. The method of claim 13, wherein in step (c)
Wherein the first internal read command is generated prior to the write latency by 2 * tCCD timing and the second internal read command is generated prior to the tCCD timing than the write latency.

14. The method of claim 13, wherein in step (c)
The first internal read command is generated after the first data of the data corresponding to the upper burst length is input and the second internal read command is generated after the first data of the data corresponding to the lower burst length is input Wherein the memory device is a memory device.

14. The method of claim 13, wherein in step (c)
Wherein the first internal read command is generated in response to a clock received with the address and the second internal read command is generated after the first internal read command is generated and after the tCCD timing.

14. The method of claim 13, wherein in step (c)
Wherein the first internal read command is generated before the tCCD timing than the write latency and the second internal read command is generated after the first internal read command is generated and after the tCCD timing.

14. The method of claim 13, wherein in step (e)
The first internal write command is generated after the last data of the data corresponding to the upper burst length is input and the second internal write command is generated after the last data of the data corresponding to the lower burst length is input Wherein the memory device is a memory device.

14. The method of claim 13, wherein in step (e)
Wherein the first internal write command is generated after the last data of the data corresponding to the upper burst length is input and is delayed by a predetermined time and the second internal write command is inputted with the last data of the data corresponding to the lower burst length, And after a predetermined time delay.