KR20140113370A - Pass through storage devices - Google Patents

Abstract

The present invention relates to an apparatus and a method to realize a transformation pass through a storage architecture. According to the embodiments, a device includes a control circuit configured to allocate data between first and second memory tiers. The first memory tier may include a solid state memory, and the second memory tier may include a non-volatile memory. According to embodiments, a pass through storage device can be realized. According to the embodiments, at least one interface can be included to allow communication between the control circuit; and at least one of a memory, a device, and a system allows communication between any of the combination thereof.

Description

[0001] PASS THROUGH STORAGE DEVICES [0002]

Cross reference to related applications

This application is a continuation-in-part of U.S. Provisional Application No. < RTI ID = 0.0 > filed March 15,2013 < / RTI > entitled " Extended Capacity SSD Using Passthru Tiered Storage Design & Claims priority to patent application No. 61 / 790,978, the contents of which are incorporated by reference in their entirety.

The present invention relates to data storage devices having a hybrid storage architecture having at least two separate types of data storage media.

The embodiments disclosed herein generally provide devices and methods for a pass through storage device. Some embodiments of the apparatus may comprise control circuitry configured to allocate data between at least a first memory tier and a second memory tier. The first memory tier may comprise a non-volatile solid state memory and the second memory tier may comprise another non-volatile memory. The device may further include a host interface and a data storage device interface. The host interface may be configured to communicate between the control circuit and the host device. The data storage device interface may be configured to communicate between the control circuit and a data storage device comprising the second memory tier. The data storage device interface may be able to fake or replicate the host interface so that the data storage device interfaces with the device as if the data storage device directly interfaces with the host device. The control circuit is further configured to manage data transfer to the host device, the first memory tier, and the second memory tier.

Some embodiments provide an apparatus comprising a control circuit, an initiator interface and a target interface. The control circuit may be configured to allocate data between at least a first memory tier and a second memory tier and the first memory tier includes a non-volatile solid state memory and the second memory tier includes another non-volatile memory . The initiator interface may be configured to communicate between the control circuit and the initiator device. The target interface may be configured to communicate between the control circuit and the target device. Wherein at least one of the initiator interface and the target interface is capable of dodging a host controller such that the data storage device comprising the nonvolatile memory of the second memory tier interfaces with the device as if it were a host device.

Certain embodiments provide an apparatus comprising control circuitry configured to receive from a host system a request to write selected data. The control circuit may be further configured to cache the selected data in a first non-volatile solid state memory. In addition, the control circuit may store at least the selected data subset in the second non-volatile memory based on the trigger event. The device may further include a host interface and a data storage interface. The host interface may be configured to communicate between the control circuit and the host system. The data storage interface may be configured to communicate between the control circuit and the second nonvolatile memory. The data storage interface may mimic the host interface such that the data storage device interfaces with the device as if the data storage device directly interfaces with the host system.

1 is a diagram of certain embodiments of a pass through storage device;
2 is a functional block diagram of certain embodiments of a pass through storage device;
3 is a functional block diagram of certain embodiments of a pass through storage device;
4 is a flow diagram of a method of certain embodiments for pass through storage devices; And
5 is a flow diagram of a method of certain embodiments for pass through storage devices.

In the following detailed description of the embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments. It is to be understood that the features of the various described embodiments may be combined, that other embodiments may be utilized, and structural changes may be provided without departing from the scope of the present invention.

FIG. 1 shows a diagram of a system 100 including an extended solid state device (XSSD) module 104 in accordance with some embodiments of the invention. The system 100 further includes a data storage device (DSD) 106 having a data storage medium (DSM) 106 (hereinafter referred to as DSM 106) that can be coupled to the XSSD module 104 and a host 102 .

Host 102 may also be referred to as a host system or host computer. Host 102 may be a desktop computer, a laptop computer, a server, a personal digital assistant (PDA), a telephone, a music player, other electronic devices, or any combination thereof. The DSM 106 may be any of the devices listed above for the host 102 or any other device that may be used to store or retrieve data, such as a hard disk drive (HDD).

In some embodiments, the XSSD module 104 may be integrated on a bridge adapter configured to interface with and connect to the host 102 and the DSM 106. Alternatively or additionally, the XSSD module 104 may be integrated on the host 102 or the DSM 106.

The XSSD module 104 may be coupled to the XSSD module 104 via one or more interfaces 108,101 that may include connectors that allow the XSSD module 104 to be physically removed from the host 102, the DSM 106, May communicate with the host 102 and the DSM 106. The interface (s) 108 may comprise hardware circuits, logic, firmware, or any combination thereof. In some embodiments, the interface (s) 108 may include one or more of the following standards: universal serial bus (USB), IEEE 1394, serial advanced technology attachment (SATA), external SATA (eSATA), parallel advanced technology attachment (PATA) , A small computer system interface (SCSI), a serial attached SCSI (SAS), a peripheral component interconnect express (PCIe), and a fiber channel (FC). However, any other suitable interface that allows the XSSD module 104 to communicate with the host 102, DSM 106, or both can be used. The XSSD module 104, the DSM 106, or both may be located inside or outside the enclosure of the host 102.

Referring to Figure 2, a functional block diagram of an exemplary embodiment of a system 200 including an extended solid state module device (XSSD) module 104 is shown. The XSSD module 104 may include a number of ports, for example, that allow connection of various devices, such as one or more types of non-volatile data storage media.

The XSSD module 104 may include an initiator interface 202 and a target interface 204. The initiator interface 202 may be configured to allow the XSSD module 104 to interface with the initiator 206 and the target interface 204 may be configured to allow the XSSD module 104 to communicate with the target 208 . In some embodiments, the initiator 206 may be a host device, such as the types of devices described above with reference to the host 102 of FIG. The target 208 may be a data storage device, such as the types described above with reference to the DSM 106 of FIG. In other embodiments, the data storage device may be considered as an initiator 206 and the host device may be considered as a target 208.

The XSSD module 104 may include a control circuit 210 having one or more associated processors 212. The control circuitry 210 may be configured to execute and control a hybrid file system that determines and tracks the allocation of data requested by or received from the initiator 206, the target 208, or both.

In some embodiments, the XSSD module 104 may include a solid state memory (SSM) 214 that is used as a cache for data that at least partially meets one or more cache criteria. The SSM 214 may be a volatile solid state memory (VSSM), such as a static random-access memory (SRAM) or a dynamic random-access memory Memory. It should be understood that any other type (s) or combination (s) SSM 214 or NVSSM may be used, although the following description refers primarily to NVSSM or flash memory 214. [

The XSSD module 104 may include a buffer manager 216 that may allocate data from / to one or more memory units used as the buffer memory 218. For example, the XSSD module 104 may transfer data that is transmitted during read and write operations to / from the target 208, to / from the NVSSM, or any combination thereof, from / to the initiator 206 And may have one or more SRAM or DRAM units 218 used for temporary storage. Buffer memory 218 may include an instruction queue (not shown) that may be temporarily stored while access operations are waiting for execution. Although SRAM / DRAM unit (s) 218 are shown in Figure 2 as being present in XSSD module 104, they may additionally or alternatively be provided outside XSSD module 104, e.g., In DRAM unit 312 shown in FIG.

The XSSD module 104 further includes a flash protocol processor 222 and a first-in-first-out (FIFO) memory unit 220 for coupling the flash memory 214 to the buffer manager 216 with respect to communication Which, in turn, is coupled to the control circuit 210 in terms of communication. The FIFO memory unit 220 may receive data from the buffer manager 216 and may store data until it is transmitted to the flash protocol processor 222 based on the FIFO basis. The FIFO memory unit 220 may include an error correction code (ECC) that implements checks on the data received in the FIFO memory unit 220 and may correct any error bits so that data integrity is maintained.

Flash protocol processor 222 may be a specialized processor dedicated to extracting / processing / constructing data received from FIFO memory unit 220 in accordance with one or more communication protocols, Send data in the proper format for my storage.

Alternatively or additionally, the XSSD module 104 may be configured to allow the addition of one or more external flashes (or any other type of NVSSM) memory units 214. Figure 2 illustrates the performance of the flash memory 214 coupled with communication to the flash protocol processor 222 via one or more flash input / output (I / O) ports 224. It should be understood that a plurality of external flash memory units 214 may be attached to the XSSD module 104, although a single external flash memory 214 is shown.

The XSSD module 104 may further include a general purpose input / output (GPIO) control 226 that can control the behavior of GPIO pins (not shown) on the XSSD module 104. In addition, the XSSD module 104 may additionally include one or more additional ports for connecting the device to be used in combination with the XSSD module 104. [ For example, the XSSD module 104 may include one or more serial ports 228 that conform to the RS-232 standard to interface with a modem or similar communication device. As another example, the XXSD module 104 may include one or more diagnostic ports 230 for interfacing with a testing device that may be used to diagnose issues with the XSSD module 104, for example.

FIG. 3 is a functional block diagram of another exemplary embodiment of a system 300 that includes an extended solid state device (XSSD) module 104. The XSSD module 104 may include a controller 302, which in some embodiments is an example of the control circuit 210 described above with reference to FIG.

Controller 302 may communicate with host system 102 via an interface that includes host controller 304. Controller 302 may also communicate with data storage device (DSD) 106 via interface 110, which includes host interface-dummy controller 306. The host interface-dummy controller 306, which is referred to as dummy because it can be configured to replicate the host controller 304, and the DSD 106 is connected to the XSSD module 104 as if the DSD were directly interfaced with the host system 102. [ I.e., the DSD 106 can not distinguish between the interfaces with the XSSD module 104 and the host system 102.

The controller 302 may further communicate with one or more non-volatile solid state memory (NVSSM) units 308 via one or more NVSSM controllers 310. [ In some embodiments, NVSSM units 308 are NAND flash memory units and NVSSM controllers 310 are NAND controllers. Furthermore, XSSD module 104 may use NVSSM units 308 as non-volatile cache and may use DSD 106 as persistent storage. Thus, it should be understood that the XSSD module 104 may be configured to communicate and be coupled to any type of memory suitable for use as a persistent storage, and any type of memory suitable for use as a non-volatile cache.

The controller 302 may further communicate with the buffer memory unit 312 via an interface including a buffer memory controller 314. In some embodiments, the buffer memory controller 314 may be a component of the buffer manager 316 used to allocate data to / from the buffer memory 312. The buffer memory unit 312 may be used to temporarily store data to be transmitted during read and write operations to / from the target 208, from / to the NVSSM, or any combination thereof. . Buffer memory 312 may include an instruction queue (not shown) that may be temporarily stored while access operations are waiting to be executed. Although the buffer memory unit 312 is shown in FIG. 3 as an external single DRAM unit for the XSSD module 104, the controller 302 includes a plurality of buffer memory units 312 (see FIG. 2) It should be understood that the buffer memory units 312 may communicate with one or more DRAM units (as described, including one or more DRAM units) and that the buffer memory units 312 may additionally or alternatively reside within the XSSD module 104.

In some embodiments, the controller 302 and each host system (s) 102, DSD (s) 106, NVSSM unit (s) 308 and buffer memory unit (s) The interface (s) may include one or more of the following standards: universal serial bus (USB), IEEE 1394, serial advanced technology attachment (SATA), external SATA, parallel advanced technology attachment (PATA) (SAS), peripheral component interconnect express (PCIe), and fiber channel (FC). However, it is contemplated that controller 302 may be configured to communicate with host system (s) 102, DSD (s) 106, NVSSM unit (s) 308, buffer memory unit (s) 312, Any other suitable interface may be used to allow.

The controller 302 may include an instruction CPU 318, a translation layer CPU 320, an instruction memory 322 and a data memory 324. The instruction data sent to the controller 302 may be temporarily stored in the instruction memory 322 and the user data transmitted to the controller 302 at the same time may be temporarily stored in the data memory 324. [ Accordingly, the instruction memory 322 and the data memory 324 are used to temporarily store data transmitted during read and write operations until they are actually executed by the instruction CPU 318 or the translation layer CPU 320 or both Or buffer memory units (i.e., buffer memory units disposed between buffer memory unit 312 and CPUs 318, 320).

In accordance with some embodiments, the instruction CPU 318 may be configured to receive read and write requests and may include host system (s) 102, DSD (s) 106, NVSSM unit (s) 308, And allocates user data associated with requests between the buffer memory unit (s) Translation layer CPU 320 may be configured to process a software layer that manages read and write access to NVSSM unit (s) 308. [ The translation layer CPU 320 or the protocol processor may be a flash translation layer (FTL) CPU that translates the data allocated to the NAND flash memory so that the allocated data is readable by the NAND flash memory.

All or a portion of the components shown in Figures 2-3 may be built into a single processor or controller chip and perform the functions and operations discussed herein with respect to the XSSD module 104 and systems 200, Lt; RTI ID = 0.0 > and / or < / RTI >

FIG. 4 shows a flowchart of an exemplary embodiment of a method 400 for implementing a tiered storage architecture. When describing the embodiments of the method 400 illustrated by FIG. 4, the drawing numbers will also be provided in FIGS. 1-3 to clarify certain aspects of the method 400.

At block 402, the XSSD module 104 receives a read request. For example, the host system 102 may send a read request to the XSSD module 104. However, the read request may originate from any device or system to which the XSSD module 104 is coupled with respect to communication.

If the XSSD module 104 determines that the read request is a cache hit (i.e., if the requested data is stored in the cache at the time of the request), then the XSSD module 104 ) Determines at block 405 whether the requested data is cached in the DRAM (or SRAM). If the requested data is cached in the DRAM, then the XSSD module 104 retrieves the data from the DRAM and provides data to the read requester (i. E., The device or system that initiated the read request) at block 410. If the requested data is not cached in the DRAM then the XSSD module 104 retrieves the data from the nonvolatile solid state memory (NVSSM) of the first memory tier at block 406 and sends the data to the read requester at block 410 Lt; / RTI >

If, however, at block 404 the XSSD module 104 determines that the read request is not a cache hit, then the XSSD module 104 retrieves the data from the data storage device / media of the second memory tier at block 408 And provides data to the read requestor at block < RTI ID = 0.0 > 410. < / RTI >

As used in this application, the term " first memory tier " is used to distinguish a memory tier that includes a " second memory tier " that includes non-volatile memory used as persistent storage and an NVSSM that is used as a cache. However, the terms " first memory tier " and " second memory tier " are not intended to limit embodiments of the present invention to two memory tiers, Nor is it intended to exclude one or more memory tiers after. Flash memory 214, 308 in Figures 2-3 illustrates NVSSM included in the first memory tier of some embodiments. The data storage device / medium (DSD / DSM) 106 of FIG. 3 illustrates a non-volatile memory included in a second memory tier of some embodiments.

In some embodiments, the XSSD module 104 determines whether it meets either or both of the cache criteria and the persistent storage criteria, respectively. The XSSD module 104 determines that the data meets its cache criteria and then is written to the NVSSM of the first memory tier if the data has not yet been stored therein. If the XSSD module 104 determines that the data meets its persistent storage criteria, then it is written to the DSD / DSM of the second memory tier if the data has not yet been stored therein. In some embodiments, cache criteria, persistent storage criteria, or both may be predetermined based on one or more parameters. However, in some embodiments, cache criteria, parameters for persistent storage criteria, or both may be updated or determined on-the-fly by the XSSD module 104. The parameters that may be based on cache criteria, persistent storage criteria, or both may be aging (timing), capacity (% pool), power events (e.g., shutdown), sensed idle time or parameters, Combinations thereof, but are not limited thereto.

FIG. 5 shows a flowchart of another exemplary embodiment of a method 500 for implementing a tiered storage architecture. When describing embodiments of the method 500 illustrated by FIG. 5, the drawing numbers will also be provided in FIGS. 1-3 to clarify certain aspects of the method 500.

At block 502, the XSSD module 104 may receive a write request. For example, the host system 102 may send a write request to the XSSD module 104. However, the write request may originate from any device or system to which the XSSD module 104 is coupled with respect to communication. In some embodiments, the write request may include user data and command data buffered in volatile memory.

In some embodiments of the method 500, the XSSD module 104 determines at block 504 data selected in the non-volatile solid state memory (NVSSM) of the first memory tier (i.e., Data) can be recorded. Thus, all selected data may be cached in the NVSSM of the first memory tier before the first memory tier has pushed any selected data elsewhere.

In some embodiments, all data passing through the XSSD module 104 may be stored in the NVSSM. For example, all writes may be directed to the NVSSM after a threshold time in the cache buffer, which may be a volatile random access memory. When the cache is flushed to the NVSSM after a critical time (or based on another trigger), a minimum amount of write data, such as a page in the flash memory, may be required. Furthermore, readings received by the XSSD module 104 may be stored in the NVSSM. In some instances, when data from a read command is stored in the XSSD module 104, a minimum number of items may be stored in the NVSSM. First, the actual data requested by the host can be stored, and second, additional Read Look Ahead data can be stored in the NVSSM. For example, if the host 102 will seek data from a logical block address (LBA) 100 and it is not yet in the NVSSM, then the XSSD module 104 will retrieve the data from the DSD 106, And return data to the host 102. The XSSD module 104 may also store data in the NVSSM for future reads from the LBA 100 and further read from the LBA 101 if the subsequent request from the host 102 is for the LBA 101. [ It will also store Read Look Ahead data. The XSSD module 104 or the DSD 106 may initiate a read for Read Look Ahead data which may then be stored in the NVSSM of the XSSD module 104. [

At block 506, the XSSD module 104 may determine whether a persistent storage trigger event has occurred for some or all of the selected data, whether one or more persistent storage criteria are satisfied, or a combination thereof. If so, then the XSSD module 104 moves at block 508 a minimal subset of the selected data to the non-volatile memory of the second memory tier. The persistent storage trigger event, persistent storage criteria, or a combination thereof may include one or more parameters such as: aging (timing), capacity (% pool), power events (e.g., shutdown), sensed idle time, , ≪ / RTI > or any combination thereof.

Although FIG. 5 shows a method 500 of caching all selected data to the NVSSM of the first memory tier before the first memory tier has pushed any selected data elsewhere, Or caching only those data that meet the cache criteria, as described above with reference to FIG. 4, for example.

In some embodiments, a hybrid data storage system, with these implementations of the apparatus and methods described above with respect to Figures 1-5, may be implemented in a host system or a data storage device (e.g., a hard disk drive (HDD) Can be implemented with little or no modifications. Furthermore, the XSSD module 104 may selectively allocate storage space among a plurality of devices to be used as a storage space with its own address or as a non-volatile cache. In some instances, the HDD may be used as permanent storage, while the non-volatile solid state memory (NVSSM) may be used for data that is fixed in the cache for faster read access times from the HDD, or as nonvolatile cache for incoming and outgoing data . In some embodiments, the total storage capacity reported to the host system may be the capacity of the NVSSM in addition to the capacity of the HDD. Moreover, in some embodiments, multiple storage devices / media may, for example, be a backup for the NVSSM, or may act as a backup for either or both.

The XSSD module 104 may be at least partially integrated on the host system so that data may be transmitted between the host system, the first memory tier, and the second memory tier. Additionally or alternatively, the XSSD module 104 may be at least partially integrated on a data storage device including a non-volatile memory of a second memory tier so that data is transferred between the host system, the first memory tier, Lt; / RTI > Additionally or alternatively, the XSSD module 104 may be integrated, at least partially, on a bridge adapter configured to allow coupling of the XSSD module 104 to a data storage device and host system comprising a non-volatile memory of a second memory tier So that data can be transmitted between the host system, the first memory tier and the second memory tier.

According to various embodiments, the methods described in this application may be implemented as a computer processor or a controller, e.g., one or more software programs operating on a controller 206. [ According to another embodiment, the methods described in this application may be implemented with one or more software programs running on a computing device, e.g., a personal computer, using a disk drive. Dedicated hardware implementations including, but not limited to, application specific integrated circuits, programmable logic arrays, and other hardware devices may likewise be configured to implement the methods described in this application. Moreover, the methods described in this application may be embodied in a computer-readable medium including instructions that are executable by a processor to perform the methods.

The examples of embodiments described in this application are intended to provide a general understanding of the structure of the various embodiments. The examples are not intended to serve as a complete description of all the elements and features of the devices and systems utilizing the structures or methods described in this application. Many other embodiments will be apparent to those of ordinary skill in the art upon review of the present invention. Other embodiments may be utilized and derived from the present invention, so that structural and logical alternatives and variations may be provided without departing from the scope of the present invention. In addition, it should be understood that although certain embodiments have been described and illustrated in this application, any subsequent arrangement designed to achieve the same or similar purposes may be substituted for the specific embodiments shown.

The present invention is intended to cover any and all subsequent modifications or variations of the various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those skilled in the art upon examination of the detailed description. In addition, the examples are merely representative and may not be drawn to scale. In the examples, some parts can be exaggerated, while others can be reduced. Accordingly, the invention and the drawings are to be regarded as illustrative and not restrictive.

Claims (20)

In the apparatus,
A control circuit configured to allocate data between at least a first memory tier and a second memory tier, wherein the first memory tier comprises a non-volatile solid state memory and the second memory tier comprises another non- A control circuit;
A host interface configured to communicate between the control circuit and the host device;
A data storage device interface configured to communicate between the data storage device comprising the second memory tier and the control circuit, the data storage device interface mimicking the host interface such that the data storage device is in communication with the data storage device The data storage device interface that interfaces with the device as if it were directly interfacing with a host device; And
Wherein the control circuit is further configured to manage data transfer to the host device, the first memory tier and the second memory tier. The method according to claim 1,
Wherein the control circuit is integrated on the host device such that data is transmitted between the host device, the first memory tier, and the second memory tier. The method according to claim 1,
Wherein the control circuit is integrated with the data storage device comprising the non-volatile memory of the second memory tier, wherein data is transmitted between the host device, the first memory tier and the second memory tier. Device. The method according to claim 1,
Wherein the device is a separately detachable hardware device capable of being disconnected from the host interface and the data storage device interface and the device comprises the nonvolatile solid state memory configured as a buffer. The method of claim 4,
Further comprising a non-volatile solid state memory protocol processor configured to implement a protocol translation layer that translates the assigned data when data is assigned to the non-volatile solid state memory, In a format readable by the device. The method of claim 5,
A buffer manager configured to communicate with the control circuit and allocate data between one or more volatile memory units configured as buffers; And
Further comprising: a first-in-first-out (FIFO) memory unit configured to store data received from the buffer manager and to transmit the received data to the non-volatile solid state memory protocol processor. The method of claim 5,
Wherein the non-volatile solid state memory is a flash memory and the non-volatile memory is a magnetic data storage medium, wherein the apparatus further comprises a buffer manager configured to allocate data between one or more volatile memory units configured as buffers and to communicate with the control circuit Comprising: The method of claim 5,
The first memory tier; And
And an output from the non-volatile solid state memory protocol processor, the output configured to couple the non-volatile solid state memory protocol processor to the non-volatile solid state memory. The method of claim 5,
Further comprising a non-volatile solid state memory interface configured to communicate between the non-volatile solid state memory protocol processor and the non-volatile solid state memory, wherein the first memory tier comprises one or more individually detachable Lt; RTI ID = 0.0 > hardware devices. ≪ / RTI > The method according to claim 1,
The control circuit
Cache data in the non-volatile solid state memory of the first memory tier for data that meets one or more cache criteria; And
And store data in the non-volatile memory of the second tier at least partially as storage space for data that meets one or more storage criteria for the second memory tier. The method of claim 10,
Wherein the one or more cache criteria and the one or more storage criteria are determined based on one or more parameters selected from the group consisting of timing, capacity, power event, and idle time. In the apparatus,
A control circuit configured to allocate data between at least a first memory tier and a second memory tier, wherein the first memory tier includes a non-volatile solid state memory, and the second memory tier includes another non-volatile memory. A control circuit;
An initiator interface configured to communicate between the control circuit and the initiator device;
A target interface configured to communicate between the control circuit and the target device;
At least one of the initiator interface and the target interface replicating a host interface such that the data storage device comprising the non-volatile memory of the second memory tier interfaces with the device as if it were a host device; And
Wherein the control circuit is further configured to manage data transfer to the host device, the first memory tier and the second memory tier. The method of claim 12,
Wherein the initiator interface and the target interface each comply with an interface standard. The method of claim 12,
And to cache all data in the non-volatile solid state memory of the first memory tier prior to storing the data in the non-volatile memory of the second memory tier. 15. The method of claim 14,
Further comprising a buffer manager configured to allocate data and communicate with the control circuitry between one or more volatile memory units configured as buffers. 16. The method of claim 15,
Further comprising a non-volatile solid state memory protocol processor configured to implement a protocol translation layer that translates the assigned data when data is assigned to the non-volatile solid state memory, In a format readable by the device. 18. The method of claim 16,
A non-volatile solid state memory interface configured to communicate between the non-volatile solid state memory protocol processor and the non-volatile solid state memory; And
Further comprising: a volatile memory interface configured to communicate between the buffer manager and one or more volatile memory units configured as buffers. In the apparatus,
Receive a request from the host system to record the selected data;
Cache the selected data to a first non-volatile solid state memory; And
A control circuit configured to store at least the selected data subset in a second non-volatile memory based on a trigger event;
A host interface configured to communicate between the control circuit and the host device;
A data storage device interface configured to communicate between the second non-volatile memory and the control circuit, the data storage device interface mimicking the host interface such that the data storage device is directly interfaceable with the host system Wherein the data storage device interface interfaces with the device as if it were a data storage device. 19. The method of claim 18,
Wherein the selected data is interpreted by a protocol processor before it is cached in the first non-volatile solid state memory so that the selected data is readable by the first non-volatile solid state memory. The method of claim 19,
And a non-volatile solid state memory interface configured to communicate between the protocol processor and the first non-volatile solid state memory.

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