KR20140103013A - Address access counter circuit and operating method thereof - Google Patents

Abstract

An address access counter circuit comprises an address division circuit which divides received address signals into several address segments; and multiple counter circuits which carry out counting of each of the address segments.

Description

[0001] DESCRIPTION [0002] ADDRESS ACCESS COUNTER CIRCUIT AND OPERATING METHOD THEREOF [0003]

An embodiment according to the inventive concept relates to an address access counter circuit and more particularly to an address access counter circuit capable of dividing an address signal into a plurality of address segments and performing a count operation on each of the divided address segments A counter circuit, a method of operating the same, and apparatuses including the same.

The address of the memory device is an identifier for the data storage location of the memory device. The address may be used in an access operation to the memory device, for example, a write operation that writes data to the memory device or a read operation that reads data stored in the memory device.

Because the address consists of a plurality of bits, a large number of counters are needed to count the number of accesses to all addresses of the memory device.

SUMMARY OF THE INVENTION The present invention is directed to an address access counter circuit capable of dividing an address signal into a plurality of address segments and performing a count operation on each of the divided address segments, And the like.

An address access counter circuit according to an embodiment of the present invention includes an address divider circuit for receiving an address signal and dividing the received address signal into a plurality of address segments and a divider circuit for each of the address segments And a plurality of counter circuits for performing a plurality of counter circuits.

According to an embodiment, each of the counter circuits may include a decoder for decoding each of the address segments and a plurality of counters for counting the number of times of detection of each of the sub-addresses corresponding to the decoding result.

According to the embodiment, each of the counter circuits may include: a counter circuit for comparing the count number of each of the plurality of counters with the reference count and for outputting a plurality of the sub addresses having the count number greater than the reference number, Of comparators.

According to an embodiment, each of the counter circuits may further comprise an encoder for encoding the sub-address output from any one of the plurality of comparators.

According to an embodiment, it may further comprise an address combination circuit for combining the sub-addresses output from the encoder included in each of the counter circuits to calculate a result address.

According to an embodiment, each of the counter circuits may further comprise a comparator, wherein each of the counter circuits compares the count number of each of the plurality of counters with each other.

According to an embodiment, the comparator may output a sub-address corresponding to the largest number of counts among the counts of the plurality of counters.

According to an embodiment, each of the counter circuits may further comprise an encoder for encoding the sub-address output from the comparator.

According to an embodiment, it may further comprise an address combination circuit for combining the sub-addresses output from the encoder included in each of the counter circuits to calculate a result address.

The memory controller according to an embodiment of the present invention may include the address access counter circuit.

The memory device according to an embodiment of the present invention may include the address access counter circuit and control logic for outputting the address signal.

The memory system according to an embodiment of the present invention may include the address access counter circuit, a memory controller outputting the address signal, and a memory device controlled by the memory controller.

A method of operation of an address access counter circuit in accordance with an embodiment of the present invention includes receiving an address signal comprising a plurality of address segments and counting a respective one of the address segments of the received address signal And < / RTI >

According to an embodiment, performing the counting operation may include decoding each of the address segments and counting the number of times of detection of the sub-address corresponding to the decoding result.

According to an embodiment, the step of performing the counting operation may further include a step of comparing the number of times of input of the counted sub-address with a reference count.

A method and apparatus in accordance with embodiments of the present invention divides an address signal into a plurality of address segments to perform a count operation on each of the divided address segments, The number of counters can be reduced.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to more fully understand the drawings recited in the detailed description of the present invention, a detailed description of each drawing is provided.
1 is a block diagram of a memory system in accordance with an embodiment of the present invention.
2 is a block diagram of a memory system in accordance with another embodiment of the present invention.
3 is a block diagram of a memory system in accordance with another embodiment of the present invention.
4 is a block diagram of a memory device including the address access counter circuit shown in FIG.
5 is a block diagram of the address access counter circuit shown in FIG.
6 is a block diagram according to one embodiment of the counter circuit shown in FIG.
7 is a diagram for explaining the operation of the plurality of counters and the plurality of comparators shown in FIG.
8 is a block diagram according to another embodiment of the counter circuit shown in FIG.
9 is a flowchart of an operation method of an address access counter circuit according to an embodiment of the present invention.
10 is a flowchart of an operation method of an address access counter circuit according to another embodiment of the present invention.
11 is a flowchart of an operation method of an address access counter circuit according to still another embodiment of the present invention.
12 is a conceptual diagram showing an embodiment of a package including the memory device shown in FIG.
FIG. 13 is a conceptual diagram that schematically shows an embodiment of a package including the memory device shown in FIG. 3; FIG.
FIG. 14 shows an embodiment of a system including the memory device shown in FIG.
FIG. 15 shows another embodiment of a system including the memory device shown in FIG.
16 shows another embodiment of a system including the memory device shown in FIG.
FIG. 17 shows another embodiment of a system including the memory device shown in FIG.
FIG. 18 shows another embodiment of a system including the memory device shown in FIG.
FIG. 19 shows another embodiment of a system including the memory device shown in FIG.

It is to be understood that the specific structural or functional description of embodiments of the present invention disclosed herein is for illustrative purposes only and is not intended to limit the scope of the inventive concept But may be embodied in many different forms and is not limited to the embodiments set forth herein.

The embodiments according to the concept of the present invention can make various changes and can take various forms, so that the embodiments are illustrated in the drawings and described in detail herein. It should be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms disclosed, but includes all modifications, equivalents, or alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms may be named for the purpose of distinguishing one element from another, for example, without departing from the scope of the right according to the concept of the present invention, the first element may be referred to as a second element, The component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises" or "having" and the like are used to specify that there are features, numbers, steps, operations, elements, parts or combinations thereof described herein, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning of the context in the relevant art and, unless explicitly defined herein, are to be interpreted as ideal or overly formal Do not.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings attached hereto.

1 is a block diagram of a memory system in accordance with an embodiment of the present invention.

Referring to Figure 1, a memory system 10A in accordance with an embodiment of the present invention may be implemented as a portable electronic device. The portable electronic device may be a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video a portable multimedia player (PMP), a personal navigation device or portable navigation device (PDN), a handheld game console, a mobile internet device (MID), or an e- But is not limited thereto.

The memory system 10A may include a host 100, a memory controller 200, a memory device 300, and an address access counter circuit 400. [

The memory controller 200 can control data communication between the host 100 and the memory device 300. [

The memory controller 200 controls the access operation to the memory device 300 under the control of the host 100 such as a write operation to write data to the memory device 300 or data stored in the memory device 300 It is possible to control the read operation for reading.

The memory device 300 is a medium for storing data, and may be embodied as a hard disk, a volatile memory device, or a non-volatile memory device according to an embodiment .

The volatile memory device may be implemented in a dynamic random access memory (DRAM), a static random access memory (SRAM), a thyristor RAM (T-RAM), a zero capacitor RAM (Z-RAM), or a twin transistor RAM But is not limited thereto.

The nonvolatile memory device may be an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic RAM, a spin-transfer torque MRAM, a conductive bridging RAM (CBRAM) a ferroelectric RAM, a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotube RRAM, a polymer RAM (PoRAM), a nano floating gate memory (NFGM) ), A holographic memory, a molecular electronics memory device, or an insulator resistance change memory, but is not limited thereto.

The address access counter circuit 400 may perform a count operation on each of the address segments included in the address signal based on the address signal transmitted from the memory controller 200. [

Herein, "performing a count operation on each of the address segments" means an operation of counting the number of times each of the address segments is input or detected, or a sub address corresponding to each of the address segments Quot;) may be counted. The address segments are described in detail with reference to FIGS. 5 and 6, and the sub-address is described in detail with reference to FIG.

2 is a block diagram of a memory system in accordance with another embodiment of the present invention.

1 and 2, a memory system 10B according to another embodiment of the present invention includes a memory system 200 'of FIG. 1, except that the memory controller 200' includes an address access counter circuit 400 10A). ≪ / RTI >

3 is a block diagram of a memory system in accordance with another embodiment of the present invention.

1 and 3, a memory system 10C according to another embodiment of the present invention includes a memory system 300 'of FIG. 1, except that the memory device 300' (10A).

4 is a block diagram of a memory device including the address access counter circuit shown in FIG.

Referring to FIGS. 3 and 4, the memory device 300 'may be implemented as a dynamic random access memory (DRAM), but is not limited thereto.

The memory device 300'includes control logic 310, a refresh counter circuit 320, a row multiplexer 322, a plurality of row buffers 324, And may include row decoders 326, bank control logic 328, a plurality of column buffers 330, a plurality of column decoders 332, a plurality of banks banks 340, an input / output gate 346, an input / output (I / O) interface 348, and an address access counter circuit 400.

The control logic 310 is responsive to a plurality of signals (a clock signal CK, a command signal CMD, and an address signal ADD) to control each component (e.g., the refresh counter circuit 320, (E.g., a row multiplexer 322, a bank control logic 328, and / or a plurality of column buffers 330).

The command signal CMD may refer to a combination of a plurality of instructions (e.g., CS, RAS, CAS, and / or WE). According to an embodiment, the command signal CMD and the address signal ADD may be transmitted from a memory controller (not shown) which controls the memory device 300 '.

The control logic 310 may include a command decoder 312. According to an embodiment, the command decoder 312 may be implemented outside of the control logic 310, but is not limited thereto.

The command decoder 312 decodes the command signal CMD composed of a combination of a plurality of instructions (e.g., CS, RAS, CAS, and / or WE) based on the clock signal CK, May generate instructions and / or addresses for controlling components (e.g., refresh counter circuitry 320, low multiplexer 322, bank control logic 328, or a plurality of column buffers 330) .

The refresh counter circuit 320 can transmit the row address related to the row to be subjected to the refresh operation to the row multiplexer 322 in response to the refresh command output from the command decoder 312. [

The row multiplexer 322 can select either the row address generated by the refresh counter circuit 320 and the row address output from the control logic 310. [

According to an embodiment, when a refresh operation is performed, the row multiplexer 322 may select the row address generated by the refresh counter circuitry 320. [

In accordance with another embodiment, when a normal memory access operation (e.g., a read operation or a write operation) is performed, the row multiplexer 322 may select the row address output from the control logic 310. [

Each of the plurality of row buffers 324 may buffer the row address output from the row multiplexer 322. According to an embodiment, the plurality of row buffers 324 may be implemented as one row buffer, but are not limited thereto.

The row decoder corresponding to the bank selected by the bank control logic 328 among the plurality of row decoders 326 can decode the row address output from the row buffer corresponding to the bank among the plurality of row buffers 324 have.

According to an embodiment, the plurality of row decoders 326 may be implemented as one row decoder, but is not limited thereto.

The bank control logic 328 may select a bank to access from among the plurality of banks 340 under the control of the control logic 310. [

Each of the plurality of column buffers 330 may buffer the column address output from the control logic 310. According to an embodiment, the plurality of column buffers 330 may be implemented as one column buffer, but are not limited thereto.

The column decoder corresponding to the bank selected by the bank control logic 328 among the plurality of column decoders 332 can decode the column address output from the column buffer corresponding to the bank among the plurality of column buffers 330 have.

According to an embodiment, the plurality of column decoders 332 may be implemented as one column decoder, but are not limited thereto.

Each of the banks 340 includes a memory cell array 342 and a sense amplifier & write driver block 342. The memory cell array 342 is labeled with banks Bank0 to BankN, ; 344).

For convenience of description, each of the plurality of banks 340 is implemented as a different layer. However, if the scope of the present invention is limited by the structure and arrangement of the plurality of banks 340 Can not be done.

The memory cell array 342 is connected to a plurality of word lines (or row lines), a plurality of bit lines (or column lines), and a plurality of word lines and the plurality of bit lines, And a plurality of memory cells for storing data.

The sense amplifier & write driver block 344 may operate as a sense amplifier that senses and amplifies the voltage change of each bit line when the memory device 300 'performs the read operation.

The sense amplifier & write driver block 344 may operate as a write driver capable of driving each of the plurality of bit lines included in the memory cell array 342 when the memory device 300 ' have.

The input / output gate 346 transmits data or signals output from the sense amplifier & write driver block 344 to the input / output interface 348 in response to the column selection signal output from any of the plurality of column decoders 332 .

According to the embodiment, the input / output gate 346 may transmit the data or signals input through the input / output interface 348 to the sense amplifier & write driver block 344 in response to the column select signal.

The input / output interface 348 may interface data input / output between the memory device 300 'and external devices.

The address access counter circuit 400 may receive the address signal ADD 'transmitted from the timing controller 310. [

According to an embodiment, the address signal ADD 'may be a row address signal and / or a column address signal.

FIG. 4 shows a case where the address access counter circuit 400 is included in the memory device 300 '. However, the address access counter circuit 400 may be implemented outside the memory device 300 'as in FIG. 1, or may be included in the memory controller 200' as in FIG. 2, but is not limited thereto.

Depending on the embodiment, the address access counter circuit 400 may be applied to various devices in which address signals are used in addition to the memory systems 10A to 10C.

The address access counter circuit 400 generates a result address signal RADD associated with the address having the highest access count or an address exceeding the reference access count based on the address signal ADD ' And generate a result address signal RADD.

The address access counter circuit 400 may transmit the generated result address signal RADD to the control logic 312. [

Figure 4 illustrates an embodiment in which the resulting address signal RADD is sent to the control logic 312. [ However, the resulting address signal RADD may be used for efficient address allocation of the memory device 300, but is not limited to, being transferred to the memory controller (200 in FIG. 1) and / or the host (100 in FIG.

The structure and operation of the address access counter circuit 400 will be described in detail with reference to Figs. 5 to 11. Fig.

5 is a block diagram of the address access counter circuit shown in FIG.

4 and 5, the address access counter circuit 400 includes an address segmentation circuit 410, a plurality of counter circuits 420-1 to 420-4, an address combination circuit 430 may be included.

5 to 8 show the address signal ADD '[0:11] when the address signal ADD' is 12 bits for the sake of convenience of description, but the technical scope of the present invention is not limited to the address signal ADD ' It should not be limited by the number of bits.

The address dividing circuit 410 receives the address signal ADD '[0:11] and outputs the received 12-bit address signal ADD' [0:11] to four address segments each having 3 bits (ADD '[0: 2], ADD' [3: 5], ADD '[6: 8], and ADD' [9:11].

For example, when the address signal ADD '[0:11] is' 010111001110', the first address segment ADD '[0: 2] is' 010' and the second address segment ADD '[3: 5 ] May be '111', the third address segment ADD '[6: 8] may be' 001 ', and the fourth address segment ADD' [9:11] may be '110'.

[0: 2], ADD '[3: 5], ADD' [6] generated by dividing the address signal ADD '[0:11] : 8], and ADD '[9:11]) and the pattern to be divided are merely examples, but the present invention is not limited thereto.

Each of the plurality of counter circuits 420-1 to 420-4 includes address segments ADD '[0: 2], ADD' [3: 5], ADD '[6: 8], and ADD' [9: 11], respectively.

Each of the plurality of counter circuits 420-1 to 420-4 includes a result address segment RADD [0: 2], RADD [3: 5], RADD [6: 8] [9:11]).

The resultant address segments RADD [0: 2], RADD [3: 5], RADD [6: 8], and RADD [9:11] and the plurality of counter circuits 420-1 through 420-4 Will be described in detail with reference to Figs. 6 to 8. Fig.

The address combination circuit 430 receives the result address segments RADD [0: 2], RADD [3: 5], RADD [6: 8] output from the plurality of counter circuits 420-1 to 420-4, , And RADD [9: 11]) to generate a result address signal RADD [0: 11].

The address combination circuit 430 may transmit the generated result address signal RADD [0: 11] to the control logic 310.

6 is a block diagram according to one embodiment of the counter circuit shown in FIG. 7 is a diagram for explaining the operation of the plurality of counters and the plurality of comparators shown in FIG.

5 and 6, a counter circuit 420-1A according to an embodiment of the counter circuit 420-1 shown in FIG. 5 includes an address decoder 422, a plurality of counters , 424-1 through 424-8, a plurality of comparators 426-1, and an address encoder 428. [

The address decoder 422 may receive the first address segment ADD '[0: 2] and may decode the received first address segment ADD' [0: 2]. The address decoder 422 instructs the counter corresponding to the first address segment ADD '[0: 2] among the plurality of counters 424-1 to 424-8 to detect that a specific address has been detected (E.g., a single pulse signal).

The first address segment ADD '[0: 2] may correspond to a sub-address corresponding to the first 3 bits of the entire address. That is, the sub-address may mean a part of the entire address.

Each of the plurality of counters 424-1 through 424-8 may correspond to each of the sub-addresses.

7, the first counter 424-1 corresponds to the sub-address '000', the second counter 424-2 corresponds to the sub-address '001', the third counter 424-3 corresponds to the sub- The fourth counter 424-4 corresponds to the sub-address '010', the fourth counter 424-4 corresponds to the sub-address '011', the fifth counter 424-5 corresponds to the sub-address '100' The eighth counter 424-8 corresponds to the sub-address '101', the seventh counter 424-7 corresponds to the sub-address '110', and the eighth counter 424-8 corresponds to the sub- have.

Each of the plurality of counters 424-1 through 424-8 counts accesses to the sub address corresponding to the decoded first address segment ADD '[0: 2], and outputs the count number in accordance with the count result, Lt; RTI ID = 0.0 > 426-1 < / RTI >

Each of the plurality of comparators 426-1 through 426-8 can compare the number of counts transmitted from each of the plurality of counters 424-1 through 424-8 with the reference count. That is, each of the plurality of comparators 426-1 through 426-8 can detect a sub address accessed more than the reference number.

Hereinafter, it is assumed that the reference number of each of the plurality of comparators 426-1 through 426-8 is 100 times.

Referring to FIG. 7, in the seventh comparator 426-7, since the number of counts received is 100, the sub address '110' can be detected as a sub address accessed more than the reference number. The seventh comparator 426-7 can output the detection signal to the address encoder 428 in accordance with the detection result.

The address encoder 428 generates a sub address (e.g., '110') corresponding to the one of the comparators based on the detection signal transmitted from any one of the plurality of comparators 426-1 through 426-8 To generate a first result address segment (RADD [0: 2]).

The address encoder 428 may output the generated first result address segment RADD [0: 2] to the address combination circuit 430. [

Referring to FIGS. 5 and 6, each of the remaining counter circuits 420-2 to 420-4 may operate as the counter circuit 420-1A.

In this case, the address combination circuit 430 receives the 3-bit result address segments RADD [0: 2], RADD [3: 5], RADD [ 6: 8], and RADD [9: 11]) to generate a 12-bit result address signal RADD [0:11]. That is, the result address signal RADD [0: 11] may indicate the address accessed more than the reference number.

For example, the first result address segment RADD [0: 2] is '110', the second result address segment RADD [3: 5] 8] is '111' and the fourth result address segment RADD [9: 11] is '000', the result address signal RADD [0:11] may be '110010111000'.

Each of the remaining counter circuits 420-2 to 420-4 may have the same structure as the counter circuit 420-1A.

In principle, 4096 (= 2 ^ 12) counters are needed to count the number of accesses to 12-bit addresses. However, the address access counter circuit (400 in Figs. 1 to 4) according to the embodiment of the present invention includes a total of 32 counters in order to count the number of accesses to 12-bit addresses. Therefore, the method and apparatus according to the embodiment of the present invention have the effect of reducing the chip size of the memory device.

8 is a block diagram according to another embodiment of the counter circuit shown in FIG.

5 through 8, the structure and operation of the counter circuit 420-B according to another embodiment of the counter circuit 420-1A shown in FIG. 5 is the same as that of the counter circuit 420-B except for the comparator 426 ' 420-1A, respectively.

The comparator 426 'may compare the number of counts transmitted from each of the plurality of counters 424-1 through 424-8 with each other. For example, comparator 426 'may detect the most accessed sub-address.

Referring to FIG. 7, in the case of the seventh counter 424-7, the count number is the largest value when compared with the count number of the other counters 424-1 to 424-6 and 424-8.

That is, comparator 426 'may detect sub-address' 110' as the most accessed sub-address. The comparator 426 'may output the detection signal to the address encoder 428 in accordance with the detection result.

The address encoder 428 may generate a first result address segment RADD [0: 2] indicating a sub-address corresponding to the detection signal, based on the detection signal transmitted from the comparator 426 '.

The address encoder 428 may output the generated first result address segment RADD [0: 2] to the address combination circuit 430. [

Referring to FIGS. 5 and 8, each of the remaining counter circuits 420-2 to 420-4 may operate as the counter circuit 420-1B.

In this case, the address combination circuit 430 receives the 3-bit result address segments RADD [0: 2], RADD [3: 5], RADD [ 6: 8], and RADD [9: 11]) to generate a 12-bit result address signal RADD [0:11]. That is, the result address signal RADD [0: 11] may indicate the most accessed address.

For example, the first result address segment RADD [0: 2] is '110', the second result address segment RADD [3: 5] 8] is '111' and the fourth result address segment RADD [9:11] is '000', the result address signal RADD [0:12] may be '110010111000'.

9 is a flowchart of an operation method of an address access counter circuit according to an embodiment of the present invention.

5 to 9, the address division circuit 410 receives an address signal (for example, ADD '[0:11]) (S10) Can be divided into a plurality of address segments (e.g., ADD '[0: 2], ADD' [3: 5], ADD '[6: 8], and ADD' [9:11]).

Each of the counter circuits 420-1 to 420-4 includes a plurality of divided address segments (e.g., ADD '[0: 2], ADD' [3: 5], ADD '[6: 8] '[9:11]) (S12).

10 is a flowchart of an operation method of an address access counter circuit according to another embodiment of the present invention.

5 to 10, the address dividing circuit 410 receives an address signal (for example, ADD '[0:11]) (S20) Can be divided into a plurality of address segments (e.g., ADD '[0: 2], ADD' [3: 5], ADD '[6: 8], and ADD' [9:11]).

Each of the counter circuits 420-1 to 420-4 includes a plurality of divided address segments (e.g., ADD '[0: 2], ADD' [3: 5], ADD '[6: 8] '[9:11]) (S22).

Each of the comparators (426-1 to 426-8 in FIG. 6) included in each of the counter circuits 420-1 to 420-4 can compare the count number with the reference number in accordance with the count operation result (S24).

11 is a flowchart of an operation method of an address access counter circuit according to still another embodiment of the present invention.

5 to 11, the address dividing circuit 410 receives an address signal (for example, ADD '[0:11]) (S30) Can be divided into a plurality of address segments (e.g., ADD '[0: 2], ADD' [3: 5], ADD '[6: 8], and ADD' [9:11]).

Each of the counter circuits 420-1 to 420-4 includes a plurality of divided address segments (e.g., ADD '[0: 2], ADD' [3: 5], ADD '[6: 8] '[9:11]) (S32).

6) included in each of the counter circuits 420-1 to 420-4 compares the counts transmitted from each of the plurality of counters (424-1 to 424-8 in Fig. 6) with each other (S34). That is, comparator 426 'may detect the most accessed sub-address.

12 is a conceptual diagram showing an embodiment of a package including the memory device shown in FIG.

3 and 12, the package 500 may include a plurality of semiconductor devices 530, 540, and 550 that are sequentially stacked on a package substrate 510. Each of the plurality of semiconductor devices 530 to 550 may be a memory device 300 '.

The package 500 may be a Package On Package (PoP), a Ball Grid Arrays (BGAs), a Chip Scale Packages (CSPs), a Plastic Leaded Chip Carrier (PLCC), a Plastic Dual In- , A thin-out-of-line package (CERDIP), a plastic metric quad flat pack (MQFP), a thin-flat flat pack (TQFP), a small-outline integrated circuit (SOIC), a shrink small outline package (SSOP) ), A system in package (SIP), a multi-chip package (MCP), a wafer-level package (WLP), or a wafer-level processed stack package (WSP).

In accordance with an embodiment, a memory controller (not shown) may be implemented within one or more semiconductor devices of the plurality of semiconductor devices 530-550, or may be implemented on the package substrate 510. [

For electrical connection between the plurality of semiconductor devices 530 to 550, electrical vertical connection means, such as TSV (Through-silicon via), may be used.

The package 500 may be implemented as a hybrid memory cube (hereinafter referred to as "HMC") having a structure in which a memory controller and a memory cell array die are stacked. By implementing the HMC, it is possible to reduce the power consumption and production cost by improving the performance of the memory device due to the increase in bandwidth, and minimizing the area occupied by the memory device.

FIG. 13 is a conceptual diagram that schematically shows an embodiment of a package including the memory device shown in FIG. 3; FIG.

3, 12, and 13, the package 500 'includes a plurality of dies 530 to 550 of a stacked structure connected to each other through respective TSVs 560.

FIG. 14 shows an embodiment of a system including the memory device shown in FIG.

Referring to Figures 3 and 12-14, the system 600 may be implemented as an electronic device or a portable device. The portable device may be implemented as a cellular phone, a smart phone, or a tablet PC.

System 600 includes a processor 611 and a memory device 613. The memory device 613 may be the memory device 300 'of FIG.

According to an embodiment, the processor 611 and the memory device 613 may be packaged into a package 610. In this case, the package 610 may be mounted on a system board (not shown). The package 610 may mean the package 500 shown in FIG. 12 or the package 500 'shown in FIG.

The processor 611 includes a memory controller 615 that can control the data processing operations of the memory device 613, such as a write operation or a read operation. The memory controller 615 is controlled by a processor 611 that controls the overall operation of the system 600. [ According to an embodiment, the memory controller 615 may be connected between the processor 611 and the memory device 613. [

The data stored in the memory device 613 can be displayed through the display 620 under the control of the processor 611. [

The wireless transceiver 630 may receive or receive a wireless signal via the antenna ANT. For example, the wireless transceiver 630 may convert the wireless signal received via the antenna ANT into a signal that the processor 611 can process. The processor 611 may thus process the signal output from the wireless transceiver 630 and store the processed signal in the memory device 613 or display it via the display 620. [

The radio transceiver 630 converts the signal output from the processor 611 into a radio signal and outputs the converted radio signal to the outside through the antenna ANT.

The input device 640 is a device capable of inputting a control signal for controlling the operation of the processor 611 or data to be processed by the processor 611 and includes a touch pad and a computer mouse May be implemented with the same pointing device, keypad, or keyboard.

The processor 611 is connected to the display 620 so that the data output from the memory device 613, the wireless signal output from the wireless transceiver 630, or the data output from the input device 640 can be displayed through the display 620. [ Can be controlled.

FIG. 15 shows another embodiment of a system including the memory device shown in FIG.

1, 12, 13 and 15, the system 700 includes a personal computer (PC), a tablet PC, a net-book, an e-reader, , A personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

The system 700 includes a processor 711 and a memory device 713 for controlling the overall operation of the system 700. The memory device 713 may refer to the memory device 300 'shown in FIG.

According to an embodiment, the processor 711 and the memory device 713 may be packaged into a package 710. The package 710 may be mounted on a system board (not shown). The package 710 may mean the package 500 shown in FIG. 12 or the package 500 'shown in FIG.

The processor 711 may include a memory controller 715 that controls the operation of the memory device 713.

The processor 711 may display data stored in the memory device 713 through the display 730 according to an input signal generated by the input device 720. For example, the input device 720 may be implemented as a pointing device, such as a touch pad or a computer mouse, a keypad, or a keyboard.

16 shows another embodiment of a system including the memory device shown in FIG.

3, 12, 13, and 16, the system 800 may be implemented as a memory card or a smart card.

The system 800 includes a memory device 813, a memory controller 811, and a card interface 810. The memory device 813 may refer to the memory device 300 'shown in FIG.

According to an embodiment, the memory device 813 and the memory controller 811 may be packaged into a package 810. The package 810 may be mounted on a system board (not shown). The package 810 may refer to the package 500 shown in FIG. 12 or the package 500 'shown in FIG.

The memory controller 811 can control the exchange of data between the memory device 813 and the card interface 820. [

According to an embodiment, the card interface 820 may be a secure digital (SD) card interface or a multi-media card (MMC) interface, but is not limited thereto.

The card interface 820 may interface data exchange between the host and the memory controller 811 according to the protocol of the host.

When the system 800 is connected to a host, such as a computer, a digital camera, a digital audio player, a mobile phone, a console video game hardware, or a digital set-top box, the host can interface with the card interface 820 and the memory controller 811, The data stored in the memory device 813 can be given or received.

FIG. 17 shows another embodiment of a system including the memory device shown in FIG.

Referring to Figures 3, 12, 13 and 17, the system 900 may be implemented as a digital camera or a portable device with a digital camera attached thereto.

The system 900 includes a processor 911 and a memory device 913 that control the overall operation of the system 900. At this time, the memory device 913 may refer to the memory device 300 'shown in FIG.

According to an embodiment, the processor 911 and the memory device 913 may be packaged into a package 910. The package 910 may be mounted on a system board (not shown). The package 910 may refer to the package 500 shown in FIG. 12 or the package 500 'shown in FIG.

The image sensor 920 of the system 900 converts the optical image into a digital signal and the converted digital signal is stored in the memory device 913 under control of the processor 911 or displayed through the display 930. In addition, the digital signal stored in the memory device 913 is displayed through the display 930 under the control of the processor 911.

FIG. 18 shows another embodiment of a system including the memory device shown in FIG.

3, 12, 13, and 18, the system 1000 includes a memory device 1013 and a processor 1011 that can control the overall operation of the system 1000. The memory device 1013 can refer to the memory device 300 'shown in FIG.

According to an embodiment, the memory device 1013 and the processor 1011 may be packaged into a package 1010. The package 1010 may be mounted on a system board (not shown). The package 1010 may refer to the package 500 shown in FIG. 12 or the package 500 'shown in FIG.

The processor 1011 includes a memory controller 1015 for controlling the operation of the memory device 1013.

The system 1000 includes a memory 1040 that can be used as an operation memory of the processor 1011. The memory 1040 may be implemented as a non-volatile memory such as read only memory (ROM) or flash memory.

A host connected to the system 1000 can receive or receive data with the memory device 1013 through the processor 1011 and the host interface 1030. [ At this time, the memory controller 815 can perform a function of a memory interface.

According to an embodiment, the system 1000 may further include an error correction code (ECC) block 1020.

The ECC block 1020 operating under the control of the processor 1011 can detect and correct errors contained in the data read from the memory device 1013 via the memory controller 1015. [

The processor 1011 can control the exchange of data between the ECC block 1020, the host interface 1030, and the memory 1040 via the bus 1001. [

The system 1000 may be implemented as a Universal Serial Bus (USB) memory drive or a memory stick.

FIG. 19 shows another embodiment of a system including the memory device shown in FIG.

The channel 1101 may refer to an optical connecting means. The optical connecting means may mean an optical fiber, an optical waveguide, or a medium for transmitting an optical signal.

Referring to FIGS. 3 and 19, the system 1100 may include a first system 1200 and a second system 1300.

The first system 1200 may include a first memory device 300a and an all-optical conversion circuit 1210. [ The all-optical conversion circuit 1210 converts the electrical signal output from the first memory device 300a into an optical signal and outputs the converted optical signal to the second system 1300 through the optical connecting means 1101 .

The second system 1300 includes a photoelectric conversion circuit 1320 and a second memory device 300b. The photoelectric conversion circuit 1320 can convert the optical signal inputted through the optical connecting means 1101 into an electric signal and transmit the converted electric signal to the second memory device 300b.

The first system 1200 may further include a photoelectric conversion circuit 1220 and the second system 1300 may further include an all-optical conversion circuit 1310. [

When the second system 1300 transmits data to the first system 1200, the all-optical conversion circuit 1310 converts the electrical signal output from the second memory device 300b into an optical signal, And output to the first system 1200 through the optical connecting means 1101. [ The photoelectric conversion circuit 1220 can convert the optical signal inputted through the optical connecting means 1101 into an electric signal and transmit the converted electric signal to the first memory device 300a. The structure and operation of each memory device 300a and 300b is substantially the same as the structure and operation of the memory device 300 'of FIG.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

10A, 10B, 10C: Memory system
100: Host
200, 200 ': memory controller
300, 300 ': memory device
400: address access counter circuit
410: address division circuit
420-1 to 420-4:
430: address combination circuit

Claims (10)

An address divider circuit for receiving the address signal and dividing the received address signal into a plurality of address segments; And
And a plurality of counter circuits, each of the counter circuits performing a count operation on each of the address segments. 2. The circuit of claim 1, wherein each of the counter circuits comprises:
A decoder for decoding each of the address segments; And
Each address counter circuit comprising a plurality of counters for counting the number of times of detection of a sub-address corresponding to a decoding result. 3. The circuit of claim 2, wherein each of the counter circuits comprises:
Further comprising a plurality of comparators each of which compares the count number of each of the plurality of counters with a reference number and outputs the sub address whose count number is larger than the reference number in accordance with the comparison result. 4. The circuit of claim 3, wherein each of the counter circuits comprises:
And an encoder to encode the sub-address output from any one of the plurality of comparators. 5. The method of claim 4,
And an address combination circuit for combining the sub-addresses output from the encoder included in each of the counter circuits to calculate a result address. 3. The circuit of claim 2, wherein each of the counter circuits comprises:
Further comprising a comparator that each compares the count number of each of the plurality of counters with each other. 7. The apparatus of claim 6,
And outputs a sub-address corresponding to the largest count number among the counts of the plurality of counters. 8. The circuit of claim 7, wherein each of the counter circuits comprises:
And an encoder to encode the sub-address output from the comparator. 9. The method of claim 8,
And an address combination circuit for combining the sub-addresses output from the encoder included in each of the counter circuits to calculate a result address. The method comprising: receiving an address signal comprising a plurality of address segments; And
And performing a count operation on each of the address segments of the received address signal.

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