KR20140075363A - Sense amplifier and semiconductor apparatus including the same - Google Patents

Abstract

The sense amplifier includes a data line connection part and a data transmission part. The data line connection unit connects the first data input / output line and the second data input / output line in response to the input / output switch signal having the first voltage level. The data transfer unit amplifies the first data input / output line in response to a level control signal having a sense amplifier enable signal and a second voltage level lower than the first voltage level.

Description

[0001] DESCRIPTION [0002] SENSE AMPLIFIER AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME [0003]

The present invention relates to a semiconductor device, and more particularly, to a sense amplifier of a semiconductor device.

2. Description of the Related Art A semiconductor device, particularly a memory, includes memory cells and a plurality of data input / output lines to perform data input / output operations. A bit line, a local input / output line, a global input / output line, and the like exist in the data input / output line where data moves. Since the paths through which data is input / output through the data input / output lines are quite long and the loads between the data input / output lines electrically connected are different from each other, the semiconductor memory device has a sense amplifier for amplifying data for smooth data transmission do.

FIG. 1 is a view showing a configuration of a conventional semiconductor memory device. 1, data stored in a memory cell (not shown) is loaded into bit lines BL and BLB and amplified by a bit line sense amplifier BLSA, and data of the bit lines BL and BLB are amplified by a bit line sense amplifier And transferred to the segment input / output lines (SIO, SIOB) by the column select signal CSL. Data transmitted to the segment input / output lines (SIO, SIOB) is amplified by the local sense amplifier (LSA) 10 and transmitted to the local input / output lines (LIO, LIOB). The data transmitted to the local input / output lines LIO and LIOB may be transmitted to a global input / output line (not shown) and output to the outside through a data pad (not shown). When the data is input, the data input path is opposite to the output path of the data.

FIG. 2 is a diagram showing a configuration of the local sense amplifier of FIG. 1; FIG. In FIG. 2, the local sense amplifier 10 includes first to seventh transistors N1 to N7. The first and second transistors N1 and N2 couple the segment input / output lines SIO and SIOB with the local input / output lines LIO and LIOB in response to an internal write signal WE. The third and fourth transistors N3 and N4 are respectively connected to the local input / output line in response to the internal read signal RD, and the fifth and sixth transistors N5 and N6 are connected to the segment input / SIO, and SIOB, and the seventh transistor N7 is turned on in response to the internal read signal RD to allow a current to flow to the ground voltage VSS. The internal read signal RD is a signal that enables the local sense amplifier 10 to perform the differential amplification operation on the segment input / output lines SIO and SIOB, and is also referred to as a sense amplifier enable signal LSAEN. The local sense amplifier 10 has a structure capable of separately performing a write operation and a read operation. Particularly, in a write operation, data is transferred by connecting the local input / output lines LIO and LIOB with the segment lines SIO and SIOB. In the read operation, data of the segment input / output lines SIO and SIOB are differential And transfers the amplified data to the local input / output lines LIO and LIOB. That is, the local sense amplifier LSA of the prior art can be connected to the segment input / output lines SIO and SIOB only when the internal write signal WE or the internal read signal RD is applied, and the local input / output lines LIO and LIOB ).

Embodiments of the present invention provide a sense amplifier and a semiconductor memory device including the same that can accurately operate at high speed while reducing current consumption.

A sense amplifier according to an embodiment of the present invention includes a data line connection unit for connecting a first data input / output line and a second data input / output line in response to an input / output switch signal having a first voltage level; And a data transfer unit for amplifying the first data input / output line in response to a level control signal having a sense amplifier enable signal and a second voltage level lower than the first voltage level.

The semiconductor device according to another embodiment of the present invention differs from the first data input / output line in the read operation by transferring the data of the first data input / output line to the second data input / output line and performing the differential amplification operation in the write operation, And a sense amplifier for transmitting data of the first data input / output line to the first data input / output line.

Also, the semiconductor device according to another embodiment of the present invention connects the first and second data input / output lines to each other during the active operation, and performs differential amplification of the data of the first data input / output line in response to the sense amplifier enable signal in the read operation And a sense amplifier for transmitting the data to the second data input / output line and maintaining the swing width of the second data input / output line constant in response to the level control signal.

According to the embodiment of the present invention, the skew of the signal for controlling the sense amplifier and the pre-charge unit is removed, and the pre-charge effect of the data input / output line is enhanced, so that the correct read or write operation can be performed. Therefore, continuous read or write operation is possible, which is advantageous for high-speed operation. In addition, it is possible to optimize the level of the control signal for controlling the sense amplifier, thereby reducing current consumption occurring in the sense amplifier operation.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a configuration of a conventional semiconductor memory device,
FIG. 2 is a diagram showing the configuration of the local sense amplifier of FIG. 1,
3 is a view showing a configuration of a semiconductor device including a sense amplifier according to an embodiment of the present invention,
FIG. 4 is a diagram showing a configuration of an embodiment of a driver block for generating a sense amplifier enable signal and a precharge signal of FIG. 3;
5 is a diagram showing the configuration of an embodiment of a level converter for generating the level control signal of FIG. 3,
6 is a block diagram schematically showing a configuration of a semiconductor device according to an embodiment of the present invention.
7 is a timing diagram showing the operation of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a diagram schematically showing a configuration of a semiconductor device including a sense amplifier 100 according to an embodiment of the present invention. 3, the sense amplifier 100 according to the embodiment of the present invention transmits data from the first data input / output line (SIO, SIOB) to the second data input / output line (LIO, LIOB) LIO, LIOB) to the first data input / output line (SIO, SIOB). The sense amplifier 100 substantially maintains the connection of the first and second data input / output lines SIO, SIOB, LIO, and LIOB during the active operation of the semiconductor device.

The sense amplifier 100 performs data transfer between the first and second data input / output lines SIO, SIOB, LIO, and LIOB when the read and write operations of the semiconductor device are performed. The sense amplifier 100 may differentially amplify the data of the first data input / output line (SIO, SIOB) during a read operation and transmit the data to the second data input / output line (LIO, LIOB). The sense amplifier 100 can differentially amplify the data of the first data input / output lines SIO and SIOB in response to a sense amplifier enable signal LSAEND in a read operation. Also, the sense amplifier 100 may adjust the swing width of the second data input / output lines LIO and LIOB in response to the level control signal LE.

The sense amplifier 100 transmits data of the second data input / output lines LIO and LIOB to the first data input / output lines SIO and SIOB without performing the differential amplification operation in a write operation. In the semiconductor device, the loading of the second data input / output line (LIO, LIOB) is smaller than the loading of the first data input / output line (SIO, SIOB). Therefore, when data is transferred from the second data input / output line (LIO, LIOB) to the first data input / output line (SIO, SIOB), the sense amplifier 100 consumes an unnecessary current to perform the differential amplification operation . The sense amplifier 100 does not perform the differential amplification operation in the write operation but maintains the connection of the first and second data input / output lines SIO, SIOB, LIO, and LIOB during the active operation, So that the data of the second data input / output line (LIO, LIOB) can be accurately transmitted to the first data input / output line (SIO, SIOB).

The sense amplifier 100 includes a data line connection unit 110 and a data transmission unit 120. 3, the data line transfer unit 110 connects the first data input / output line (SIO, SIOB) and the second data input / output line (LIO, LIOB) in response to an input / output switch signal IOSW. Accordingly, when the input / output switch signal IOSW is enabled, the data (or signal) of the second data input / output line LIO or LIOB is transmitted to the first data input / output line SIO or SIOB . Alternatively, data (or signal) of the first data input / output line (SIO, SIOB) may be transmitted to the second data input / output line (LIO, LIOB).

The data transfer unit 120 is connected to the first and second data input / output lines SIO, SIOB, LIO, and LIOB in response to a level control signal LE. The data transfer unit 120 responds to a sense amplifier enable signal LSAEND And differential-amplifies the first data input / output line (SIO, SIOB). When the sense amplifier enable signal LSAEND is enabled, the data transfer unit 120 differentially amplifies the data of the first data input / output line SIO, and outputs the amplified data to the second data input / (LIO, LIOB). The data transfer unit 120 changes the levels of the second data input / output lines LIO and LIOB according to a result of differential amplification of data of the first data input / output line SIO and the second data input / output line SIOB, And maintains the swing width of the second data input / output lines (LIO, LIOB) constant in response to the signal LE.

In the embodiment of the present invention, the input / output switch signal IOSW is a signal for selecting the second data input / output line (LIO, LIOB), and may be generated from an active signal and a signal for selecting a row. Further, the active signal is a signal that can be generated in response to an active command from the outside (or controller) so that the semiconductor device is activated in order to perform a read or write operation in a precharge state. The row select signal may be a signal for selecting a row of a memory block of the semiconductor device, for example, a signal for selecting a word line.

The data line connection unit 110 of the sense amplifier 100 connects the first and second data input / output lines SIO, SIOB, LIO and LIOB in response to the input / output switch signal IOSW, The first data input / output line (SIO, SIOB) is continuously connected to the second data input / output line (LIO, LIOB).

The level control signal LE may be generated from the active signal and the row select signal in the same manner as the input / output switch signal IOSW. However, the level control signal LE is generated at a voltage level different from that of the input / output switch signal IOSW. In an embodiment of the present invention, the input / output switch signal IOSW has a first voltage level, and the level control signal LE has a second voltage level. For example, the first voltage level may be a power supply voltage level, and the second voltage level may be an internal voltage (VINT) level. The power supply voltage input to the semiconductor device may be fluctuated in level due to high voltage application and noise. Therefore, when a high level power supply voltage is applied, the swing width of the second data input / output lines (LIO, LIOB) becomes abnormally large, thus consuming an unnecessary current. However, a constant voltage level is maintained regardless of the level variation of the power supply voltage of the internal voltage VINT. Accordingly, the data transfer unit 120 may receive the level control signal LE to maintain the swing width of the second data input / output lines LIO and LIOB constant. The level control signal LE may be generated using, for example, a core voltage used in a memory bank and a peripheral circuit portion of a semiconductor device.

The sense amplifier enable signal LSAEND may be generated from the internal read signal. The internal lead signal is a signal generated internally when a read command is applied from the outside (or a controller) for the semiconductor device to perform the read operation. Also, the sense amplifier enable signal LSAEND may be generated from the internal read signal and the internal sense amplifier enable signal. A general semiconductor device generates an internal read signal and an internal write signal inside a semiconductor device when receiving a read or write command to perform a read or write operation and outputs the internal sense amplifier enable signal from the internal lead and write signal . As described in more detail below, in the embodiment of the present invention, the sense amplifier enable signal LSAEND does not change the structure of a general semiconductor device, but combines the internal lead signal and the internal sense amplifier enable signal, So that the sense amplifier enable signal LSAEND can be generated.

In Fig. 3, the semiconductor device further includes a precharge section 200. Fig. The precharge section 200 precharges the first data input / output line (SIO, SIOB) in response to a precharge signal (SIOPC). The precharge section 200 provides the internal voltage VINT to the first data input / output line SIO and the first data input / output line SIO in response to the precharge signal SIOPC, To be precharged to the internal voltage (VINT) level. The internal voltage VINT may be, for example, a core voltage used in the memory bank of the semiconductor device 1 and peripheral circuitry. The precharge signal SIOPC is a signal that can be generated from the internal precharge signal and is generated when the semiconductor device 1 receives an active command from the outside (or controller) like the input / output switch signal IOSW Signal. The precharge signal SIOPC is a signal that can be deactivated when the semiconductor device receives a read or write command from the outside (or a controller) to generate the internal read signal or the internal write signal.

Although not shown in FIG. 3, since the input / output switch signal IOSW is generated from an active signal or a signal for row selection, the input / output switch signal IOSW can be generated from the row decoder block of the semiconductor device, The charge signal may be generated from the column decoder block of the semiconductor device. More details will be described later.

In FIG. 3, the data line connection part 110 includes first and second NMOS transistors N11 and N12. The first NMOS transistor N11 receives the input / output switch signal IOSW as a gate and outputs the first and second data input / output lines SIO and LIO when the input / output switch signal IOSW is enabled Connect. The second NMOS transistor N12 receives the input / output switch signal IOSW to a gate and outputs the first and second data input / output lines SIOB and LIOB when the input / output switch signal IOSW is enabled Connect.

The data transmission unit 120 includes a differential amplification unit 121 and a swing width control unit 122. The differential amplifier 121 differential-amplifies the data of the first data input / output line (SIO, SIOB) in response to the sense amplifier enable signal (LSAEND). The swing width adjuster 122 may connect the differential amplifier 121 and the second data input / output lines LIO and LIOB to each other in response to the level control signal LE. In addition, the swing width adjuster 122 may maintain a constant swing width of the second data input / output lines LIO and LIOB in response to the level control signal LE. That is, the swing width controller 122 prevents the swing width of the second data input / output lines LIO and LIOB from being excessively changed by the signal amplified by the differential amplifier 121. The swing width adjuster 122 limits the excessively amplified signal to a predetermined reference or less by the level control signal LE to prevent the swing width of the second data input / output lines LIO and LIOB from becoming large.

3, the differential amplifier 121 may include a third NMOS transistor N13, a fourth NMOS transistor N15, and a fifth NMOS transistor N15. The third NMOS transistor N13 has a gate connected to the first data input / output line SIO and one end connected to one end of the fifth NMOS transistor N15. The fourth NMOS transistor N14 is connected to the first data input / output line SIOB, and the other end of the fifth NMOS transistor N15 is connected to the other end of the fifth NMOS transistor N15. The fifth NMOS transistor N15 receives the sense amplifier enable signal LSAEND as a gate and has one end commonly connected to one end of the third and fourth NMOS transistors N13 and N14, The terminal is connected to the ground voltage VSS.

The swing width adjuster 122 includes sixth and seventh NMOS transistors N16 and N17. The sixth NMOS transistor N16 receives the level control signal LE at its gate and has one end connected to the second data input / output line LIOB and the other end connected to the third NMOS transistor N13. . The seventh NMOS transistor N17 receives the level control signal LE at its gate and has one end connected to the second data input / output line LIO and the other end connected to the fourth NMOS transistor N14 ).

In the active operation, when the level control signal LE is enabled, the sixth and seventh NMOS transistors N16 and N17 are both turned on. When the sense amplifier enable signal LASEND is enabled in the read operation, the fifth NMOS transistor N15 is turned on. At this time, the third and fourth NMOS transistors N13 and N14 are complementarily turned on according to the data level of the first data input / output line SIO and the first data input / output line SIO, Differential amplification of the data can be performed. At this time, the amount of current flowing through the sixth and seventh NMOS transistors N16 and N17 may be limited by the level control signal LE. That is, the sixth and seventh NMOS transistors N16 and N17 can be reduced in current driving capability when receiving the level control signal LE, rather than receiving the input / output switch signal IOSW to the gate have. Therefore, the sixth and seventh NMOS transistors N16 and N17 transmit the signals amplified by the differential amplifier 121 to the second data input / output lines LIO and LIOB with a reduced current driving capability, respectively , The swing width of the second data input / output lines (LIO, LIOB) can be kept constant.

The precharge section 200 includes a first PMOS transistor P11, a second PMOS transistor P12, and a third PMOS transistor P13. The first to third PMOS transistors P11 to P13 receive the precharge signal SIOPC at a gate and output the internal voltage VINT when the precharge signal SIOPC is enabled, Output line (SIO, SIOB), and precharges the first data input / output line (SIO, SIOB).

The sense amplifier 100 is configured to substantially simultaneously switch the first data input / output line (SIO, SIOB) and the second data input / output line (LIO, LIOB) in response to the input / output switch signal IOSW during the active operation of the semiconductor device Continuously connect. Therefore, if the precharge section 200 precharges the first data input / output line (SIO, SIOB), the effect of precharging the first data input / output line (SIO, SIOB) , LIOB). Therefore, the semiconductor device according to the embodiment of the present invention further facilitates the precharging of the second data input / output lines LIO and LIOB, and the first and second data input / output lines SIO, SIOB and LIO , LIOB) can be accurately performed.

FIG. 4 is a diagram showing a configuration of an embodiment of driver blocks 410 and 420 for generating the sense amplifier enable signal LSAEND and the precharge signal SIOPC of FIG. The driver block 410 includes a first NAND gate 411 and a first inverter 412. The first NAND gate 411 receives an internal sense amplifier enable signal LSAEN, an input / output switch control signal IOSW, and an internal read signal RD. The first inverter 412 inverts the output of the first NAND gate 411 to generate the sense amplifier enable signal LSAEND. The internal sense amplifier enable signal LSAEN may be generated in a read and write operation, the input / output switch control signal IOSW may remain enabled during an active operation, Lt; / RTI > Therefore, the sense amplifier enable signal LSAEND can be generated only in the read operation.

The driver block 420 includes a second NAND gate 421. The second NAND gate 421 receives the internal precharge signal SIOPCB and the input / output switch signal IOSW to generate the precharge signal SIOPC. The driver blocks 410 and 420 generate a sense amplifier enable signal LSAEND and a precharge signal SIOPC used in a semiconductor device according to an embodiment of the present invention by using signals used in a general semiconductor device Was presented. However, the present invention is not intended to be limited to the configuration shown in FIG. 4, and may be implemented in various ways.

5 is a diagram showing a configuration of an embodiment of a level converter 500 for generating the level control signal LE of FIG. The level limiting unit 500 may receive the input / output switch signal IOSW to generate the level control signal LE. The level conversion unit LE converts the input / output switch signal IOSW having a power supply voltage level into the level control signal LE having an internal voltage VINT level. Thus, the level converter 500 may be enabled during an active operation and generate the level control signal LE having an internal voltage (VINT) level.

6 is a view showing a configuration of a semiconductor device 1 according to an embodiment of the present invention. 6, the semiconductor device 1 includes a plurality of memory blocks MB, a local sense amplifier block S / A, a column decoder block Y-DEC, and driver blocks 410 and 420. Referring to FIG. 3, the plurality of memory blocks MB includes a plurality of bit lines BL and BLB that communicate with memory cells provided therein. 6, the memory cell may communicate with the bit lines BL and BLB through a bit line sense amplifier BLSA, and the first data input / output lines SIO and SIOB may be connected to the column select signal / And may be connected to the bit lines BL and BLB according to the bit line YI.

The first data input / output line (SIO, SIOB) is connected to the second data input / output line (LIO, LIOB) through the sense amplifier block (S / A). The sense amplifier block S / A corresponds to the number of the first and second data input / output lines SIO, SIOB, LIO and LIOB in the sense amplifier 100 and the precharge section 200 of FIG. And a plurality of units may be provided.

The column decoder block (Y-DEC) generates a column address signal for column selection of the semiconductor device (1). Also, in the embodiment of the present invention, the column decoder block Y-DEC generates the internal sense amplifier enable signal LSAEN and the internal precharge signal SIOPCB. As described above, the internal sense amplifier enable signal LSAEN and the internal precharge signal SIOPCB may be generated internally in the semiconductor device 1 in response to an active command, a read command, or a write command. The column decoder block Y-DEC is configured to generate the internal sense amplifier enable signal LSAEN and the internal precharge signal SIOPC. Since the internal sense amplifier enable signal LSAEN and the internal precharge signal SIOPCB are generated in the column decoder block Y-DEC, the column select signal for selecting the column of the semiconductor device 1 Lt; RTI ID = 0.0 > YI) < / RTI > Therefore, in performing the read or write operation, signals related to the read or write operation can be transmitted in the same direction, so that a more accurate read or write operation can be performed and the operation time can be accurately ensured.

The driver blocks 410 and 420 are located in a cross area A between the memory blocks MB. The intersecting region A is a region located between the memory blocks MB at the intersection of the X direction and the Y direction. The driver blocks 410 and 420 receive the internal sense amplifier enable signal LSAEN, the internal read signal RD, the internal precharge signal SIOPCB, and the input / output switch signal IOSW, The enable signal LSAEND and the precharge signal SIOPC. The driver blocks 410 and 420 are located in the intersection area A of the semiconductor device 1 and are connected to the row decoder block, that is, the I / O switch signal IOSW transmitted from the X direction and the column decoder block, Amplifies and drives the internal sense amplifier enable signal LSAEN and the internal precharge signal SIOPCB transmitted from the Y direction to the sense amplifier block S / A. 6, the driver block 410 drives the internal sense amplifier enable signal LSAEN to generate the sense amplifier enable signal LSAEND, and the driver block 420 outputs the internal precharge signal SIOPCB) to generate the precharge signal SIOPC. Therefore, the driver block 410 provides the sense amplifier enable signal LSAEND to both the sense amplifier blocks S / A, and the driver block 320 outputs the sense amplifier enable signal LSAEND, And provides the precharge signal SIOPC to the amplifier block S / A. However, the arrangement of the driver blocks 410 and 420 is not limited. That is, the driver block 420 for driving the internal precharge signal SIOPCB to generate the precharge signal SIOPC is positioned at the same position as the driver block 410 for generating the sense amplifier enable signal LSAEN And can provide the precharge signal SIOPC to both sense amplifier blocks S / A.

7 is a timing chart showing the operation of the semiconductor device 1 according to the embodiment of the present invention. The operation of the semiconductor device 1 according to the embodiment of the present invention will now be described with reference to FIGS. 3 to 7. FIG. When the active command ACT is applied from the outside, the active operation of the semiconductor device 1 is performed, and the input / output switch signal IOSW and the level control signal LE are enabled. The first and second NMOS transistors N11 and N12 of the data line connection unit 110 are received and turned on by the input / output switch signal IOSW, and the sixth and seventh energies of the swing- The MOS transistors N16 and N17 receive the level control signal LE and are turned on. Therefore, the first data input / output line (SIO, SIOB) is connected to the second data input / output line (LIO, LIOB). The internal precharge signal SIOPCB and the input / output switch signal IOSW are driven by the driver block 420 to generate the precharge signal SIOPC. The first data input / output line SIO, Precharged to the internal voltage (VINT) level. Since the first data input / output line SIO and the second data input / output line SIOB are connected to the second data input / output lines LIO and LIOB, the precharge section 200 is connected to the first data input / To the second data input / output line (LIO, LIOB). Therefore, precharging of the second data input / output lines (LIO, LIOB) can be assisted.

Thereafter, when the read command (READ) is applied, the column select signal YI, the internal sense amplifier enable signal LSAEN and the internal read signal RD are generated, and the internal precharge signal SIOPCB is And is disabled. The driver blocks 410 and 420 drive the internal sense amplifier enable signal LSAEN, the internal read signal RD, the internal precharge signal SIOPCB, and the input / output switch signal IOSW, The enable signal LSAEND is enabled, and the precharge signal SIOPC is disabled. Therefore, the first to third PMOS transistors P11 to P13 of the precharge section 200 are all turned off, and the precharging state of the first data input / output line SIO, SIOB is released. The data of the bit lines BL and BLB amplified by the bit line sense amplifier BLSA is transferred to the first data input / output line SIO. SIOB when the column select signal is enabled. The fifth NMOS transistor N15 receives the sense amplifier enable signal LSAEND and is turned on so that the differential amplifier 121 amplifies the data loaded on the first data input / Respectively. The sixth and seventh NMOS transistors N16 and N17 of the swing width controller 122 receive the differential amplified signal from the second data input / output lines LIO and LIOB in response to the level control signal LE, To transfer the data of the first data input / output line (SIO, SIOB) to the second data input / output line (LIO, LIOB).

Thereafter, when the write command WRITE is applied, the driver block 410 does not enable the sense amplifier enable signal LSAEND because the internal read signal RD is not enabled. Therefore, data of the second data input / output lines LIO and LIOB can be transmitted to the first data input / output line SIO through the data line connection unit 110, , SIOB) can be transferred to the bit lines BL and BLB by the column select signal YI.

When the precharge command PCG is applied, the input / output switch signal IOSW and the level control signal LE are disabled, and the first data input / output line SIO and the second data input / The connection of the lines (LIO, LIOB) is released.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

1: Semiconductor device 100: Sense amplifier
110: Data line connection part 120: Data transmission part
121: Differential amplifier 122: Swing width adjuster
200: Free car part 410/420: Driver block
500: level conversion section

Claims (19)

A data line connection unit connecting a first data input / output line and a second data input / output line in response to an input / output switch signal having a first voltage level; And
And a data transfer section for amplifying the first data input / output line in response to a level control signal having a sense amplifier enable signal and a second voltage level lower than the first voltage level. The method according to claim 1,
Wherein the input / output switch signal is generated based on an active signal or a signal for row selection. The method according to claim 1,
And the sense amplifier enable signal is generated based on the read command. The method according to claim 1,
Wherein the level control signal is generated based on an active signal or a signal for row selection. The method according to claim 1,
Wherein the level control signal is generated from an internal voltage whose voltage level is kept constant regardless of a level change of the power supply voltage. The method according to claim 1,
Wherein the data transfer unit includes: a differential amplification unit for performing differential amplification on data of the first data input / output line in response to the sense amplifier enable signal; And
And a swing width adjuster for connecting the differential amplifier and the second data input / output line in response to the level control signal and maintaining the swing width of the second data input / output line constant. The data of the first data input / output line is differentially amplified and transmitted to the second data input / output line in the read operation, and the data of the second data input / output line is transmitted to the first data input / output line without performing the differential amplification operation in the write operation And a sense amplifier connected to the sense amplifier. 8. The method of claim 7,
Wherein the first data input / output line is substantially continuously connected to the second data input / output line during an active operation. 8. The method of claim 7,
And the sense amplifier connects the first and second data input / output lines in response to an input / output switch signal for selecting the second data input / output line. 10. The method of claim 9,
Wherein the input / output switch signal is generated from an active signal or a signal for row selection. 8. The method of claim 7,
Wherein the sense amplifier differentially amplifies the data of the first data input / output line in response to a sense amplifier enable signal enabled in the read operation. 12. The method of claim 11,
And the sense amplifier enable signal is not enabled in the write operation. 8. The method of claim 7,
Wherein the sense amplifier maintains a constant swing width of the second data input / output line in response to a level control signal in the read operation. 14. The method of claim 13,
Wherein the level control signal is generated from an internal voltage that maintains a constant voltage level regardless of a level change of the power supply voltage. 8. The method of claim 7,
And a precharging unit for precharging the first input / output line during an active operation except when the read and write operations are performed. Output lines during the active operation, differentially amplifies the data of the first data input / output line in response to the sense amplifier enable signal in the read operation, and transmits the differential amplified data to the second data input / output line, And a sense amplifier which keeps the swing width of the second data input / output line constant in response to the second data input / output line. 17. The method of claim 16,
Wherein the sense amplifier transfers data of the second data input / output line to the first data input / output line without performing a differential amplification operation in a write operation. 17. The method of claim 16,
Wherein the sense amplifier includes: a differential amplifier for differentially amplifying the first data input / output line in response to the sense amplifier enable signal in a read operation; And
And a swing width adjusting unit for connecting the differential amplifying unit and the second data input / output unit in response to the level control signal. 19. The method of claim 18,
Wherein the level control signal is generated from an internal voltage that maintains a constant voltage level regardless of a level change of the power supply voltage.

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